ARM: Handle accesses to TTBR0 and TTBR1.

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 52329a3dcb663b9c95fa8274f23175d76b45620b..f43b55271026d52c951c30dad6d3dac40d835652 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -106,6 +106,8 @@ namespace ArmISA
         MISCREG_BPIALLIS,
         MISCREG_BPIALL,
         MISCREG_MIDR,
+        MISCREG_TTBR0,
+        MISCREG_TTBR1,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TLBTR,
@@ -142,8 +144,6 @@ namespace ArmISA
         MISCREG_SCR,
         MISCREG_SDER,
         MISCREG_NSACR,
-        MISCREG_TTBR0,
-        MISCREG_TTBR1,
         MISCREG_TTBCR,
         MISCREG_V2PCWPR,
         MISCREG_V2PCWPW,
@@ -198,7 +198,7 @@ namespace ArmISA
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "midr", "ctr", "tlbtr", "tcmtr", "mpidr",
+        "midr", "ttbr0", "ttbr1", "ctr", "tlbtr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -206,7 +206,7 @@ namespace ArmISA
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
-        "scr", "sder", "nsacr", "ttbr0", "ttbr1", "ttbcr",
+        "scr", "sder", "nsacr", "ttbcr",
         "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
         "v2powpr", "v2powpw", "v2powur", "v2powuw",
         "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",