i965: move exec_size from fs_instruction to backend_instruction

We are going to need this in the vec4 backend too.

Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 16ee3d2906c29e76aa2b571a5eb31d79b2f3fe36..c569bd473d76cb6ee05785d524b5c52074a8e4e6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -367,13 +367,6 @@ public:
 
    uint8_t sources; /**< Number of fs_reg sources. */
 
-   /**
-    * Execution size of the instruction.  This is used by the generator to
-    * generate the correct binary for the given fs_inst.  Current valid
-    * values are 1, 8, 16.
-    */
-   uint8_t exec_size;
-
    /**
     * Channel group from the hardware execution and predication mask that
     * should be applied to the instruction.  The subset of channel enable

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e8b34d59ab60ceeb160bbe8793c295e2fe8f0ccb..b5af6ab841f03dfc646d2a178a1ed062d839fc20 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -133,6 +133,13 @@ struct backend_instruction {
    const char *annotation;
    /** @} */
 
+   /**
+    * Execution size of the instruction.  This is used by the generator to
+    * generate the correct binary for the given instruction.  Current valid
+    * values are 1, 4, 8, 16, 32.
+    */
+   uint8_t exec_size;
+
    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
    uint8_t mlen; /**< SEND message length */
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c615ac0bca0417954d2c3bfc91591ec091bf96ed..e88bb7c7e4b14bbe4e947b3d78e579be9de9ab1a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -55,6 +55,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
    this->mlen = 0;
    this->base_mrf = 0;
    this->offset = 0;
+   this->exec_size = 8;
    this->annotation = NULL;
 }