add fields for 3R1W

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 0bba849233d1d62a780b4d9f2db9e4e9be7e1692..5e650b1134a92afd0c582b755b1c69ec6cbaccef 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -38,15 +38,30 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | MASK                         | `1:3`      | Execution Mask                                                            |
 | ELWIDTH                      | `4:5`      | Element Width                                                             |
 | SUBVL                        | `6:7`      | Sub-vector length                                                         |
-| Rdest_EXTRA                  | `8:10`     | extra bits for Rdest                                                      |
-| Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1                                                      |
-| Rsrc2_EXTRA                  | `14:16`    | extra bits for Rsrc2                                                      |
-| Rsrc3_EXTRA                  | `17:19`    | extra bits for Rsrc3                                                      |
+| Rdest_EXTRA                  | `8:10`     | extra bits for Rdest (Uses R\*_EXTRA Encoding)                            |
+| Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
+| Rsrc2_EXTRA                  | `14:16`    | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding)                            |
+| Rsrc3_EXTRA                  | `17:19`    | extra bits for Rsrc3 (Uses R\*_EXTRA Encoding)                            |
 | MASK_SRC                     | `14:16`    | Execution Mask for Source (only on instructions with twin-predication)    |
 | ELWIDTH_SRC                  | `17:18`    | Element Width for Source (only on instructions with twin-predication)     |
 | SUBVL_SRC                    | `19:20`    | Sub-vector length for Source (only on instructions with twin-predication) |
 | TBD                          | `21:23`    | TBD                                                                       |
 
+## R\*_EXTRA Encoding
+
+In the following table, `<N>` denotes the value of the corresponding register field in the SVP64 suffix word. 
+
+| R\*_EXTRA | Vector/Scalar<br/>Mode | CR Register   | Int/FP<br/>Register |
+|-----------|------------------------|---------------|---------------------|
+| 000       | Scalar                 | `SVCR<N>_000` | `SV[F]R<N>_00`      |
+| 001       | Scalar                 | `SVCR<N>_010` | `SV[F]R<N>_01`      |
+| 010       | Scalar                 | `SVCR<N>_100` | `SV[F]R<N>_10`      |
+| 011       | Scalar                 | `SVCR<N>_110` | `SV[F]R<N>_11`      |
+| 100       | Vector                 | `SVCR<N>_000` | `SV[F]R<N>_00`      |
+| 101       | Vector                 | `SVCR<N>_010` | `SV[F]R<N>_01`      |
+| 110       | Vector                 | `SVCR<N>_100` | `SV[F]R<N>_10`      |
+| 111       | Vector                 | `SVCR<N>_110` | `SV[F]R<N>_11`      |
+
 ## ELWIDTH Encoding
 
 | Instruction Kind | ELWIDTH Value | Mnemonic                  | Description                                                                         |
@@ -171,7 +186,7 @@ There are two different encodings: single-predication (typically arithmetic oper
 
 # Register Naming
 
-SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.
+SV Registers are numbered using the notation `SV[F|C]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.
 
 For all `SV[F|C]R<N>_<M>` registers, the N is the
 upper bits in decimal and the M is the lower bits in binary, so `SVR5_01` is
@@ -457,6 +472,6 @@ TBD
 
 Remapped Encoding Fields:
 
-|  |
-|--|
-|  |
+| `0`       | `1:3` | `4:5`   | `6:7` | `8:10`      | `11:13`     | `14:16`     | `17:19`     | `20:23`  |
+|-----------|-------|---------|-------|-------------|-------------|-------------|-------------|----------|
+| MASK_KIND | MASK  | ELWIDTH | SUBVL | Rdest_EXTRA | Rsrc1_EXTRA | Rsrc2_EXTRA | Rsrc3_EXTRA | Reserved |