for (auto wire : module->wires())
{
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
init_map[initsig[i]] = initval[i] == State::S1;
for (auto cell : module->cells())
{
- if (cell->type == "$_NOT_")
+ if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
continue;
}
- if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
+ if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
{
- SigBit D = sigmap(cell->getPort("\\D").as_bit());
- SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
+ SigBit D = sigmap(cell->getPort(ID::D).as_bit());
+ SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
ff_map[Q] = D;
continue;
}
- if (cell->type == "$_AND_")
+ if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
continue;
}
- if (cell->type == "$initstate")
+ if (cell->type == ID($initstate))
{
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
undriven_bits.erase(Y);
continue;
}
- if (cell->type == "$assert")
+ if (cell->type == ID($assert))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
- SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
asserts.push_back(make_pair(A, EN));
continue;
}
- if (cell->type == "$assume")
+ if (cell->type == ID($assume))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
- SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
assumes.push_back(make_pair(A, EN));
continue;
}
- if (cell->type == "$live")
+ if (cell->type == ID($live))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
- SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
liveness.push_back(make_pair(A, EN));
continue;
}
- if (cell->type == "$fair")
+ if (cell->type == ID($fair))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
- SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
fairness.push_back(make_pair(A, EN));
continue;
}
- if (cell->type == "$anyconst")
+ if (cell->type == ID($anyconst))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit);
continue;
}
- if (cell->type == "$anyseq")
+ if (cell->type == ID($anyseq))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit);
undriven_bits.insert(bit);
unused_bits.insert(bit);
- bool scc = wire->attributes.count(ID(abc9_scc));
+ bool scc = wire->attributes.count(ID::abc9_scc);
if (wire->port_input || scc)
input_bits.insert(bit);
for (auto cell : module->cells()) {
if (!cell->has_keep_attr()) {
- if (cell->type == "$_NOT_")
+ if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
continue;
}
- if (cell->type == "$_AND_")
+ if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
continue;
}
- if (cell->type == "$__ABC9_FF_" &&
+ if (cell->type == ID($__ABC9_FF_) &&
// The presence of an abc9_mergeability attribute indicates
// that we do want to pass this flop to ABC
- cell->attributes.count("\\abc9_mergeability"))
+ cell->attributes.count(ID::abc9_mergeability))
{
- SigBit D = sigmap(cell->getPort("\\D").as_bit());
- SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
+ SigBit D = sigmap(cell->getPort(ID::D).as_bit());
+ SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
continue;
}
- if (cell->type.in("$specify2", "$specify3", "$specrule"))
+ if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
continue;
}
bool abc9_flop = false;
if (!cell->has_keep_attr()) {
- auto it = cell->attributes.find("\\abc9_box_seq");
+ auto it = cell->attributes.find(ID::abc9_box_seq);
if (it != cell->attributes.end()) {
int abc9_box_seq = it->second.as_int();
if (GetSize(box_list) <= abc9_box_seq)
box_list[abc9_box_seq] = cell;
// Only flop boxes may have arrival times
// (all others are combinatorial)
- abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
+ abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
if (!abc9_flop)
continue;
}
RTLIL::Module* box_module = module->design->module(cell->type);
log_assert(box_module);
- log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop"));
+ log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
auto r = box_ports.insert(cell->type);
if (r.second) {
for (const auto &port_name : box_module->ports) {
auto w = box_module->wire(port_name);
log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) {
if (carry_in != IdString())
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
}
// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
- if (box_module->get_bool_attribute("\\abc9_flop")) {
+ if (box_module->get_bool_attribute(ID::abc9_flop)) {
SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
if (rhs.empty())
log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
for (const auto &i : ff_bits) {
const Cell *cell = i.second;
- const SigBit &q = sigmap(cell->getPort("\\Q"));
+ const SigBit &q = sigmap(cell->getPort(ID::Q));
aig_m++, aig_i++;
log_assert(!aig_map.count(q));
aig_map[q] = 2*aig_m;
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute("\\abc9_flop"))
+ if (box_module->get_bool_attribute(ID::abc9_flop))
box_inputs++;
std::get<0>(v) = box_inputs;
std::get<1>(v) = box_outputs;
- std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int();
+ std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
}
write_h_buffer(std::get<0>(v));
const SigBit &d = i.first;
const Cell *cell = i.second;
- int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int();
+ int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
log_assert(mergeability > 0);
write_r_buffer(mergeability);
- Const init = cell->attributes.at(ID(abc9_init), State::Sx);
+ Const init = cell->attributes.at(ID::abc9_init, State::Sx);
log_assert(GetSize(init) == 1);
if (init == State::S1)
write_s_buffer(1);
f(f), module(module), design(design), config(config), ct(design), sigmap(module)
{
for (Wire *wire : module->wires())
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
switch (initval[i]) {
case State::S0:
continue;
}
- if (!config->icells_mode && cell->type == "$_NOT_") {
+ if (!config->icells_mode && cell->type == ID($_NOT_)) {
f << stringf(".names %s %s\n0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_AND_") {
+ if (!config->icells_mode && cell->type == ID($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_OR_") {
+ if (!config->icells_mode && cell->type == ID($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_XOR_") {
+ if (!config->icells_mode && cell->type == ID($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_NAND_") {
+ if (!config->icells_mode && cell->type == ID($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_NOR_") {
+ if (!config->icells_mode && cell->type == ID($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_XNOR_") {
+ if (!config->icells_mode && cell->type == ID($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_ANDNOT_") {
+ if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_ORNOT_") {
+ if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_AOI3_") {
+ if (!config->icells_mode && cell->type == ID($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y)));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_OAI3_") {
+ if (!config->icells_mode && cell->type == ID($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
- cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y)));
+ cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_AOI4_") {
+ if (!config->icells_mode && cell->type == ID($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y)));
+ cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_OAI4_") {
+ if (!config->icells_mode && cell->type == ID($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
- cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y)));
+ cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_MUX_") {
+ if (!config->icells_mode && cell->type == ID($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_NMUX_") {
+ if (!config->icells_mode && cell->type == ID($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_FF_") {
- f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
- cstr_init(cell->getPort("\\Q")));
+ if (!config->icells_mode && cell->type == ID($_FF_)) {
+ f << stringf(".latch %s %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
+ cstr_init(cell->getPort(ID::Q)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_DFF_N_") {
- f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
- cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q")));
+ if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
+ f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
+ cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_DFF_P_") {
- f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
- cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q")));
+ if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
+ f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
+ cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_DLATCH_N_") {
- f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
- cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
+ if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
+ f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
+ cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$_DLATCH_P_") {
- f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")),
- cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q")));
+ if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
+ f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
+ cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$lut") {
+ if (!config->icells_mode && cell->type == ID($lut)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
- auto width = cell->parameters.at("\\WIDTH").as_int();
+ auto width = cell->parameters.at(ID::WIDTH).as_int();
log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--)
f << stringf(" %s", cstr(inputs.extract(i, 1)));
log_assert(output.size() == 1);
f << stringf(" %s", cstr(output));
f << stringf("\n");
- RTLIL::SigSpec mask = cell->parameters.at("\\LUT");
+ RTLIL::SigSpec mask = cell->parameters.at(ID::LUT);
for (int i = 0; i < (1 << width); i++)
if (mask[i] == State::S1) {
for (int j = width-1; j >= 0; j--) {
goto internal_cell;
}
- if (!config->icells_mode && cell->type == "$sop") {
+ if (!config->icells_mode && cell->type == ID($sop)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
- auto width = cell->parameters.at("\\WIDTH").as_int();
- auto depth = cell->parameters.at("\\DEPTH").as_int();
- vector<State> table = cell->parameters.at("\\TABLE").bits;
+ auto width = cell->parameters.at(ID::WIDTH).as_int();
+ auto depth = cell->parameters.at(ID::DEPTH).as_int();
+ vector<State> table = cell->parameters.at(ID::TABLE).bits;
while (GetSize(table) < 2*width*depth)
table.push_back(State::S0);
log_assert(inputs.size() == width);
string getinfo(T *obj, bool srcsym = false)
{
string infostr = log_id(obj);
- if (obj->attributes.count("\\src")) {
- string src = obj->attributes.at("\\src").decode_string().c_str();
+ if (obj->attributes.count(ID::src)) {
+ string src = obj->attributes.at(ID::src).decode_string().c_str();
if (srcsym && infostr[0] == '$') {
std::replace(src.begin(), src.end(), ' ', '_');
if (srcsymbols.count(src) || module->count_id("\\" + src)) {
cell_recursion_guard.insert(cell);
btorf_push(log_id(cell));
- if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
- "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
+ ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
{
string btor_op;
- if (cell->type == "$add") btor_op = "add";
- if (cell->type == "$sub") btor_op = "sub";
- if (cell->type == "$mul") btor_op = "mul";
- if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
- if (cell->type == "$shr") btor_op = "srl";
- if (cell->type == "$sshr") btor_op = "sra";
- if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
- if (cell->type.in("$and", "$_AND_")) btor_op = "and";
- if (cell->type.in("$or", "$_OR_")) btor_op = "or";
- if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
- if (cell->type == "$concat") btor_op = "concat";
- if (cell->type == "$_NAND_") btor_op = "nand";
- if (cell->type == "$_NOR_") btor_op = "nor";
- if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
+ if (cell->type == ID($add)) btor_op = "add";
+ if (cell->type == ID($sub)) btor_op = "sub";
+ if (cell->type == ID($mul)) btor_op = "mul";
+ if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
+ if (cell->type == ID($shr)) btor_op = "srl";
+ if (cell->type == ID($sshr)) btor_op = "sra";
+ if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
+ if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
+ if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
+ if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
+ if (cell->type == ID($concat)) btor_op = "concat";
+ if (cell->type == ID($_NAND_)) btor_op = "nand";
+ if (cell->type == ID($_NOR_)) btor_op = "nor";
+ if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
- bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
- bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
+ bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
+ bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
if (btor_op == "shift" && !b_signed)
btor_op = "srl";
- if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
+ if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
b_signed = false;
- if (cell->type == "$sshr" && !a_signed)
+ if (cell->type == ID($sshr) && !a_signed)
btor_op = "srl";
int sid = get_bv_sid(width);
goto okay;
}
- if (cell->type.in("$div", "$mod"))
+ if (cell->type.in(ID($div), ID($mod)))
{
string btor_op;
- if (cell->type == "$div") btor_op = "div";
- if (cell->type == "$mod") btor_op = "rem";
+ if (cell->type == ID($div)) btor_op = "div";
+ if (cell->type == ID($mod)) btor_op = "rem";
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
- bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
- bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
+ bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
+ bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
goto okay;
}
- if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid1 = next_nid++;
int nid2 = next_nid++;
- if (cell->type == "$_ANDNOT_") {
+ if (cell->type == ID($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
- if (cell->type == "$_ORNOT_") {
+ if (cell->type == ID($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
goto okay;
}
- if (cell->type.in("$_OAI3_", "$_AOI3_"))
+ if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
- int nid_c = get_sig_nid(cell->getPort("\\C"));
+ int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid1 = next_nid++;
int nid2 = next_nid++;
int nid3 = next_nid++;
- if (cell->type == "$_OAI3_") {
+ if (cell->type == ID($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
}
- if (cell->type == "$_AOI3_") {
+ if (cell->type == ID($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
goto okay;
}
- if (cell->type.in("$_OAI4_", "$_AOI4_"))
+ if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
- int nid_c = get_sig_nid(cell->getPort("\\C"));
- int nid_d = get_sig_nid(cell->getPort("\\D"));
+ int nid_c = get_sig_nid(cell->getPort(ID::C));
+ int nid_d = get_sig_nid(cell->getPort(ID::D));
int nid1 = next_nid++;
int nid2 = next_nid++;
int nid3 = next_nid++;
int nid4 = next_nid++;
- if (cell->type == "$_OAI4_") {
+ if (cell->type == ID($_OAI4_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
}
- if (cell->type == "$_AOI4_") {
+ if (cell->type == ID($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
goto okay;
}
- if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
+ if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
{
string btor_op;
- if (cell->type == "$lt") btor_op = "lt";
- if (cell->type == "$le") btor_op = "lte";
- if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
- if (cell->type.in("$ne", "$nex")) btor_op = "neq";
- if (cell->type == "$ge") btor_op = "gte";
- if (cell->type == "$gt") btor_op = "gt";
+ if (cell->type == ID($lt)) btor_op = "lt";
+ if (cell->type == ID($le)) btor_op = "lte";
+ if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
+ if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
+ if (cell->type == ID($ge)) btor_op = "gte";
+ if (cell->type == ID($gt)) btor_op = "gt";
log_assert(!btor_op.empty());
int width = 1;
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
- bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
- bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
+ bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
+ bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid = next_nid++;
- if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
+ if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
} else {
btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
goto okay;
}
- if (cell->type.in("$not", "$neg", "$_NOT_"))
+ if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
{
string btor_op;
- if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
- if (cell->type == "$neg") btor_op = "neg";
+ if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
+ if (cell->type == ID($neg)) btor_op = "neg";
log_assert(!btor_op.empty());
int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
- bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
+ bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
int sid = get_bv_sid(width);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
goto okay;
}
- if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
+ if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
{
string btor_op;
- if (cell->type == "$logic_and") btor_op = "and";
- if (cell->type == "$logic_or") btor_op = "or";
- if (cell->type == "$logic_not") btor_op = "not";
+ if (cell->type == ID($logic_and)) btor_op = "and";
+ if (cell->type == ID($logic_or)) btor_op = "or";
+ if (cell->type == ID($logic_not)) btor_op = "not";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
goto okay;
}
- if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
+ if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
{
string btor_op;
- if (cell->type == "$reduce_and") btor_op = "redand";
- if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
- if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
+ if (cell->type == ID($reduce_and)) btor_op = "redand";
+ if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
+ if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
int nid = next_nid++;
- if (cell->type == "$reduce_xnor") {
+ if (cell->type == ID($reduce_xnor)) {
int nid2 = next_nid++;
btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d not %d %d %d\n", nid2, sid, nid);
goto okay;
}
- if (cell->type.in("$mux", "$_MUX_", "$_NMUX_"))
+ if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
- if (cell->type == "$_NMUX_") {
+ if (cell->type == ID($_NMUX_)) {
int tmp = nid;
nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
goto okay;
}
- if (cell->type == "$pmux")
+ if (cell->type == ID($pmux))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
goto okay;
}
- if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N_", "$_FF_"))
+ if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
{
- SigSpec sig_d = sigmap(cell->getPort("\\D"));
- SigSpec sig_q = sigmap(cell->getPort("\\Q"));
+ SigSpec sig_d = sigmap(cell->getPort(ID::D));
+ SigSpec sig_q = sigmap(cell->getPort(ID::Q));
- if (!info_filename.empty() && cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_"))
+ if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
{
- SigSpec sig_c = sigmap(cell->getPort(cell->type == "$dff" ? "\\CLK" : "\\C"));
+ SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
int nid = get_sig_nid(sig_c);
bool negedge = false;
- if (cell->type == "$_DFF_N_")
+ if (cell->type == ID($_DFF_N_))
negedge = true;
- if (cell->type == "$dff" && !cell->getParam("\\CLK_POLARITY").as_bool())
+ if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
negedge = true;
info_clocks[nid] |= negedge ? 2 : 1;
goto okay;
}
- if (cell->type.in("$anyconst", "$anyseq"))
+ if (cell->type.in(ID($anyconst), ID($anyseq)))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
btorf("%d state %d\n", nid, sid);
- if (cell->type == "$anyconst") {
+ if (cell->type == ID($anyconst)) {
int nid2 = next_nid++;
btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
}
goto okay;
}
- if (cell->type == "$initstate")
+ if (cell->type == ID($initstate))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
goto okay;
}
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int nwords = cell->getParam("\\SIZE").as_int();
- int rdports = cell->getParam("\\RD_PORTS").as_int();
- int wrports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int nwords = cell->getParam(ID::SIZE).as_int();
+ int rdports = cell->getParam(ID::RD_PORTS).as_int();
+ int wrports = cell->getParam(ID::WR_PORTS).as_int();
- Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
- Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
+ Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
+ Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
bool asyncwr = wr_clk_en.is_fully_zero();
log_error("Memory %s.%s has sync read ports.\n",
log_id(module), log_id(cell));
- SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
- SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
+ SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
+ SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
- SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
- SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
- SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
+ SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
+ SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
+ SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1);
int sid = get_mem_sid(abits, width);
- Const initdata = cell->getParam("\\INIT");
+ Const initdata = cell->getParam(ID::INIT);
initdata.exts(nwords*width);
int nid_init_val = -1;
for (auto wire : module->wires())
{
- if (wire->attributes.count("\\init")) {
- Const attrval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const attrval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
if (attrval[i] == State::S0 || attrval[i] == State::S1)
initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
for (auto cell : module->cells())
{
- if (cell->type == "$assume")
+ if (cell->type == ID($assume))
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
- int nid_en = get_sig_nid(cell->getPort("\\EN"));
+ int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++;
int nid = next_nid++;
btorf_pop(log_id(cell));
}
- if (cell->type == "$assert")
+ if (cell->type == ID($assert))
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
- int nid_en = get_sig_nid(cell->getPort("\\EN"));
+ int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
btorf_pop(log_id(cell));
}
- if (cell->type == "$cover" && cover_mode)
+ if (cell->type == ID($cover) && cover_mode)
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
- int nid_a = get_sig_nid(cell->getPort("\\A"));
- int nid_en = get_sig_nid(cell->getPort("\\EN"));
+ int nid_a = get_sig_nid(cell->getPort(ID::A));
+ int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_en_and_a = next_nid++;
btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
btorf_push(stringf("next %s", log_id(cell)));
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int wrports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int wrports = cell->getParam(ID::WR_PORTS).as_int();
- SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
- SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
- SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
+ SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
+ SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
+ SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1);
}
else
{
- SigSpec sig = sigmap(cell->getPort("\\D"));
+ SigSpec sig = sigmap(cell->getPort(ID::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
{
const auto wireName = make_id(wire->name);
// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
log_warning("Initial value (%s) for (%s.%s) not supported\n",
- wire->attributes.at("\\init").as_string().c_str(),
+ wire->attributes.at(ID::init).as_string().c_str(),
log_id(module), log_id(wire));
}
if (wire->port_id)
}
// Not a module instance. Set up cell properties
bool extract_y_bits = false; // Assume no extraction of final bits will be required.
- int a_width = cell->parameters.at("\\A_WIDTH", ndef).as_int(); // The width of "A"
- int b_width = cell->parameters.at("\\B_WIDTH", ndef).as_int(); // The width of "A"
- const int y_width = cell->parameters.at("\\Y_WIDTH", ndef).as_int(); // The width of the result
- const bool a_signed = cell->parameters.at("\\A_SIGNED", ndef).as_bool();
- const bool b_signed = cell->parameters.at("\\B_SIGNED", ndef).as_bool();
+ int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
+ int b_width = cell->parameters.at(ID::B_WIDTH, ndef).as_int(); // The width of "A"
+ const int y_width = cell->parameters.at(ID::Y_WIDTH, ndef).as_int(); // The width of the result
+ const bool a_signed = cell->parameters.at(ID::A_SIGNED, ndef).as_bool();
+ const bool b_signed = cell->parameters.at(ID::B_SIGNED, ndef).as_bool();
bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this).
int firrtl_width = 0;
string primop;
bool always_uint = false;
string y_id = make_id(cell->name);
- if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
+ if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(ID::A));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
}
// Don't use the results of logical operations (a single bit) to control padding
- if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) {
+ if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
}
// Assume the FIRRTL width is a single bit.
firrtl_width = 1;
- if (cell->type == "$not") primop = "not";
- else if (cell->type == "$neg") {
+ if (cell->type == ID($not)) primop = "not";
+ else if (cell->type == ID($neg)) {
primop = "neg";
firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
firrtl_width = a_width;
- } else if (cell->type == "$logic_not") {
+ } else if (cell->type == ID($logic_not)) {
primop = "eq";
a_expr = stringf("%s, UInt(0)", a_expr.c_str());
}
- else if (cell->type == "$reduce_and") primop = "andr";
- else if (cell->type == "$reduce_or") primop = "orr";
- else if (cell->type == "$reduce_xor") primop = "xorr";
- else if (cell->type == "$reduce_xnor") {
+ else if (cell->type == ID($reduce_and)) primop = "andr";
+ else if (cell->type == ID($reduce_or)) primop = "orr";
+ else if (cell->type == ID($reduce_xor)) primop = "xorr";
+ else if (cell->type == ID($reduce_xnor)) {
primop = "not";
a_expr = stringf("xorr(%s)", a_expr.c_str());
}
- else if (cell->type == "$reduce_bool") {
+ else if (cell->type == ID($reduce_bool)) {
primop = "neq";
// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
continue;
}
- if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
- "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
- "$logic_and", "$logic_or", "$pow"))
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
+ ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
+ ID($logic_and), ID($logic_or), ID($pow)))
{
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
}
// Shift amount is always unsigned, and needn't be padded to result width,
// otherwise, we need to cast the b_expr appropriately
- if (b_signed && !cell->type.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) {
+ if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
b_expr = "asSInt(" + b_expr + ")";
// Expand the "B" operand to the result width
if (b_width < y_width) {
// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
// This corresponds (according to iverilog) to what verilog compilers implement.
- if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or"))
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or)))
{
if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
firrtl_width = a_width;
auto a_sig = cell->getPort(ID::A);
- if (cell->type == "$add") {
+ if (cell->type == ID($add)) {
primop = "add";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = max(a_width, b_width);
- } else if (cell->type == "$sub") {
+ } else if (cell->type == ID($sub)) {
primop = "sub";
firrtl_is_signed = true;
int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
- } else if (cell->type == "$mul") {
+ } else if (cell->type == ID($mul)) {
primop = "mul";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width + b_width;
- } else if (cell->type == "$div") {
+ } else if (cell->type == ID($div)) {
primop = "div";
firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width;
- } else if (cell->type == "$mod") {
+ } else if (cell->type == ID($mod)) {
primop = "rem";
firrtl_width = min(a_width, b_width);
- } else if (cell->type == "$and") {
+ } else if (cell->type == ID($and)) {
primop = "and";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if (cell->type == "$or" ) {
+ else if (cell->type == ID($or) ) {
primop = "or";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if (cell->type == "$xor") {
+ else if (cell->type == ID($xor)) {
primop = "xor";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if (cell->type == "$xnor") {
+ else if (cell->type == ID($xnor)) {
primop = "xnor";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if ((cell->type == "$eq") | (cell->type == "$eqx")) {
+ else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
primop = "eq";
always_uint = true;
firrtl_width = 1;
}
- else if ((cell->type == "$ne") | (cell->type == "$nex")) {
+ else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
primop = "neq";
always_uint = true;
firrtl_width = 1;
}
- else if (cell->type == "$gt") {
+ else if (cell->type == ID($gt)) {
primop = "gt";
always_uint = true;
firrtl_width = 1;
}
- else if (cell->type == "$ge") {
+ else if (cell->type == ID($ge)) {
primop = "geq";
always_uint = true;
firrtl_width = 1;
}
- else if (cell->type == "$lt") {
+ else if (cell->type == ID($lt)) {
primop = "lt";
always_uint = true;
firrtl_width = 1;
}
- else if (cell->type == "$le") {
+ else if (cell->type == ID($le)) {
primop = "leq";
always_uint = true;
firrtl_width = 1;
}
- else if ((cell->type == "$shl") | (cell->type == "$sshl")) {
+ else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
// FIRRTL will widen the result (y) by the amount of the shift.
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
firrtl_width = a_width + (1 << b_width) - 1;
}
}
- else if ((cell->type == "$shr") | (cell->type == "$sshr")) {
+ else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?
// We'll need to do some special fixups if the source (and thus result) is signed.
if (firrtl_is_signed) {
// If this is a "logical" shift right, pretend the source is unsigned.
- if (cell->type == "$shr") {
+ if (cell->type == ID($shr)) {
a_expr = "asUInt(" + a_expr + ")";
}
}
}
- else if ((cell->type == "$logic_and")) {
+ else if ((cell->type == ID($logic_and))) {
primop = "and";
a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true;
firrtl_width = 1;
}
- else if ((cell->type == "$logic_or")) {
+ else if ((cell->type == ID($logic_or))) {
primop = "or";
a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true;
firrtl_width = 1;
}
- else if ((cell->type == "$pow")) {
+ else if ((cell->type == ID($pow))) {
if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
// We'll convert this to a shift. To simplify things, change the a_expr to "1"
// so we can use b_expr directly as a shift amount.
}
}
- if (!cell->parameters.at("\\B_SIGNED").as_bool()) {
+ if (!cell->parameters.at(ID::B_SIGNED).as_bool()) {
b_expr = "asUInt(" + b_expr + ")";
}
continue;
}
- if (cell->type.in("$mux"))
+ if (cell->type.in(ID($mux)))
{
- int width = cell->parameters.at("\\WIDTH").as_int();
+ int width = cell->parameters.at(ID::WIDTH).as_int();
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S));
continue;
}
- if (cell->type.in("$mem"))
+ if (cell->type.in(ID($mem)))
{
string mem_id = make_id(cell->name);
- int abits = cell->parameters.at("\\ABITS").as_int();
- int width = cell->parameters.at("\\WIDTH").as_int();
- int size = cell->parameters.at("\\SIZE").as_int();
+ int abits = cell->parameters.at(ID::ABITS).as_int();
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ int size = cell->parameters.at(ID::SIZE).as_int();
memory m(cell, mem_id, abits, size, width);
- int rd_ports = cell->parameters.at("\\RD_PORTS").as_int();
- int wr_ports = cell->parameters.at("\\WR_PORTS").as_int();
+ int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
+ int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
- Const initdata = cell->parameters.at("\\INIT");
+ Const initdata = cell->parameters.at(ID::INIT);
for (State bit : initdata.bits)
if (bit != State::Sx)
log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
- Const rd_clk_enable = cell->parameters.at("\\RD_CLK_ENABLE");
- Const wr_clk_enable = cell->parameters.at("\\WR_CLK_ENABLE");
- Const wr_clk_polarity = cell->parameters.at("\\WR_CLK_POLARITY");
+ Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
+ Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
+ Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
- int offset = cell->parameters.at("\\OFFSET").as_int();
+ int offset = cell->parameters.at(ID::OFFSET).as_int();
if (offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
if (rd_clk_enable[i] != State::S0)
log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
- SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
- SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width);
+ SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
+ SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
string addr_expr = make_expr(addr_sig);
string name(stringf("%s.r%d", m.name.c_str(), i));
bool clk_enable = false;
bool clk_enable = true;
bool clk_parity = true;
bool transparency = false;
- SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits);
+ SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
string addr_expr = make_expr(addr_sig);
- SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width);
+ SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
string data_expr = make_expr(data_sig);
- SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i);
+ SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
string clk_expr = make_expr(clk_sig);
- SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width);
+ SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
string wen_expr = make_expr(wen_sig[0]);
for (int i = 1; i < GetSize(wen_sig); i++)
continue;
}
- if (cell->type.in("$memwr", "$memrd", "$meminit"))
+ if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
{
std::string cell_type = fid(cell->type);
- std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string());
- int abits = cell->parameters.at("\\ABITS").as_int();
- int width = cell->parameters.at("\\WIDTH").as_int();
+ std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
+ int abits = cell->parameters.at(ID::ABITS).as_int();
+ int width = cell->parameters.at(ID::WIDTH).as_int();
memory *mp = nullptr;
- if (cell->type == "$meminit" ) {
+ if (cell->type == ID($meminit) ) {
log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
} else {
// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
- auto addrSig = cell->getPort("\\ADDR");
- auto dataSig = cell->getPort("\\DATA");
- auto enableSig = cell->getPort("\\EN");
- auto clockSig = cell->getPort("\\CLK");
- Const clk_enable = cell->parameters.at("\\CLK_ENABLE");
- Const clk_polarity = cell->parameters.at("\\CLK_POLARITY");
+ auto addrSig = cell->getPort(ID::ADDR);
+ auto dataSig = cell->getPort(ID::DATA);
+ auto enableSig = cell->getPort(ID::EN);
+ auto clockSig = cell->getPort(ID::CLK);
+ Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
+ Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
// Do we already have an entry for this memory?
if (memories.count(mem_id) == 0) {
int portNum = 0;
bool transparency = false;
string data_expr = make_expr(dataSig);
- if (cell->type.in("$memwr")) {
+ if (cell->type.in(ID($memwr))) {
portNum = (int) mp->write_ports.size();
write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
mp->add_memory_write_port(wp);
cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
cell_exprs.push_back(wp.gen_write(indent.c_str()));
- } else if (cell->type.in("$memrd")) {
+ } else if (cell->type.in(ID($memrd))) {
portNum = (int) mp->read_ports.size();
read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
mp->add_memory_read_port(rp);
continue;
}
- if (cell->type.in("$dff"))
+ if (cell->type.in(ID($dff)))
{
- bool clkpol = cell->parameters.at("\\CLK_POLARITY").as_bool();
+ bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
if (clkpol == false)
log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
- int width = cell->parameters.at("\\WIDTH").as_int();
- string expr = make_expr(cell->getPort("\\D"));
- string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ string expr = make_expr(cell->getPort(ID::D));
+ string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
- register_reverse_wire_map(y_id, cell->getPort("\\Q"));
+ register_reverse_wire_map(y_id, cell->getPort(ID::Q));
continue;
}
process_instance(cell, wire_exprs);
continue;
}
- if (cell->type == "$shiftx") {
+ if (cell->type == ID($shiftx)) {
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
string b_expr = make_expr(cell->getPort(ID::B));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
- if (cell->getParam("\\B_SIGNED").as_bool()) {
+ if (cell->getParam(ID::B_SIGNED).as_bool()) {
// Use validif to constrain the selection (test the sign bit)
auto b_string = b_expr.c_str();
- int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1;
+ int b_sign = cell->parameters.at(ID::B_WIDTH).as_int() - 1;
b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
}
string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
- if (cell->type == "$shift") {
+ if (cell->type == ID($shift)) {
// assign y = a >> b;
// where b may be negative
string expr;
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
- if (cell->getParam("\\B_SIGNED").as_bool()) {
+ if (cell->getParam(ID::B_SIGNED).as_bool()) {
// We generate a left or right shift based on the sign of b.
std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width);
std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue;
}
- if (cell->type == "$pos") {
+ if (cell->type == ID($pos)) {
// assign y = a;
// printCell(cell);
string a_expr = make_expr(cell->getPort(ID::A));
void eval_cell(HierDirtyFlags *work, Cell *cell)
{
- if (cell->type.in("$_BUF_", "$_NOT_"))
+ if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr;
- if (cell->type == "$_BUF_") expr = a_expr;
- if (cell->type == "$_NOT_") expr = "!" + a_expr;
+ if (cell->type == ID($_BUF_)) expr = a_expr;
+ if (cell->type == ID($_NOT_)) expr = "!" + a_expr;
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
return;
}
- if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
string expr;
- if (cell->type == "$_AND_") expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_NAND_") expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_OR_") expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_NOR_") expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_XOR_") expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_XNOR_") expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_ANDNOT_") expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str());
- if (cell->type == "$_ORNOT_") expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_AND_)) expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_NAND_)) expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_OR_)) expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_NOR_)) expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_XOR_)) expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_XNOR_)) expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str());
+ if (cell->type == ID($_ORNOT_)) expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str());
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
return;
}
- if (cell->type.in("$_AOI3_", "$_OAI3_"))
+ if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
- SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
+ SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
string expr;
- if (cell->type == "$_AOI3_") expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
- if (cell->type == "$_OAI3_") expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
+ if (cell->type == ID($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
+ if (cell->type == ID($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
return;
}
- if (cell->type.in("$_AOI4_", "$_OAI4_"))
+ if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
- SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
- SigBit d = sigmaps.at(work->module)(cell->getPort("\\D"));
+ SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
+ SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
string expr;
- if (cell->type == "$_AOI4_") expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
- if (cell->type == "$_OAI4_") expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
+ if (cell->type == ID($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
+ if (cell->type == ID($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
return;
}
- if (cell->type.in("$_MUX_", "$_NMUX_"))
+ if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr.c_str(),
- cell->type == "$_NMUX_" ? "!" : "", b_expr.c_str(),
- cell->type == "$_NMUX_" ? "!" : "", a_expr.c_str());
+ cell->type == ID($_NMUX_) ? "!" : "", b_expr.c_str(),
+ cell->type == ID($_NMUX_) ? "!" : "", a_expr.c_str());
log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
for (Wire *w : module->wires())
{
- if (w->attributes.count("\\init"))
+ if (w->attributes.count(ID::init))
{
SigSpec sig = sigmaps.at(module)(w);
- Const val = w->attributes.at("\\init");
+ Const val = w->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx);
for (int i = 0; i < GetSize(sig); i++)
log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
- if (cell->type.in("$mem") && conn.first.in("\\RD_CLK", "\\WR_CLK"))
+ if (cell->type.in(ID($mem)) && conn.first.in(ID::RD_CLK, ID::WR_CLK))
{
SigSpec clk = sigmap(conn.second);
for (int i = 0; i < GetSize(clk); i++)
if (clk[i].wire == nullptr)
continue;
- if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i] != State::S1)
+ if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_ENABLE : ID::WR_CLK_ENABLE)[i] != State::S1)
continue;
- if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i] == State::S1)
+ if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_POLARITY : ID::WR_CLK_POLARITY)[i] == State::S1)
clock_posedge.insert(clk[i]);
else
clock_negedge.insert(clk[i]);
}
}
else
- if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C"))
+ if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && conn.first.in(ID::CLK, ID::C))
{
- bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool());
+ bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
for (auto bit : sigmap(conn.second)) {
if (posedge)
clock_posedge.insert(bit);
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
- else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C"));
- else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D"));
+ else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C));
+ else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
else processed_expr += ch;
}
{
RTLIL::SigSpec sig_a, sig_b;
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
- bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int width = GetSize(sig_y);
if (type == 's' || type == 'd' || type == 'b') {
exported_cells.insert(cell);
recursive_cells.insert(cell);
- if (cell->type == "$initstate")
+ if (cell->type == ID($initstate))
{
SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
return;
}
- if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
+ if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
registers.insert(cell);
- makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q")));
- register_bool(cell->getPort("\\Q"), idcounter++);
+ makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q)));
+ register_bool(cell->getPort(ID::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
- if (cell->type == "$_BUF_") return export_gate(cell, "A");
- if (cell->type == "$_NOT_") return export_gate(cell, "(not A)");
- if (cell->type == "$_AND_") return export_gate(cell, "(and A B)");
- if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))");
- if (cell->type == "$_OR_") return export_gate(cell, "(or A B)");
- if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))");
- if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)");
- if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))");
- if (cell->type == "$_ANDNOT_") return export_gate(cell, "(and A (not B))");
- if (cell->type == "$_ORNOT_") return export_gate(cell, "(or A (not B))");
- if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)");
- if (cell->type == "$_NMUX_") return export_gate(cell, "(not (ite S B A))");
- if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))");
- if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))");
- if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))");
- if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))");
+ if (cell->type == ID($_BUF_)) return export_gate(cell, "A");
+ if (cell->type == ID($_NOT_)) return export_gate(cell, "(not A)");
+ if (cell->type == ID($_AND_)) return export_gate(cell, "(and A B)");
+ if (cell->type == ID($_NAND_)) return export_gate(cell, "(not (and A B))");
+ if (cell->type == ID($_OR_)) return export_gate(cell, "(or A B)");
+ if (cell->type == ID($_NOR_)) return export_gate(cell, "(not (or A B))");
+ if (cell->type == ID($_XOR_)) return export_gate(cell, "(xor A B)");
+ if (cell->type == ID($_XNOR_)) return export_gate(cell, "(not (xor A B))");
+ if (cell->type == ID($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
+ if (cell->type == ID($_ORNOT_)) return export_gate(cell, "(or A (not B))");
+ if (cell->type == ID($_MUX_)) return export_gate(cell, "(ite S B A)");
+ if (cell->type == ID($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
+ if (cell->type == ID($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
+ if (cell->type == ID($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
+ if (cell->type == ID($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
+ if (cell->type == ID($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
// FIXME: $lut
if (bvmode)
{
- if (cell->type.in("$ff", "$dff"))
+ if (cell->type.in(ID($ff), ID($dff)))
{
registers.insert(cell);
- makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")));
- register_bv(cell->getPort("\\Q"), idcounter++);
+ makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)));
+ register_bv(cell->getPort(ID::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
- if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq"))
+ if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
{
registers.insert(cell);
string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell);
- if (cell->attributes.count("\\reg"))
- infostr += " " + cell->attributes.at("\\reg").decode_string();
+ if (cell->attributes.count(ID::reg))
+ infostr += " " + cell->attributes.at(ID::reg).decode_string();
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str()));
- if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\maximize")){
+ if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::maximize)){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
}
- else if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\minimize")){
+ else if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::minimize)){
decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
}
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y)));
- if (cell->type == "$anyseq")
+ if (cell->type == ID($anyseq))
ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
register_bv(cell->getPort(ID::Y), idcounter++);
recursive_cells.erase(cell);
return;
}
- if (cell->type == "$and") return export_bvop(cell, "(bvand A B)");
- if (cell->type == "$or") return export_bvop(cell, "(bvor A B)");
- if (cell->type == "$xor") return export_bvop(cell, "(bvxor A B)");
- if (cell->type == "$xnor") return export_bvop(cell, "(bvxnor A B)");
+ if (cell->type == ID($and)) return export_bvop(cell, "(bvand A B)");
+ if (cell->type == ID($or)) return export_bvop(cell, "(bvor A B)");
+ if (cell->type == ID($xor)) return export_bvop(cell, "(bvxor A B)");
+ if (cell->type == ID($xnor)) return export_bvop(cell, "(bvxnor A B)");
- if (cell->type == "$shl") return export_bvop(cell, "(bvshl A B)", 's');
- if (cell->type == "$shr") return export_bvop(cell, "(bvlshr A B)", 's');
- if (cell->type == "$sshl") return export_bvop(cell, "(bvshl A B)", 's');
- if (cell->type == "$sshr") return export_bvop(cell, "(bvLshr A B)", 's');
+ if (cell->type == ID($shl)) return export_bvop(cell, "(bvshl A B)", 's');
+ if (cell->type == ID($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
+ if (cell->type == ID($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
+ if (cell->type == ID($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
- if (cell->type.in("$shift", "$shiftx")) {
- if (cell->getParam("\\B_SIGNED").as_bool()) {
+ if (cell->type.in(ID($shift), ID($shiftx))) {
+ if (cell->getParam(ID::B_SIGNED).as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvlshr A (bvneg B)))",
GetSize(cell->getPort(ID::B)), 0), 's');
}
}
- if (cell->type == "$lt") return export_bvop(cell, "(bvUlt A B)", 'b');
- if (cell->type == "$le") return export_bvop(cell, "(bvUle A B)", 'b');
- if (cell->type == "$ge") return export_bvop(cell, "(bvUge A B)", 'b');
- if (cell->type == "$gt") return export_bvop(cell, "(bvUgt A B)", 'b');
+ if (cell->type == ID($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
+ if (cell->type == ID($le)) return export_bvop(cell, "(bvUle A B)", 'b');
+ if (cell->type == ID($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
+ if (cell->type == ID($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
- if (cell->type == "$ne") return export_bvop(cell, "(distinct A B)", 'b');
- if (cell->type == "$nex") return export_bvop(cell, "(distinct A B)", 'b');
- if (cell->type == "$eq") return export_bvop(cell, "(= A B)", 'b');
- if (cell->type == "$eqx") return export_bvop(cell, "(= A B)", 'b');
+ if (cell->type == ID($ne)) return export_bvop(cell, "(distinct A B)", 'b');
+ if (cell->type == ID($nex)) return export_bvop(cell, "(distinct A B)", 'b');
+ if (cell->type == ID($eq)) return export_bvop(cell, "(= A B)", 'b');
+ if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b');
- if (cell->type == "$not") return export_bvop(cell, "(bvnot A)");
- if (cell->type == "$pos") return export_bvop(cell, "A");
- if (cell->type == "$neg") return export_bvop(cell, "(bvneg A)");
+ if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)");
+ if (cell->type == ID($pos)) return export_bvop(cell, "A");
+ if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)");
- if (cell->type == "$add") return export_bvop(cell, "(bvadd A B)");
- if (cell->type == "$sub") return export_bvop(cell, "(bvsub A B)");
- if (cell->type == "$mul") return export_bvop(cell, "(bvmul A B)");
- if (cell->type == "$div") return export_bvop(cell, "(bvUdiv A B)", 'd');
- if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd');
+ if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)");
+ if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)");
+ if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)");
+ if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
+ if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
- if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") &&
+ if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
- bool is_and = cell->type == "$reduce_and";
+ bool is_and = cell->type == ID($reduce_and);
string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b');
}
- if (cell->type == "$reduce_and") return export_reduce(cell, "(and A)", true);
- if (cell->type == "$reduce_or") return export_reduce(cell, "(or A)", false);
- if (cell->type == "$reduce_xor") return export_reduce(cell, "(xor A)", false);
- if (cell->type == "$reduce_xnor") return export_reduce(cell, "(not (xor A))", false);
- if (cell->type == "$reduce_bool") return export_reduce(cell, "(or A)", false);
+ if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true);
+ if (cell->type == ID($reduce_or)) return export_reduce(cell, "(or A)", false);
+ if (cell->type == ID($reduce_xor)) return export_reduce(cell, "(xor A)", false);
+ if (cell->type == ID($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
+ if (cell->type == ID($reduce_bool)) return export_reduce(cell, "(or A)", false);
- if (cell->type == "$logic_not") return export_reduce(cell, "(not (or A))", false);
- if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false);
- if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false);
+ if (cell->type == ID($logic_not)) return export_reduce(cell, "(not (or A))", false);
+ if (cell->type == ID($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
+ if (cell->type == ID($logic_or)) return export_reduce(cell, "(or A B)", false);
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
std::string processed_expr = get_bv(cell->getPort(ID::A));
// FIXME: $slice $concat
}
- if (memmode && cell->type == "$mem")
+ if (memmode && cell->type == ID($mem))
{
int arrayid = idcounter++;
memarrays[cell] = arrayid;
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
bool async_read = false;
- if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
- if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_zero())
+ if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
+ if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero())
log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
async_read = true;
}
if (statebv)
{
- int mem_size = cell->getParam("\\SIZE").as_int();
- int mem_offset = cell->getParam("\\OFFSET").as_int();
+ int mem_size = cell->getParam(ID::SIZE).as_int();
+ int mem_offset = cell->getParam(ID::OFFSET).as_int();
makebits(memstate, width*mem_size, get_id(cell));
decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
for (int i = 0; i < rd_ports; i++)
{
- SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
- SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
+ SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
std::string addr = get_bv(addr_sig);
- if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
for (int i = 0; i < rd_ports; i++)
{
- SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
- SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
+ SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
std::string addr = get_bv(addr_sig);
- if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
pool<SigBit> reg_bits;
for (auto cell : module->cells())
- if (cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) {
+ if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) {
// not using sigmap -- we want the net directly at the dff output
- for (auto bit : cell->getPort("\\Q"))
+ for (auto bit : cell->getPort(ID::Q))
reg_bits.insert(bit);
}
for (auto bit : SigSpec(wire))
if (reg_bits.count(bit))
is_register = true;
- if (wire->port_id || is_register || wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) {
+ if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) {
RTLIL::SigSpec sig = sigmap(wire);
if (wire->port_input)
decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width));
decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
if (is_register)
decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
- if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\'))
+ if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\'))
decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
vector<string> init_list;
for (auto wire : module->wires())
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
RTLIL::SigSpec sig = sigmap(wire);
- Const val = wire->attributes.at("\\init");
+ Const val = wire->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx);
if (bvmode && GetSize(sig) > 1) {
Const mask(State::S1, GetSize(sig));
for (auto cell : module->cells())
{
- if (cell->type.in("$assert", "$assume", "$cover"))
+ if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{
- int &id = cell->type == "$assert" ? assert_id :
- cell->type == "$assume" ? assume_id :
- cell->type == "$cover" ? cover_id : *(int*)nullptr;
+ int &id = cell->type == ID($assert) ? assert_id :
+ cell->type == ID($assume) ? assume_id :
+ cell->type == ID($cover) ? cover_id : *(int*)nullptr;
- char postfix = cell->type == "$assert" ? 'a' :
- cell->type == "$assume" ? 'u' :
- cell->type == "$cover" ? 'c' : 0;
+ char postfix = cell->type == ID($assert) ? 'a' :
+ cell->type == ID($assume) ? 'u' :
+ cell->type == ID($cover) ? 'c' : 0;
string name_a = get_bool(cell->getPort(ID::A));
- string name_en = get_bool(cell->getPort("\\EN"));
+ string name_en = get_bool(cell->getPort(ID::EN));
string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell);
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
- if (cell->type == "$cover")
+ if (cell->type == ID($cover))
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
else
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
- if (cell->type == "$assert")
+ if (cell->type == ID($assert))
assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id));
- else if (cell->type == "$assume")
+ else if (cell->type == ID($assume))
assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id));
id++;
for (auto cell : this_regs)
{
- if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
+ if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
- std::string expr_d = get_bool(cell->getPort("\\D"));
- std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state");
- trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q"))));
- ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort("\\Q")).c_str(), get_bool(cell->getPort("\\Q"), "other_state").c_str()));
+ std::string expr_d = get_bool(cell->getPort(ID::D));
+ std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state");
+ trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q))));
+ ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)).c_str(), get_bool(cell->getPort(ID::Q), "other_state").c_str()));
}
- if (cell->type.in("$ff", "$dff"))
+ if (cell->type.in(ID($ff), ID($dff)))
{
- std::string expr_d = get_bv(cell->getPort("\\D"));
- std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state");
- trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q"))));
- ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Q")).c_str(), get_bv(cell->getPort("\\Q"), "other_state").c_str()));
+ std::string expr_d = get_bv(cell->getPort(ID::D));
+ std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state");
+ trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q))));
+ ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)).c_str(), get_bv(cell->getPort(ID::Q), "other_state").c_str()));
}
- if (cell->type.in("$anyconst", "$allconst"))
+ if (cell->type.in(ID($anyconst), ID($allconst)))
{
std::string expr_d = get_bv(cell->getPort(ID::Y));
std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y))));
- if (cell->type == "$anyconst")
+ if (cell->type == ID($anyconst))
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str()));
}
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
int arrayid = memarrays.at(cell);
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
bool async_read = false;
string initial_memstate, final_memstate;
- if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) {
- log_assert(cell->getParam("\\WR_CLK_ENABLE").is_fully_zero());
+ if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
+ log_assert(cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero());
async_read = true;
initial_memstate = stringf("%s#%d#0", get_id(module), arrayid);
final_memstate = stringf("%s#%d#final", get_id(module), arrayid);
if (statebv)
{
- int mem_size = cell->getParam("\\SIZE").as_int();
- int mem_offset = cell->getParam("\\OFFSET").as_int();
+ int mem_size = cell->getParam(ID::SIZE).as_int();
+ int mem_offset = cell->getParam(ID::OFFSET).as_int();
if (async_read) {
makebits(final_memstate, width*mem_size, get_id(cell));
for (int i = 0; i < wr_ports; i++)
{
- SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
- SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
- SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
+ SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
+ SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
std::string addr = get_bv(addr_sig);
std::string data = get_bv(data_sig);
for (int i = 0; i < wr_ports; i++)
{
- SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
- SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
- SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
+ SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
+ SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
std::string addr = get_bv(addr_sig);
std::string data = get_bv(data_sig);
if (async_read)
hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell)));
- Const init_data = cell->getParam("\\INIT");
- int memsize = cell->getParam("\\SIZE").as_int();
+ Const init_data = cell->getParam(ID::INIT);
+ int memsize = cell->getParam(ID::SIZE).as_int();
for (int i = 0; i < memsize; i++)
{
for (auto module : sorted_modules)
for (auto cell : module->cells())
- if (cell->type.in("$allconst", "$allseq"))
+ if (cell->type.in(ID($allconst), ID($allseq)))
goto found_forall;
if (0) {
found_forall:
if (wire->port_input)
inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire)));
- if (wire->attributes.count("\\init"))
- assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at("\\init"))));
+ if (wire->attributes.count(ID::init))
+ assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at(ID::init))));
}
for (auto cell : module->cells())
{
// FIXME: $slice, $concat, $mem
- if (cell->type.in("$assert"))
+ if (cell->type.in(ID($assert)))
{
SigSpec sig_a = cell->getPort(ID::A);
- SigSpec sig_en = cell->getPort("\\EN");
+ SigSpec sig_en = cell->getPort(ID::EN);
invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
continue;
}
- if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"))
+ if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
break;
}
- bool signed_a = cell->getParam("\\A_SIGNED").as_bool();
- bool signed_b = cell->getParam("\\B_SIGNED").as_bool();
- string op = cell->type.in("$shl", "$sshl") ? "<<" : ">>";
+ bool signed_a = cell->getParam(ID::A_SIGNED).as_bool();
+ bool signed_b = cell->getParam(ID::B_SIGNED).as_bool();
+ string op = cell->type.in(ID($shl), ID($sshl)) ? "<<" : ">>";
string expr, expr_a;
- if (cell->type == "$sshr" && signed_a)
+ if (cell->type == ID($sshr) && signed_a)
{
expr_a = rvalue_s(sig_a, width);
expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a.c_str(), op.c_str(), rvalue(sig_b.extract(0, shift_b_width)), width_y);
rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width,
rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str());
}
- else if (cell->type.in("$shift", "$shiftx") && signed_b)
+ else if (cell->type.in(ID($shift), ID($shiftx)) && signed_b)
{
expr_a = rvalue_u(sig_a, width);
}
else
{
- if (cell->type.in("$shift", "$shiftx") || !signed_a)
+ if (cell->type.in(ID($shift), ID($shiftx)) || !signed_a)
expr_a = rvalue_u(sig_a, width);
else
expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width);
continue;
}
- if (cell->type.in("$not", "$pos", "$neg"))
+ if (cell->type.in(ID($not), ID($pos), ID($neg)))
{
int width = GetSize(cell->getPort(ID::Y));
string expr_a, op;
- if (cell->type == "$not") op = "!";
- if (cell->type == "$pos") op = "";
- if (cell->type == "$neg") op = "-";
+ if (cell->type == ID($not)) op = "!";
+ if (cell->type == ID($pos)) op = "";
+ if (cell->type == ID($neg)) op = "-";
- if (cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
continue;
}
- if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor"))
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
{
int width = GetSize(cell->getPort(ID::Y));
string expr_a, expr_b, op;
- if (cell->type == "$add") op = "+";
- if (cell->type == "$sub") op = "-";
- if (cell->type == "$mul") op = "*";
- if (cell->type == "$and") op = "&";
- if (cell->type == "$or") op = "|";
- if (cell->type == "$xor") op = "xor";
- if (cell->type == "$xnor") op = "xnor";
+ if (cell->type == ID($add)) op = "+";
+ if (cell->type == ID($sub)) op = "-";
+ if (cell->type == ID($mul)) op = "*";
+ if (cell->type == ID($and)) op = "&";
+ if (cell->type == ID($or)) op = "|";
+ if (cell->type == ID($xor)) op = "xor";
+ if (cell->type == ID($xnor)) op = "xnor";
- if (cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width)));
continue;
}
- if (cell->type.in("$div", "$mod"))
+ if (cell->type.in(ID($div), ID($mod)))
{
int width_y = GetSize(cell->getPort(ID::Y));
int width = max(width_y, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op;
- if (cell->type == "$div") op = "/";
- if (cell->type == "$mod") op = "mod";
+ if (cell->type == ID($div)) op = "/";
+ if (cell->type == ID($mod)) op = "mod";
- if (cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y));
continue;
}
- if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt"))
+ if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
{
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op;
- if (cell->type == "$eq") op = "=";
- if (cell->type == "$ne") op = "!=";
- if (cell->type == "$eqx") op = "=";
- if (cell->type == "$nex") op = "!=";
- if (cell->type == "$lt") op = "<";
- if (cell->type == "$le") op = "<=";
- if (cell->type == "$ge") op = ">=";
- if (cell->type == "$gt") op = ">";
+ if (cell->type == ID($eq)) op = "=";
+ if (cell->type == ID($ne)) op = "!=";
+ if (cell->type == ID($eqx)) op = "=";
+ if (cell->type == ID($nex)) op = "!=";
+ if (cell->type == ID($lt)) op = "<";
+ if (cell->type == ID($le)) op = "<=";
+ if (cell->type == ID($ge)) op = ">=";
+ if (cell->type == ID($gt)) op = ">";
- if (cell->getParam("\\A_SIGNED").as_bool())
+ if (cell->getParam(ID::A_SIGNED).as_bool())
{
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width);
continue;
}
- if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool"))
+ if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr;
- if (cell->type == "$reduce_and") expr = stringf("%s = !0ub%d_0", expr_a, width_a);
- if (cell->type == "$reduce_or") expr = stringf("%s != 0ub%d_0", expr_a, width_a);
- if (cell->type == "$reduce_bool") expr = stringf("%s != 0ub%d_0", expr_a, width_a);
+ if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
+ if (cell->type == ID($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
+ if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
continue;
}
- if (cell->type.in("$reduce_xor", "$reduce_xnor"))
+ if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
{
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_y = lvalue(cell->getPort(ID::Y));
expr += rvalue(bit);
}
- if (cell->type == "$reduce_xnor")
+ if (cell->type == ID($reduce_xnor))
expr = "!(" + expr + ")";
definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
continue;
}
- if (cell->type.in("$logic_and", "$logic_or"))
+ if (cell->type.in(ID($logic_and), ID($logic_or)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_b = GetSize(cell->getPort(ID::B));
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr;
- if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b;
- if (cell->type == "$logic_or") expr = expr_a + " | " + expr_b;
+ if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
+ if (cell->type == ID($logic_or)) expr = expr_a + " | " + expr_b;
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
continue;
}
- if (cell->type.in("$logic_not"))
+ if (cell->type.in(ID($logic_not)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
continue;
}
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
SigSpec sig_a = cell->getPort(ID::A);
continue;
}
- if (cell->type == "$dff")
+ if (cell->type == ID($dff))
{
- vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort("\\Q")), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))));
- assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D"))));
+ vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))));
+ assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D))));
continue;
}
- if (cell->type.in("$_BUF_", "$_NOT_"))
+ if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
- string op = cell->type == "$_NOT_" ? "!" : "";
+ string op = cell->type == ID($_NOT_) ? "!" : "";
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A))));
continue;
}
- if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
string op;
- if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_")) op = "&";
- if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_")) op = "|";
- if (cell->type.in("$_XOR_")) op = "xor";
- if (cell->type.in("$_XNOR_")) op = "xnor";
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) op = "&";
+ if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) op = "|";
+ if (cell->type.in(ID($_XOR_))) op = "xor";
+ if (cell->type.in(ID($_XNOR_))) op = "xnor";
- if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else
- if (cell->type.in("$_NAND_", "$_NOR_"))
+ if (cell->type.in(ID($_NAND_), ID($_NOR_)))
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else
continue;
}
- if (cell->type == "$_MUX_")
+ if (cell->type == ID($_MUX_))
{
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue;
}
- if (cell->type == "$_NMUX_")
+ if (cell->type == ID($_NMUX_))
{
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue;
}
- if (cell->type == "$_AOI3_")
+ if (cell->type == ID($_AOI3_))
{
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)),
- rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C"))));
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
continue;
}
- if (cell->type == "$_OAI3_")
+ if (cell->type == ID($_OAI3_))
{
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)),
- rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C"))));
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
continue;
}
- if (cell->type == "$_AOI4_")
+ if (cell->type == ID($_AOI4_))
{
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)),
- rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
continue;
}
- if (cell->type == "$_OAI4_")
+ if (cell->type == ID($_OAI4_))
{
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)),
- rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
+ rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
continue;
}
if (attr2comment)
as_comment = true;
for (auto it = attributes.begin(); it != attributes.end(); ++it) {
- if (it->first == "\\init" && regattr) continue;
+ if (it->first == ID::init && regattr) continue;
f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
f << stringf(" = ");
if (modattr && (it->second == State::S0 || it->second == Const(0)))
f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str());
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
f << stringf(" = ");
- dump_const(f, wire->attributes.at("\\init"));
+ dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else if (!wire->port_input && !wire->port_output)
std::string cellname(RTLIL::Cell *cell)
{
- if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q"))
+ if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort(ID::Q))
{
- RTLIL::SigSpec sig = cell->getPort("\\Q");
+ RTLIL::SigSpec sig = cell->getPort(ID::Q);
if (GetSize(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
- if (cell->type == "$_NOT_") {
+ if (cell->type == ID($_NOT_)) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
return true;
}
- if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) {
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_"))
+ if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
f << stringf("~(");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(" ");
- if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_"))
+ if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_)))
f << stringf("&");
- if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_"))
+ if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
f << stringf("|");
- if (cell->type.in("$_XOR_", "$_XNOR_"))
+ if (cell->type.in(ID($_XOR_), ID($_XNOR_)))
f << stringf("^");
dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" ");
- if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
f << stringf("~(");
dump_cell_expr_port(f, cell, "B", false);
- if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
+ if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
f << stringf(")");
f << stringf(";\n");
return true;
}
- if (cell->type == "$_MUX_") {
+ if (cell->type == ID($_MUX_)) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
return true;
}
- if (cell->type == "$_NMUX_") {
+ if (cell->type == ID($_NMUX_)) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = !(");
return true;
}
- if (cell->type.in("$_AOI3_", "$_OAI3_")) {
+ if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
- f << stringf(cell->type == "$_AOI3_" ? " & " : " | ");
+ f << stringf(cell->type == ID($_AOI3_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
- f << stringf(cell->type == "$_AOI3_" ? ") |" : ") &");
+ f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" ");
dump_cell_expr_port(f, cell, "C", false);
return true;
}
- if (cell->type.in("$_AOI4_", "$_OAI4_")) {
+ if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
- f << stringf(cell->type == "$_AOI4_" ? " & " : " | ");
+ f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false);
- f << stringf(cell->type == "$_AOI4_" ? ") |" : ") &");
+ f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" (");
dump_cell_expr_port(f, cell, "C", false);
- f << stringf(cell->type == "$_AOI4_" ? " & " : " | ");
+ f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "D", false);
f << stringf("));\n");
return true;
if (cell->type.begins_with("$_DFF_"))
{
std::string reg_name = cellname(cell);
- bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
+ bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) {
f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
- dump_reg_init(f, cell->getPort("\\Q"));
+ dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n";
}
dump_attributes(f, indent, cell->attributes);
f << stringf("%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg");
- dump_sigspec(f, cell->getPort("\\C"));
+ dump_sigspec(f, cell->getPort(ID::C));
if (cell->type[7] != '_') {
f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
- dump_sigspec(f, cell->getPort("\\R"));
+ dump_sigspec(f, cell->getPort(ID::R));
}
f << stringf(")\n");
if (cell->type[7] != '_') {
f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
- dump_sigspec(f, cell->getPort("\\R"));
+ dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n");
f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
f << stringf("%s" " else\n", indent.c_str());
if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Q"));
+ dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str());
}
char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
std::string reg_name = cellname(cell);
- bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
+ bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) {
f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
- dump_reg_init(f, cell->getPort("\\Q"));
+ dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n";
}
dump_attributes(f, indent, cell->attributes);
f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
- dump_sigspec(f, cell->getPort("\\C"));
+ dump_sigspec(f, cell->getPort(ID::C));
f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort(ID::S));
f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg");
- dump_sigspec(f, cell->getPort("\\R"));
+ dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n");
f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
- dump_sigspec(f, cell->getPort("\\R"));
+ dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n");
f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str());
if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Q"));
+ dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str());
}
#define HANDLE_BINOP(_type, _operator) \
if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; }
- HANDLE_UNIOP("$not", "~")
- HANDLE_UNIOP("$pos", "+")
- HANDLE_UNIOP("$neg", "-")
-
- HANDLE_BINOP("$and", "&")
- HANDLE_BINOP("$or", "|")
- HANDLE_BINOP("$xor", "^")
- HANDLE_BINOP("$xnor", "~^")
-
- HANDLE_UNIOP("$reduce_and", "&")
- HANDLE_UNIOP("$reduce_or", "|")
- HANDLE_UNIOP("$reduce_xor", "^")
- HANDLE_UNIOP("$reduce_xnor", "~^")
- HANDLE_UNIOP("$reduce_bool", "|")
-
- HANDLE_BINOP("$shl", "<<")
- HANDLE_BINOP("$shr", ">>")
- HANDLE_BINOP("$sshl", "<<<")
- HANDLE_BINOP("$sshr", ">>>")
-
- HANDLE_BINOP("$lt", "<")
- HANDLE_BINOP("$le", "<=")
- HANDLE_BINOP("$eq", "==")
- HANDLE_BINOP("$ne", "!=")
- HANDLE_BINOP("$eqx", "===")
- HANDLE_BINOP("$nex", "!==")
- HANDLE_BINOP("$ge", ">=")
- HANDLE_BINOP("$gt", ">")
-
- HANDLE_BINOP("$add", "+")
- HANDLE_BINOP("$sub", "-")
- HANDLE_BINOP("$mul", "*")
- HANDLE_BINOP("$div", "/")
- HANDLE_BINOP("$mod", "%")
- HANDLE_BINOP("$pow", "**")
-
- HANDLE_UNIOP("$logic_not", "!")
- HANDLE_BINOP("$logic_and", "&&")
- HANDLE_BINOP("$logic_or", "||")
+ HANDLE_UNIOP(ID($not), "~")
+ HANDLE_UNIOP(ID($pos), "+")
+ HANDLE_UNIOP(ID($neg), "-")
+
+ HANDLE_BINOP(ID($and), "&")
+ HANDLE_BINOP(ID($or), "|")
+ HANDLE_BINOP(ID($xor), "^")
+ HANDLE_BINOP(ID($xnor), "~^")
+
+ HANDLE_UNIOP(ID($reduce_and), "&")
+ HANDLE_UNIOP(ID($reduce_or), "|")
+ HANDLE_UNIOP(ID($reduce_xor), "^")
+ HANDLE_UNIOP(ID($reduce_xnor), "~^")
+ HANDLE_UNIOP(ID($reduce_bool), "|")
+
+ HANDLE_BINOP(ID($shl), "<<")
+ HANDLE_BINOP(ID($shr), ">>")
+ HANDLE_BINOP(ID($sshl), "<<<")
+ HANDLE_BINOP(ID($sshr), ">>>")
+
+ HANDLE_BINOP(ID($lt), "<")
+ HANDLE_BINOP(ID($le), "<=")
+ HANDLE_BINOP(ID($eq), "==")
+ HANDLE_BINOP(ID($ne), "!=")
+ HANDLE_BINOP(ID($eqx), "===")
+ HANDLE_BINOP(ID($nex), "!==")
+ HANDLE_BINOP(ID($ge), ">=")
+ HANDLE_BINOP(ID($gt), ">")
+
+ HANDLE_BINOP(ID($add), "+")
+ HANDLE_BINOP(ID($sub), "-")
+ HANDLE_BINOP(ID($mul), "*")
+ HANDLE_BINOP(ID($div), "/")
+ HANDLE_BINOP(ID($mod), "%")
+ HANDLE_BINOP(ID($pow), "**")
+
+ HANDLE_UNIOP(ID($logic_not), "!")
+ HANDLE_BINOP(ID($logic_and), "&&")
+ HANDLE_BINOP(ID($logic_or), "||")
#undef HANDLE_UNIOP
#undef HANDLE_BINOP
- if (cell->type == "$shift")
+ if (cell->type == ID($shift))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- if (cell->getParam("\\B_SIGNED").as_bool())
+ if (cell->getParam(ID::B_SIGNED).as_bool())
{
f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B));
return true;
}
- if (cell->type == "$shiftx")
+ if (cell->type == ID($shiftx))
{
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str());
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = %s[", temp_id.c_str());
- if (cell->getParam("\\B_SIGNED").as_bool())
+ if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B));
- if (cell->getParam("\\B_SIGNED").as_bool())
+ if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf(")");
- f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int());
+ f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int());
f << stringf("];\n");
return true;
}
- if (cell->type == "$mux")
+ if (cell->type == ID($mux))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
return true;
}
- if (cell->type == "$pmux")
+ if (cell->type == ID($pmux))
{
- int width = cell->parameters["\\WIDTH"].as_int();
+ int width = cell->parameters[ID::WIDTH].as_int();
int s_width = cell->getPort(ID::S).size();
std::string func_name = cellname(cell);
return true;
}
- if (cell->type == "$tribuf")
+ if (cell->type == ID($tribuf))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- dump_sigspec(f, cell->getPort("\\EN"));
+ dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(" ? ");
dump_sigspec(f, cell->getPort(ID::A));
- f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
+ f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int());
return true;
}
- if (cell->type == "$slice")
+ if (cell->type == ID($slice))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::A));
- f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
+ f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int());
return true;
}
- if (cell->type == "$concat")
+ if (cell->type == ID($concat))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
return true;
}
- if (cell->type == "$lut")
+ if (cell->type == ID($lut))
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ");
- dump_const(f, cell->parameters.at("\\LUT"));
+ dump_const(f, cell->parameters.at(ID::LUT));
f << stringf(" >> ");
dump_attributes(f, "", cell->attributes, ' ');
dump_sigspec(f, cell->getPort(ID::A));
return true;
}
- if (cell->type == "$dffsr")
+ if (cell->type == ID($dffsr))
{
- SigSpec sig_clk = cell->getPort("\\CLK");
- SigSpec sig_set = cell->getPort("\\SET");
- SigSpec sig_clr = cell->getPort("\\CLR");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_clk = cell->getPort(ID::CLK);
+ SigSpec sig_set = cell->getPort(ID::SET);
+ SigSpec sig_clr = cell->getPort(ID::CLR);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
- int width = cell->parameters["\\WIDTH"].as_int();
- bool pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
- bool pol_set = cell->parameters["\\SET_POLARITY"].as_bool();
- bool pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool();
+ int width = cell->parameters[ID::WIDTH].as_int();
+ bool pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
+ bool pol_set = cell->parameters[ID::SET_POLARITY].as_bool();
+ bool pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool();
std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(sig_q, reg_name);
return true;
}
- if (cell->type.in("$dff", "$adff", "$dffe"))
+ if (cell->type.in(ID($dff), ID($adff), ID($dffe)))
{
RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
bool pol_clk, pol_arst = false, pol_en = false;
- sig_clk = cell->getPort("\\CLK");
- pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
+ sig_clk = cell->getPort(ID::CLK);
+ pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
- if (cell->type == "$adff") {
- sig_arst = cell->getPort("\\ARST");
- pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool();
- val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]);
+ if (cell->type == ID($adff)) {
+ sig_arst = cell->getPort(ID::ARST);
+ pol_arst = cell->parameters[ID::ARST_POLARITY].as_bool();
+ val_arst = RTLIL::SigSpec(cell->parameters[ID::ARST_VALUE]);
}
- if (cell->type == "$dffe") {
- sig_en = cell->getPort("\\EN");
- pol_en = cell->parameters["\\EN_POLARITY"].as_bool();
+ if (cell->type == ID($dffe)) {
+ sig_en = cell->getPort(ID::EN);
+ pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
}
std::string reg_name = cellname(cell);
- bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
+ bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) {
- f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
- dump_reg_init(f, cell->getPort("\\Q"));
+ f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
+ dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n";
}
f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg");
dump_sigspec(f, sig_clk);
- if (cell->type == "$adff") {
+ if (cell->type == ID($adff)) {
f << stringf(" or %sedge ", pol_arst ? "pos" : "neg");
dump_sigspec(f, sig_arst);
}
f << stringf(")\n");
- if (cell->type == "$adff") {
+ if (cell->type == ID($adff)) {
f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!");
dump_sigspec(f, sig_arst);
f << stringf(")\n");
f << stringf("%s" " else\n", indent.c_str());
}
- if (cell->type == "$dffe") {
+ if (cell->type == ID($dffe)) {
f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
dump_sigspec(f, sig_en);
f << stringf(")\n");
if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Q"));
+ dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str());
}
return true;
}
- if (cell->type == "$dlatch")
+ if (cell->type == ID($dlatch))
{
RTLIL::SigSpec sig_en;
bool pol_en = false;
- sig_en = cell->getPort("\\EN");
- pol_en = cell->parameters["\\EN_POLARITY"].as_bool();
+ sig_en = cell->getPort(ID::EN);
+ pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
std::string reg_name = cellname(cell);
- bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
+ bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) {
- f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
- dump_reg_init(f, cell->getPort("\\Q"));
+ f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
+ dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n";
}
if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str());
- dump_sigspec(f, cell->getPort("\\Q"));
+ dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str());
}
return true;
}
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
- RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string();
- std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
- int abits = cell->parameters["\\ABITS"].as_int();
- int size = cell->parameters["\\SIZE"].as_int();
- int offset = cell->parameters["\\OFFSET"].as_int();
- int width = cell->parameters["\\WIDTH"].as_int();
- bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef());
+ RTLIL::IdString memid = cell->parameters[ID::MEMID].decode_string();
+ std::string mem_id = id(cell->parameters[ID::MEMID].decode_string());
+ int abits = cell->parameters[ID::ABITS].as_int();
+ int size = cell->parameters[ID::SIZE].as_int();
+ int offset = cell->parameters[ID::OFFSET].as_int();
+ int width = cell->parameters[ID::WIDTH].as_int();
+ bool use_init = !(RTLIL::SigSpec(cell->parameters[ID::INIT]).is_fully_undef());
// for memory block make something like:
// reg [7:0] memid [3:0];
{
for (int i=0; i<size; i++)
{
- RTLIL::Const element = cell->parameters["\\INIT"].extract(i*width, width);
+ RTLIL::Const element = cell->parameters[ID::INIT].extract(i*width, width);
for (int j=0; j<element.size(); j++)
{
switch (element[element.size()-j-1])
for (int i=0; i<size; i++)
{
f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i);
- dump_const(f, cell->parameters["\\INIT"].extract(i*width, width));
+ dump_const(f, cell->parameters[ID::INIT].extract(i*width, width));
f << stringf(";\n");
}
f << stringf("%s" "end\n", indent.c_str());
// create a list of reg declarations
std::vector<std::string> lof_reg_declarations;
- int nread_ports = cell->parameters["\\RD_PORTS"].as_int();
+ int nread_ports = cell->parameters[ID::RD_PORTS].as_int();
RTLIL::SigSpec sig_rd_clk, sig_rd_en, sig_rd_data, sig_rd_addr;
bool use_rd_clk, rd_clk_posedge, rd_transparent;
// read ports
for (int i=0; i < nread_ports; i++)
{
- sig_rd_clk = cell->getPort("\\RD_CLK").extract(i);
- sig_rd_en = cell->getPort("\\RD_EN").extract(i);
- sig_rd_data = cell->getPort("\\RD_DATA").extract(i*width, width);
- sig_rd_addr = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
- use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
- rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
- rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
+ sig_rd_clk = cell->getPort(ID::RD_CLK).extract(i);
+ sig_rd_en = cell->getPort(ID::RD_EN).extract(i);
+ sig_rd_data = cell->getPort(ID::RD_DATA).extract(i*width, width);
+ sig_rd_addr = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
+ use_rd_clk = cell->parameters[ID::RD_CLK_ENABLE].extract(i).as_bool();
+ rd_clk_posedge = cell->parameters[ID::RD_CLK_POLARITY].extract(i).as_bool();
+ rd_transparent = cell->parameters[ID::RD_TRANSPARENT].extract(i).as_bool();
if (use_rd_clk)
{
{
}
}
- int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int();
+ int nwrite_ports = cell->parameters[ID::WR_PORTS].as_int();
RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en;
bool wr_clk_posedge;
// write ports
for (int i=0; i < nwrite_ports; i++)
{
- sig_wr_clk = cell->getPort("\\WR_CLK").extract(i);
- sig_wr_data = cell->getPort("\\WR_DATA").extract(i*width, width);
- sig_wr_addr = cell->getPort("\\WR_ADDR").extract(i*abits, abits);
- sig_wr_en = cell->getPort("\\WR_EN").extract(i*width, width);
- wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool();
+ sig_wr_clk = cell->getPort(ID::WR_CLK).extract(i);
+ sig_wr_data = cell->getPort(ID::WR_DATA).extract(i*width, width);
+ sig_wr_addr = cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
+ sig_wr_en = cell->getPort(ID::WR_EN).extract(i*width, width);
+ wr_clk_posedge = cell->parameters[ID::WR_CLK_POLARITY].extract(i).as_bool();
{
std::ostringstream os;
dump_sigspec(os, sig_wr_clk);
return true;
}
- if (cell->type.in("$assert", "$assume", "$cover"))
+ if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{
f << stringf("%s" "always @* if (", indent.c_str());
- dump_sigspec(f, cell->getPort("\\EN"));
+ dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(") %s(", cell->type.c_str()+1);
dump_sigspec(f, cell->getPort(ID::A));
f << stringf(");\n");
return true;
}
- if (cell->type.in("$specify2", "$specify3"))
+ if (cell->type.in(ID($specify2), ID($specify3)))
{
f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str());
- SigSpec en = cell->getPort("\\EN");
+ SigSpec en = cell->getPort(ID::EN);
if (en != State::S1) {
f << stringf("if (");
- dump_sigspec(f, cell->getPort("\\EN"));
+ dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(") ");
}
f << "(";
- if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool())
- f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge ");
+ if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
+ f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
- dump_sigspec(f, cell->getPort("\\SRC"));
+ dump_sigspec(f, cell->getPort(ID::SRC));
f << " ";
- if (cell->getParam("\\SRC_DST_PEN").as_bool())
- f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-");
- f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> ");
+ if (cell->getParam(ID::SRC_DST_PEN).as_bool())
+ f << (cell->getParam(ID::SRC_DST_POL).as_bool() ? "+": "-");
+ f << (cell->getParam(ID::FULL).as_bool() ? "*> ": "=> ");
- if (cell->type == "$specify3") {
+ if (cell->type == ID($specify3)) {
f << "(";
- dump_sigspec(f, cell->getPort("\\DST"));
+ dump_sigspec(f, cell->getPort(ID::DST));
f << " ";
- if (cell->getParam("\\DAT_DST_PEN").as_bool())
- f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-");
+ if (cell->getParam(ID::DAT_DST_PEN).as_bool())
+ f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-");
f << ": ";
- dump_sigspec(f, cell->getPort("\\DAT"));
+ dump_sigspec(f, cell->getPort(ID::DAT));
f << ")";
} else {
- dump_sigspec(f, cell->getPort("\\DST"));
+ dump_sigspec(f, cell->getPort(ID::DST));
}
bool bak_decimal = decimal;
decimal = 1;
f << ") = (";
- dump_const(f, cell->getParam("\\T_RISE_MIN"));
+ dump_const(f, cell->getParam(ID::T_RISE_MIN));
f << ":";
- dump_const(f, cell->getParam("\\T_RISE_TYP"));
+ dump_const(f, cell->getParam(ID::T_RISE_TYP));
f << ":";
- dump_const(f, cell->getParam("\\T_RISE_MAX"));
+ dump_const(f, cell->getParam(ID::T_RISE_MAX));
f << ", ";
- dump_const(f, cell->getParam("\\T_FALL_MIN"));
+ dump_const(f, cell->getParam(ID::T_FALL_MIN));
f << ":";
- dump_const(f, cell->getParam("\\T_FALL_TYP"));
+ dump_const(f, cell->getParam(ID::T_FALL_TYP));
f << ":";
- dump_const(f, cell->getParam("\\T_FALL_MAX"));
+ dump_const(f, cell->getParam(ID::T_FALL_MAX));
f << ");\n";
decimal = bak_decimal;
return true;
}
- if (cell->type == "$specrule")
+ if (cell->type == ID($specrule))
{
f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str());
- string spec_type = cell->getParam("\\TYPE").decode_string();
+ IdString spec_type = cell->getParam(ID::TYPE).decode_string();
f << stringf("%s(", spec_type.c_str());
- if (cell->getParam("\\SRC_PEN").as_bool())
- f << (cell->getParam("\\SRC_POL").as_bool() ? "posedge ": "negedge ");
- dump_sigspec(f, cell->getPort("\\SRC"));
+ if (cell->getParam(ID::SRC_PEN).as_bool())
+ f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge ");
+ dump_sigspec(f, cell->getPort(ID::SRC));
- if (cell->getPort("\\SRC_EN") != State::S1) {
+ if (cell->getPort(ID::SRC_EN) != State::S1) {
f << " &&& ";
- dump_sigspec(f, cell->getPort("\\SRC_EN"));
+ dump_sigspec(f, cell->getPort(ID::SRC_EN));
}
f << ", ";
- if (cell->getParam("\\DST_PEN").as_bool())
- f << (cell->getParam("\\DST_POL").as_bool() ? "posedge ": "negedge ");
- dump_sigspec(f, cell->getPort("\\DST"));
+ if (cell->getParam(ID::DST_PEN).as_bool())
+ f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge ");
+ dump_sigspec(f, cell->getPort(ID::DST));
- if (cell->getPort("\\DST_EN") != State::S1) {
+ if (cell->getPort(ID::DST_EN) != State::S1) {
f << " &&& ";
- dump_sigspec(f, cell->getPort("\\DST_EN"));
+ dump_sigspec(f, cell->getPort(ID::DST_EN));
}
bool bak_decimal = decimal;
decimal = 1;
f << ", ";
- dump_const(f, cell->getParam("\\T_LIMIT_MIN"));
+ dump_const(f, cell->getParam(ID::T_LIMIT_MIN));
f << ": ";
- dump_const(f, cell->getParam("\\T_LIMIT_TYP"));
+ dump_const(f, cell->getParam(ID::T_LIMIT_TYP));
f << ": ";
- dump_const(f, cell->getParam("\\T_LIMIT_MAX"));
+ dump_const(f, cell->getParam(ID::T_LIMIT_MAX));
- if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") {
+ if (spec_type.in(ID($setuphold), ID($recrem), ID($fullskew))) {
f << ", ";
- dump_const(f, cell->getParam("\\T_LIMIT2_MIN"));
+ dump_const(f, cell->getParam(ID::T_LIMIT2_MIN));
f << ": ";
- dump_const(f, cell->getParam("\\T_LIMIT2_TYP"));
+ dump_const(f, cell->getParam(ID::T_LIMIT2_TYP));
f << ": ";
- dump_const(f, cell->getParam("\\T_LIMIT2_MAX"));
+ dump_const(f, cell->getParam(ID::T_LIMIT2_MAX));
}
f << ");\n";
}
}
- if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+ if (siminit && reg_ct.count(cell->type) && cell->hasPort(ID::Q)) {
std::stringstream ss;
- dump_reg_init(ss, cell->getPort("\\Q"));
+ dump_reg_init(ss, cell->getPort(ID::Q));
if (!ss.str().empty()) {
f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str());
f << ss.str();
active_initdata.clear();
for (auto wire : module->wires())
- if (wire->attributes.count("\\init")) {
+ if (wire->attributes.count(ID::init)) {
SigSpec sig = active_sigmap(wire);
- Const val = wire->attributes.at("\\init");
+ Const val = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
if (val[i] == State::S0 || val[i] == State::S1)
active_initdata[sig[i]] = val[i];
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
for (auto cell : module->cells())
{
- if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q"))
+ if (!reg_ct.count(cell->type) || !cell->hasPort(ID::Q))
continue;
- RTLIL::SigSpec sig = cell->getPort("\\Q");
+ RTLIL::SigSpec sig = cell->getPort(ID::Q);
if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk();
reg_wires.clear();
reg_ct.clear();
- reg_ct.insert("$dff");
- reg_ct.insert("$adff");
- reg_ct.insert("$dffe");
- reg_ct.insert("$dlatch");
-
- reg_ct.insert("$_DFF_N_");
- reg_ct.insert("$_DFF_P_");
-
- reg_ct.insert("$_DFF_NN0_");
- reg_ct.insert("$_DFF_NN1_");
- reg_ct.insert("$_DFF_NP0_");
- reg_ct.insert("$_DFF_NP1_");
- reg_ct.insert("$_DFF_PN0_");
- reg_ct.insert("$_DFF_PN1_");
- reg_ct.insert("$_DFF_PP0_");
- reg_ct.insert("$_DFF_PP1_");
-
- reg_ct.insert("$_DFFSR_NNN_");
- reg_ct.insert("$_DFFSR_NNP_");
- reg_ct.insert("$_DFFSR_NPN_");
- reg_ct.insert("$_DFFSR_NPP_");
- reg_ct.insert("$_DFFSR_PNN_");
- reg_ct.insert("$_DFFSR_PNP_");
- reg_ct.insert("$_DFFSR_PPN_");
- reg_ct.insert("$_DFFSR_PPP_");
+ reg_ct.insert(ID($dff));
+ reg_ct.insert(ID($adff));
+ reg_ct.insert(ID($dffe));
+ reg_ct.insert(ID($dlatch));
+
+ reg_ct.insert(ID($_DFF_N_));
+ reg_ct.insert(ID($_DFF_P_));
+
+ reg_ct.insert(ID($_DFF_NN0_));
+ reg_ct.insert(ID($_DFF_NN1_));
+ reg_ct.insert(ID($_DFF_NP0_));
+ reg_ct.insert(ID($_DFF_NP1_));
+ reg_ct.insert(ID($_DFF_PN0_));
+ reg_ct.insert(ID($_DFF_PN1_));
+ reg_ct.insert(ID($_DFF_PP0_));
+ reg_ct.insert(ID($_DFF_PP1_));
+
+ reg_ct.insert(ID($_DFFSR_NNN_));
+ reg_ct.insert(ID($_DFFSR_NNP_));
+ reg_ct.insert(ID($_DFFSR_NPN_));
+ reg_ct.insert(ID($_DFFSR_NPP_));
+ reg_ct.insert(ID($_DFFSR_PNN_));
+ reg_ct.insert(ID($_DFFSR_PNP_));
+ reg_ct.insert(ID($_DFFSR_PPN_));
+ reg_ct.insert(ID($_DFFSR_PPP_));
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (!inputs.count(sig_a))
compute_deps(sig_a, inputs);
- if (cell->type == "$_AND_") {
+ if (cell->type == ID($_AND_)) {
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
if (!inputs.count(sig_b))
compute_deps(sig_b, inputs);
}
- else if (cell->type == "$_NOT_") {
+ else if (cell->type == ID($_NOT_)) {
}
else log_abort();
}
return false;
RTLIL::State eval_ret = RTLIL::Sx;
- if (cell->type == "$_NOT_") {
+ if (cell->type == ID($_NOT_)) {
if (sig_a == State::S0) eval_ret = State::S1;
else if (sig_a == State::S1) eval_ret = State::S0;
}
- else if (cell->type == "$_AND_") {
+ else if (cell->type == ID($_AND_)) {
if (sig_a == State::S0) {
eval_ret = State::S0;
goto eval_end;
log_assert(boxUniqueId > 0);
uint32_t oldBoxNum = parse_xaiger_literal(f);
RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
- cell->setPort("\\i", SigSpec(State::S0, boxInputs));
- cell->setPort("\\o", SigSpec(State::S0, boxOutputs));
- cell->attributes["\\abc9_box_seq"] = oldBoxNum;
+ cell->setPort(ID(i), SigSpec(State::S0, boxInputs));
+ cell->setPort(ID(o), SigSpec(State::S0, boxOutputs));
+ cell->attributes[ID::abc9_box_seq] = oldBoxNum;
boxes.emplace_back(cell);
}
}
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
if (l3 == 0)
- q_wire->attributes["\\init"] = State::S0;
+ q_wire->attributes[ID::init] = State::S0;
else if (l3 == 1)
- q_wire->attributes["\\init"] = State::S1;
+ q_wire->attributes[ID::init] = State::S1;
else if (l3 == l1) {
- //q_wire->attributes["\\init"] = RTLIL::Sx;
+ //q_wire->attributes[ID::init] = RTLIL::Sx;
}
else
log_error("Line %u has invalid reset literal for latch!\n", line_count);
}
else {
// AIGER latches are assumed to be initialized to zero
- q_wire->attributes["\\init"] = State::S0;
+ q_wire->attributes[ID::init] = State::S0;
}
latches.push_back(q_wire);
}
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
if (l3 == 0)
- q_wire->attributes["\\init"] = State::S0;
+ q_wire->attributes[ID::init] = State::S0;
else if (l3 == 1)
- q_wire->attributes["\\init"] = State::S1;
+ q_wire->attributes[ID::init] = State::S1;
else if (l3 == l1) {
- //q_wire->attributes["\\init"] = RTLIL::Sx;
+ //q_wire->attributes[ID::init] = RTLIL::Sx;
}
else
log_error("Line %u has invalid reset literal for latch!\n", line_count);
}
else {
// AIGER latches are assumed to be initialized to zero
- q_wire->attributes["\\init"] = State::S0;
+ q_wire->attributes[ID::init] = State::S0;
}
latches.push_back(q_wire);
}
{
unsigned ci_count = 0, co_count = 0;
for (auto cell : boxes) {
- for (auto &bit : cell->connections_.at("\\i")) {
+ for (auto &bit : cell->connections_.at(ID(i))) {
log_assert(bit == State::S0);
log_assert(co_count < outputs.size());
bit = outputs[co_count++];
log_assert(bit.wire->port_output);
bit.wire->port_output = false;
}
- for (auto &bit : cell->connections_.at("\\o")) {
+ for (auto &bit : cell->connections_.at(ID(o))) {
log_assert(bit == State::S0);
log_assert((piNum + ci_count) < inputs.size());
bit = inputs[piNum + ci_count++];
log_assert(q->port_input);
q->port_input = false;
- auto ff = module->addCell(NEW_ID, "$__ABC9_FF_");
- ff->setPort("\\D", d);
- ff->setPort("\\Q", q);
- ff->attributes["\\abc9_mergeability"] = mergeability[i];
+ auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
+ ff->setPort(ID::D, d);
+ ff->setPort(ID::Q, q);
+ ff->attributes[ID::abc9_mergeability] = mergeability[i];
}
dict<RTLIL::IdString, int> wideports_cache;
int init;
mf >> init;
if (init < 2)
- wire->attributes["\\init"] = init;
+ wire->attributes[ID::init] = init;
}
else if (type == "box") {
RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
design->add(module);
for (auto cell : module->cells().to_vector()) {
- if (cell->type != "$lut") continue;
+ if (cell->type != ID($lut)) continue;
auto y_port = cell->getPort(ID::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
current_module->name = ast->str;
current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
ast->location.first_column, ast->location.last_line, ast->location.last_column);
- current_module->set_bool_attribute("\\cells_not_processed");
+ current_module->set_bool_attribute(ID::cells_not_processed);
current_ast_mod = ast;
AstNode *ast_before_simplify;
log("--- END OF AST DUMP ---\n");
}
- if (flag_nowb && ast->attributes.count("\\whitebox")) {
- delete ast->attributes.at("\\whitebox");
- ast->attributes.erase("\\whitebox");
+ if (flag_nowb && ast->attributes.count(ID::whitebox)) {
+ delete ast->attributes.at(ID::whitebox);
+ ast->attributes.erase(ID::whitebox);
}
- if (ast->attributes.count("\\lib_whitebox")) {
+ if (ast->attributes.count(ID::lib_whitebox)) {
if (!flag_lib || flag_nowb) {
- delete ast->attributes.at("\\lib_whitebox");
- ast->attributes.erase("\\lib_whitebox");
+ delete ast->attributes.at(ID::lib_whitebox);
+ ast->attributes.erase(ID::lib_whitebox);
} else {
- if (ast->attributes.count("\\whitebox")) {
- delete ast->attributes.at("\\whitebox");
- ast->attributes.erase("\\whitebox");
+ if (ast->attributes.count(ID::whitebox)) {
+ delete ast->attributes.at(ID::whitebox);
+ ast->attributes.erase(ID::whitebox);
}
- AstNode *n = ast->attributes.at("\\lib_whitebox");
- ast->attributes["\\whitebox"] = n;
- ast->attributes.erase("\\lib_whitebox");
+ AstNode *n = ast->attributes.at(ID::lib_whitebox);
+ ast->attributes[ID::whitebox] = n;
+ ast->attributes.erase(ID::lib_whitebox);
}
}
- if (!blackbox_module && ast->attributes.count("\\blackbox")) {
- AstNode *n = ast->attributes.at("\\blackbox");
+ if (!blackbox_module && ast->attributes.count(ID::blackbox)) {
+ AstNode *n = ast->attributes.at(ID::blackbox);
if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n");
blackbox_module = n->asBool();
}
- if (blackbox_module && ast->attributes.count("\\whitebox")) {
- AstNode *n = ast->attributes.at("\\whitebox");
+ if (blackbox_module && ast->attributes.count(ID::whitebox)) {
+ AstNode *n = ast->attributes.at(ID::whitebox);
if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n");
blackbox_module = !n->asBool();
}
- if (ast->attributes.count("\\noblackbox")) {
+ if (ast->attributes.count(ID::noblackbox)) {
if (blackbox_module) {
- AstNode *n = ast->attributes.at("\\noblackbox");
+ AstNode *n = ast->attributes.at(ID::noblackbox);
if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n");
blackbox_module = !n->asBool();
}
- delete ast->attributes.at("\\noblackbox");
- ast->attributes.erase("\\noblackbox");
+ delete ast->attributes.at(ID::noblackbox);
+ ast->attributes.erase(ID::noblackbox);
}
if (blackbox_module)
{
- if (ast->attributes.count("\\whitebox")) {
- delete ast->attributes.at("\\whitebox");
- ast->attributes.erase("\\whitebox");
+ if (ast->attributes.count(ID::whitebox)) {
+ delete ast->attributes.at(ID::whitebox);
+ ast->attributes.erase(ID::whitebox);
}
- if (ast->attributes.count("\\lib_whitebox")) {
- delete ast->attributes.at("\\lib_whitebox");
- ast->attributes.erase("\\lib_whitebox");
+ if (ast->attributes.count(ID::lib_whitebox)) {
+ delete ast->attributes.at(ID::lib_whitebox);
+ ast->attributes.erase(ID::lib_whitebox);
}
std::vector<AstNode*> new_children;
ast->children.swap(new_children);
- if (ast->attributes.count("\\blackbox") == 0) {
- ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
+ if (ast->attributes.count(ID::blackbox) == 0) {
+ ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false);
}
}
continue;
} else {
log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n",
- existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "",
+ existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column);
design->remove(existing_mod);
}
std::string original_name = this->name.str();
std::string changed_name = original_name + "_before_replacing_local_interfaces";
design->rename(this, changed_name);
- this->set_bool_attribute("\\to_delete");
+ this->set_bool_attribute(ID::to_delete);
// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
// new module.
mod->set_bool_attribute(ID::top);
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
- mod->set_bool_attribute("\\interfaces_replaced_in_module");
+ mod->set_bool_attribute(ID::interfaces_replaced_in_module);
}
// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
if (interfaces.size() > 0) {
- mod->set_bool_attribute("\\interfaces_replaced_in_module");
+ mod->set_bool_attribute(ID::interfaces_replaced_in_module);
}
} else {
// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool /*mayfail*/)
{
- bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox));
+ bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
AstNode *new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast, quiet);
using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations
-static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
+static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{
- std::stringstream sstr;
- sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, type);
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
cell->setPort(ID::A, arg);
- cell->parameters["\\Y_WIDTH"] = result_width;
+ cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire);
return wire;
}
return;
}
- std::stringstream sstr;
- sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
+ IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
cell->setPort(ID::A, sig);
- cell->parameters["\\Y_WIDTH"] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
cell->setPort(ID::Y, wire);
sig = wire;
}
// helper function for creating RTLIL code for binary operations
-static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
+static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
- std::stringstream sstr;
- sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
-
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
+ IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
+ RTLIL::Cell *cell = current_module->addCell(name, type);
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
- cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
+ cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
+ cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
cell->setPort(ID::A, left);
cell->setPort(ID::B, right);
- cell->parameters["\\Y_WIDTH"] = result_width;
+ cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire);
return wire;
}
std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
cell->setPort(ID::A, right);
cell->setPort(ID::B, left);
}
// create initial assignments for the temporary signals
- if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
+ if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) {
subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
for (auto &lvalue_c : lvalue.chunks()) {
RTLIL::SigSpec lhs = lvalue_c;
RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
- if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
+ if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
remove_unwanted_lvalue_bits(lhs, rhs);
actions.push_back(RTLIL::SigSig(lhs, rhs));
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should
// be instantiated for this type of AST node.
- std::string type_name;
+ IdString type_name;
current_filename = filename;
for(size_t i=0; i<children.size();i++) {
if(children[i]->type == AST_INTERFACEPORTTYPE) {
std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
- wire->attributes["\\interface_type"] = res.first;
+ wire->attributes[ID::interface_type] = res.first;
if (res.second != "")
- wire->attributes["\\interface_modport"] = res.second;
+ wire->attributes[ID::interface_modport] = res.second;
break;
}
}
current_module->connect(wire, val);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
- wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
+ wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
// with the individual signals:
if (is_interface) {
- RTLIL::Wire *dummy_wire;
- std::string dummy_wire_name = "$dummywireforinterface" + str;
- if (current_module->wires_.count(dummy_wire_name))
- dummy_wire = current_module->wires_[dummy_wire_name];
- else {
+ IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str());
+ RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name);
+ if (!dummy_wire) {
dummy_wire = current_module->addWire(dummy_wire_name);
dummy_wire->set_bool_attribute(ID::is_interface);
}
- RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
- return tmp;
+ return dummy_wire;
}
wire = current_module->wires_[str];
}
if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
- RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
+ RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast;
delete right_at_zero_ast;
delete fake_ast;
}
// generate cells for unary operations: $not, $pos, $neg
- if (0) { case AST_BIT_NOT: type_name = "$not"; }
- if (0) { case AST_POS: type_name = "$pos"; }
- if (0) { case AST_NEG: type_name = "$neg"; }
+ if (0) { case AST_BIT_NOT: type_name = ID($not); }
+ if (0) { case AST_POS: type_name = ID($pos); }
+ if (0) { case AST_NEG: type_name = ID($neg); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
is_signed = children[0]->is_signed;
}
// generate cells for binary operations: $and, $or, $xor, $xnor
- if (0) { case AST_BIT_AND: type_name = "$and"; }
- if (0) { case AST_BIT_OR: type_name = "$or"; }
- if (0) { case AST_BIT_XOR: type_name = "$xor"; }
- if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
+ if (0) { case AST_BIT_AND: type_name = ID($and); }
+ if (0) { case AST_BIT_OR: type_name = ID($or); }
+ if (0) { case AST_BIT_XOR: type_name = ID($xor); }
+ if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
}
// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
- if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
- if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
- if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
- if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
+ if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); }
+ if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); }
+ if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); }
+ if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
// generate cells for unary operations: $reduce_bool
// (this is actually just an $reduce_or, but for clarity a different cell type is used)
- if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
+ if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
}
// generate cells for binary operations: $shl, $shr, $sshl, $sshr
- if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
- if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
- if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
- if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
+ if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); }
+ if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); }
+ if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); }
+ if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed;
if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
- return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
- return binop2rtlil(this, "$pow", width, left, right);
+ return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
+ return binop2rtlil(this, ID($pow), width, left, right);
}
// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
- if (0) { case AST_LT: type_name = "$lt"; }
- if (0) { case AST_LE: type_name = "$le"; }
- if (0) { case AST_EQ: type_name = "$eq"; }
- if (0) { case AST_NE: type_name = "$ne"; }
- if (0) { case AST_EQX: type_name = "$eqx"; }
- if (0) { case AST_NEX: type_name = "$nex"; }
- if (0) { case AST_GE: type_name = "$ge"; }
- if (0) { case AST_GT: type_name = "$gt"; }
+ if (0) { case AST_LT: type_name = ID($lt); }
+ if (0) { case AST_LE: type_name = ID($le); }
+ if (0) { case AST_EQ: type_name = ID($eq); }
+ if (0) { case AST_NE: type_name = ID($ne); }
+ if (0) { case AST_EQX: type_name = ID($eqx); }
+ if (0) { case AST_NEX: type_name = ID($nex); }
+ if (0) { case AST_GE: type_name = ID($ge); }
+ if (0) { case AST_GT: type_name = ID($gt); }
{
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
}
// generate cells for binary operations: $add, $sub, $mul, $div, $mod
- if (0) { case AST_ADD: type_name = "$add"; }
- if (0) { case AST_SUB: type_name = "$sub"; }
- if (0) { case AST_MUL: type_name = "$mul"; }
- if (0) { case AST_DIV: type_name = "$div"; }
- if (0) { case AST_MOD: type_name = "$mod"; }
+ if (0) { case AST_ADD: type_name = ID($add); }
+ if (0) { case AST_SUB: type_name = ID($sub); }
+ if (0) { case AST_MUL: type_name = ID($mul); }
+ if (0) { case AST_DIV: type_name = ID($div); }
+ if (0) { case AST_MOD: type_name = ID($mod); }
{
if (width_hint < 0)
detectSignWidth(width_hint, sign_hint);
}
// generate cells for binary operations: $logic_and, $logic_or
- if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
- if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
+ if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
+ if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); }
{
RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL();
case AST_LOGIC_NOT:
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
- return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
+ return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
}
// generate multiplexer for ternary operator (aka ?:-operator)
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
if (cond.size() > 1)
- cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
+ cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed;
std::stringstream sstr;
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
- cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\ADDR", addr_sig);
- cell->setPort("\\DATA", RTLIL::SigSpec(wire));
+ cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::ADDR, addr_sig);
+ cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
- cell->parameters["\\MEMID"] = RTLIL::Const(str);
- cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
- cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
+ cell->parameters[ID::MEMID] = RTLIL::Const(str);
+ cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+ cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
if (!sign_hint)
is_signed = false;
std::stringstream sstr;
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
- RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
int mem_width, mem_size, addr_bits;
if (children[2]->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
num_words = int(children[2]->asInt(false));
- cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
+ cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
}
SigSpec addr_sig = children[0]->genRTLIL();
- cell->setPort("\\ADDR", addr_sig);
- cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
+ cell->setPort(ID::ADDR, addr_sig);
+ cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
- cell->parameters["\\MEMID"] = RTLIL::Const(str);
- cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
- cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
+ cell->parameters[ID::MEMID] = RTLIL::Const(str);
+ cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
+ cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
if (type == AST_MEMWR) {
- cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
- cell->setPort("\\EN", children[2]->genRTLIL());
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
+ cell->setPort(ID::EN, children[2]->genRTLIL());
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
}
- cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
+ cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}
break;
case AST_FAIR:
case AST_COVER:
{
- const char *celltype = nullptr;
- if (type == AST_ASSERT) celltype = "$assert";
- if (type == AST_ASSUME) celltype = "$assume";
- if (type == AST_LIVE) celltype = "$live";
- if (type == AST_FAIR) celltype = "$fair";
- if (type == AST_COVER) celltype = "$cover";
+ IdString celltype;
+ if (type == AST_ASSERT) celltype = ID($assert);
+ if (type == AST_ASSUME) celltype = ID($assume);
+ if (type == AST_LIVE) celltype = ID($live);
+ if (type == AST_FAIR) celltype = ID($fair);
+ if (type == AST_COVER) celltype = ID($cover);
log_assert(children.size() == 2);
en = current_module->ReduceBool(NEW_ID, en);
IdString cellname;
- if (str.empty()) {
- std::stringstream sstr;
- sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
- cellname = sstr.str();
- } else {
+ if (str.empty())
+ cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
+ else
cellname = str;
- }
RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
}
cell->setPort(ID::A, check);
- cell->setPort("\\EN", en);
+ cell->setPort(ID::EN, en);
}
break;
RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
- cell->set_bool_attribute("\\module_not_derived");
+ cell->set_bool_attribute(ID::module_not_derived);
for (auto it = children.begin(); it != children.end(); it++) {
AstNode *child = *it;
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- if (cell->type == "$specify2") {
- int src_width = GetSize(cell->getPort("\\SRC"));
- int dst_width = GetSize(cell->getPort("\\DST"));
- bool full = cell->getParam("\\FULL").as_bool();
+ if (cell->type == ID($specify2)) {
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ int dst_width = GetSize(cell->getPort(ID::DST));
+ bool full = cell->getParam(ID::FULL).as_bool();
if (!full && src_width != dst_width)
log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
- cell->setParam("\\SRC_WIDTH", Const(src_width));
- cell->setParam("\\DST_WIDTH", Const(dst_width));
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
- else if (cell->type == "$specify3") {
- int dat_width = GetSize(cell->getPort("\\DAT"));
- int dst_width = GetSize(cell->getPort("\\DST"));
+ else if (cell->type == ID($specify3)) {
+ int dat_width = GetSize(cell->getPort(ID::DAT));
+ int dst_width = GetSize(cell->getPort(ID::DST));
if (dat_width != dst_width)
log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
- int src_width = GetSize(cell->getPort("\\SRC"));
- cell->setParam("\\SRC_WIDTH", Const(src_width));
- cell->setParam("\\DST_WIDTH", Const(dst_width));
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
- else if (cell->type == "$specrule") {
- int src_width = GetSize(cell->getPort("\\SRC"));
- int dst_width = GetSize(cell->getPort("\\DST"));
- cell->setParam("\\SRC_WIDTH", Const(src_width));
- cell->setParam("\\DST_WIDTH", Const(dst_width));
+ else if (cell->type == ID($specrule)) {
+ int src_width = GetSize(cell->getPort(ID::SRC));
+ int dst_width = GetSize(cell->getPort(ID::DST));
+ cell->setParam(ID::SRC_WIDTH, Const(src_width));
+ cell->setParam(ID::DST_WIDTH, Const(dst_width));
}
}
break;
Cell *cell = current_module->addCell(myid, str.substr(1));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
- cell->parameters["\\WIDTH"] = width;
+ cell->parameters[ID::WIDTH] = width;
- if (attributes.count("\\reg")) {
- auto &attr = attributes.at("\\reg");
+ if (attributes.count(ID::reg)) {
+ auto &attr = attributes.at(ID::reg);
if (attr->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
- cell->attributes["\\reg"] = attr->asAttrConst();
+ cell->attributes[ID::reg] = attr->asAttrConst();
}
Wire *wire = current_module->addWire(myid + "_wire", width);
deep_recursion_warning = true;
while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
- if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg"))
+ if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
{
dict<AstNode*, pool<std::string>> mem2reg_places;
dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
bool this_nomeminit = flag_nomeminit;
log_assert((memflags & ~0x00ffff00) == 0);
- if (mem->get_bool_attribute("\\nomem2reg"))
+ if (mem->get_bool_attribute(ID::nomem2reg))
continue;
- if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit"))
+ if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit))
this_nomeminit = true;
if (memflags & AstNode::MEM2REG_FL_FORCED)
reg->is_reg = true;
reg->is_signed = node->is_signed;
for (auto &it : node->attributes)
- if (it.first != ID(mem2reg))
+ if (it.first != ID::mem2reg)
reg->attributes.emplace(it.first, it.second->clone());
reg->filename = node->filename;
reg->location = node->location;
if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
for (auto c : node->children[0]->children) {
if (!c->is_simple_const_expr()) {
- if (attributes.count("\\dynports"))
- delete attributes.at("\\dynports");
- attributes["\\dynports"] = AstNode::mkconst_int(1, true);
+ if (attributes.count(ID::dynports))
+ delete attributes.at(ID::dynports);
+ attributes[ID::dynports] = AstNode::mkconst_int(1, true);
}
}
}
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
wire->str = wire_id;
if (current_block)
- wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
current_ast_mod->children.push_back(wire);
while (wire->simplify(true, false, false, 1, -1, false, false)) { }
wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
current_ast_mod->children.push_back(wire_tmp);
current_scope[wire_tmp->str] = wire_tmp;
- wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
wire_tmp->is_logic = true;
wire->is_input = false;
wire->is_output = false;
wire->is_reg = true;
- wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
if (child->type == AST_ENUM_ITEM)
wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"];
wire_addr->str = id_addr;
wire_addr->is_reg = true;
wire_addr->was_checked = true;
- wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr);
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
wire_data->is_reg = true;
wire_data->was_checked = true;
wire_data->is_signed = mem_signed;
- wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data);
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
wire_addr->is_reg = true;
wire_addr->was_checked = true;
if (block)
- wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr);
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
wire_data->was_checked = true;
wire_data->is_signed = mem_signed;
if (block)
- wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data);
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
if (!strcmp(cmd, ".blackbox"))
{
- module->attributes["\\blackbox"] = RTLIL::Const(1);
+ module->attributes[ID::blackbox] = RTLIL::Const(1);
continue;
}
vector<Cell*> remove_cells;
for (auto cell : module->cells())
- if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
+ if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
remove_cells.push_back(cell);
}
for (auto cell : remove_cells)
module->remove(cell);
- Wire *true_wire = module->wire("$true");
- Wire *false_wire = module->wire("$false");
- Wire *undef_wire = module->wire("$undef");
+ Wire *true_wire = module->wire(ID($true));
+ Wire *false_wire = module->wire(ID($false));
+ Wire *undef_wire = module->wire(ID($undef));
if (true_wire != nullptr)
module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
}
if (init != nullptr && (init[0] == '0' || init[0] == '1'))
- blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
+ blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
if (clock == nullptr)
goto no_latch_clock;
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
- cell->setPort("\\D", blif_wire(d));
- cell->setPort("\\Q", blif_wire(q));
+ cell->setPort(ID::D, blif_wire(d));
+ cell->setPort(ID::Q, blif_wire(q));
}
}
finished_parsing_constval:
if (state == RTLIL::State::Sa)
state = RTLIL::State::S0;
- if (output_sig.as_wire()->name == "$undef")
+ if (output_sig.as_wire()->name == ID($undef))
state = RTLIL::State::Sx;
module->connect(RTLIL::SigSig(output_sig, state));
goto continue_without_read;
if (sop_mode)
{
- sopcell = module->addCell(NEW_ID, "$sop");
- sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
- sopcell->parameters["\\DEPTH"] = 0;
- sopcell->parameters["\\TABLE"] = RTLIL::Const();
+ sopcell = module->addCell(NEW_ID, ID($sop));
+ sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
+ sopcell->parameters[ID::DEPTH] = 0;
+ sopcell->parameters[ID::TABLE] = RTLIL::Const();
sopcell->setPort(ID::A, input_sig);
sopcell->setPort(ID::Y, output_sig);
sopmode = -1;
}
else
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
- cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
- cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
+ cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
+ cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig);
cell->setPort(ID::Y, output_sig);
- lutptr = &cell->parameters.at("\\LUT");
+ lutptr = &cell->parameters.at(ID::LUT);
lut_default_state = RTLIL::State::Sx;
lastcell = cell;
}
if (sopcell)
{
- log_assert(sopcell->parameters["\\WIDTH"].as_int() == input_len);
- sopcell->parameters["\\DEPTH"] = sopcell->parameters["\\DEPTH"].as_int() + 1;
+ log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
+ sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
for (int i = 0; i < input_len; i++)
switch (input[i]) {
case '0':
- sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
- sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break;
case '1':
- sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
- sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
break;
default:
- sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
- sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
+ sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break;
}
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, A);
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_));
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_));
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_));
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID));
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clk_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
clk_sig = it.second->getPort(ID::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, "");
- cell->setPort("\\D", data_sig);
- cell->setPort("\\Q", iq_sig);
- cell->setPort("\\C", clk_sig);
+ cell->setPort(ID::D, data_sig);
+ cell->setPort(ID::Q, iq_sig);
+ cell->setPort(ID::C, clk_sig);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
- cell->setPort("\\R", clear_sig);
+ cell->setPort(ID::R, clear_sig);
}
if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
- cell->setPort("\\R", preset_sig);
+ cell->setPort(ID::R, preset_sig);
}
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort(ID::S, preset_sig);
- cell->setPort("\\R", clear_sig);
+ cell->setPort(ID::R, clear_sig);
}
log_assert(!cell->type.empty());
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == enable_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
enable_sig = it.second->getPort(ID::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
- if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) {
+ if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
if (clear_polarity == true || clear_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
clear_enable = inv->getPort(ID::Y);
}
- RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
- RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
if (preset_polarity == false || preset_polarity != enable_polarity)
{
- RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
preset_enable = inv->getPort(ID::Y);
}
- RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
- RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
- cell->setPort("\\D", data_sig);
- cell->setPort("\\Q", iq_sig);
- cell->setPort("\\E", enable_sig);
+ cell->setPort(ID::D, data_sig);
+ cell->setPort(ID::Q, iq_sig);
+ cell->setPort(ID::E, enable_sig);
return true;
}
if (design->has(cell_name)) {
Module *existing_mod = design->module(cell_name);
- if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+ if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
} else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", log_id(cell_name));
continue;
} else {
- log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name));
+ log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
design->remove(existing_mod);
}
}
module->name = cell_name;
if (flag_lib)
- module->set_bool_attribute("\\blackbox");
+ module->set_bool_attribute(ID::blackbox);
for (auto &attr : attributes)
module->attributes[attr] = 1;
SigSpec dbits;
for (auto cell : candidates) {
- SigBit bit = sigmap(cell->getPort("\\D"));
+ SigBit bit = sigmap(cell->getPort(ID::D));
dbits_db[bit].insert(cell);
dbits.append(bit);
}
if (verific_verbose)
log(" replacing old ff %s on bit %d.\n", log_id(old_ff), i);
- SigBit old_q = old_ff->getPort("\\Q");
+ SigBit old_q = old_ff->getPort(ID::Q);
SigBit new_q = sig_q[i];
sigmap.add(old_q, new_q);
for (auto cell : candidates)
{
- SigBit clock = cell->getPort("\\CLK");
- bool clock_pol = cell->getParam("\\CLK_POLARITY").as_bool();
+ SigBit clock = cell->getPort(ID::CLK);
+ bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
database[make_pair(clock, int(clock_pol))].insert(cell);
}
if (is_blackbox(nl)) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
- module->set_bool_attribute("\\blackbox");
+ module->set_bool_attribute(ID::blackbox);
} else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
ascii_initdata++;
}
if (initval_valid) {
- RTLIL::Cell *cell = module->addCell(new_verific_id(net), "$meminit");
- cell->parameters["\\WORDS"] = 1;
+ RTLIL::Cell *cell = module->addCell(new_verific_id(net), ID($meminit));
+ cell->parameters[ID::WORDS] = 1;
if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound())
- cell->setPort("\\ADDR", word_idx);
+ cell->setPort(ID::ADDR, word_idx);
else
- cell->setPort("\\ADDR", memory->size - word_idx - 1);
- cell->setPort("\\DATA", initval);
- cell->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
- cell->parameters["\\ABITS"] = 32;
- cell->parameters["\\WIDTH"] = memory->width;
- cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
+ cell->setPort(ID::ADDR, memory->size - word_idx - 1);
+ cell->setPort(ID::DATA, initval);
+ cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
+ cell->parameters[ID::ABITS] = 32;
+ cell->parameters[ID::WIDTH] = memory->width;
+ cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
}
}
}
}
if (initval_valid)
- wire->attributes["\\init"] = initval;
+ wire->attributes[ID::init] = initval;
}
else
{
SigBit bit = net_map_at(it.first);
log_assert(bit.wire);
- if (bit.wire->attributes.count("\\init"))
- initval = bit.wire->attributes.at("\\init");
+ if (bit.wire->attributes.count(ID::init))
+ initval = bit.wire->attributes.at(ID::init);
while (GetSize(initval) < GetSize(bit.wire))
initval.bits.push_back(State::Sx);
if (it.second == '1')
initval.bits.at(bit.offset) = State::S1;
- bit.wire->attributes["\\init"] = initval;
+ bit.wire->attributes[ID::init] = initval;
}
for (auto net : anyconst_nets)
RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
- RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd");
- cell->parameters["\\MEMID"] = memory->name.str();
- cell->parameters["\\CLK_ENABLE"] = false;
- cell->parameters["\\CLK_POLARITY"] = true;
- cell->parameters["\\TRANSPARENT"] = false;
- cell->parameters["\\ABITS"] = GetSize(addr);
- cell->parameters["\\WIDTH"] = GetSize(data);
- cell->setPort("\\CLK", RTLIL::State::Sx);
- cell->setPort("\\EN", RTLIL::State::Sx);
- cell->setPort("\\ADDR", addr);
- cell->setPort("\\DATA", data);
+ RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
+ cell->parameters[ID::MEMID] = memory->name.str();
+ cell->parameters[ID::CLK_ENABLE] = false;
+ cell->parameters[ID::CLK_POLARITY] = true;
+ cell->parameters[ID::TRANSPARENT] = false;
+ cell->parameters[ID::ABITS] = GetSize(addr);
+ cell->parameters[ID::WIDTH] = GetSize(data);
+ cell->setPort(ID::CLK, RTLIL::State::Sx);
+ cell->setPort(ID::EN, RTLIL::State::Sx);
+ cell->setPort(ID::ADDR, addr);
+ cell->setPort(ID::DATA, data);
}
continue;
}
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
- RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr");
- cell->parameters["\\MEMID"] = memory->name.str();
- cell->parameters["\\CLK_ENABLE"] = false;
- cell->parameters["\\CLK_POLARITY"] = true;
- cell->parameters["\\PRIORITY"] = 0;
- cell->parameters["\\ABITS"] = GetSize(addr);
- cell->parameters["\\WIDTH"] = GetSize(data);
- cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
- cell->setPort("\\CLK", RTLIL::State::S0);
- cell->setPort("\\ADDR", addr);
- cell->setPort("\\DATA", data);
+ RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
+ cell->parameters[ID::MEMID] = memory->name.str();
+ cell->parameters[ID::CLK_ENABLE] = false;
+ cell->parameters[ID::CLK_POLARITY] = true;
+ cell->parameters[ID::PRIORITY] = 0;
+ cell->parameters[ID::ABITS] = GetSize(addr);
+ cell->parameters[ID::WIDTH] = GetSize(data);
+ cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
+ cell->setPort(ID::CLK, RTLIL::State::S0);
+ cell->setPort(ID::ADDR, addr);
+ cell->setPort(ID::DATA, data);
if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
- cell->parameters["\\CLK_ENABLE"] = true;
- cell->setPort("\\CLK", net_map_at(inst->GetClock()));
+ cell->parameters[ID::CLK_ENABLE] = true;
+ cell->setPort(ID::CLK, net_map_at(inst->GetClock()));
}
}
continue;
RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
if (inst->IsPrimitive() && mode_keep)
- cell->attributes["\\keep"] = 1;
+ cell->attributes[ID::keep] = 1;
dict<IdString, vector<SigBit>> cell_port_conns;
for (auto wire : module->wires())
{
- if (!wire->attributes.count("\\init"))
+ if (!wire->attributes.count(ID::init))
continue;
- Const &initval = wire->attributes.at("\\init");
+ Const &initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval); i++)
{
if (initval[i] != State::S0 && initval[i] != State::S1)
}
if (initval.is_fully_undef())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
}
}
if (GetSize(init_value) != 0) {
log_assert(GetSize(sig_q) == GetSize(init_value));
if (sig_q.is_wire()) {
- sig_q.as_wire()->attributes["\\init"] = init_value;
+ sig_q.as_wire()->attributes[ID::init] = init_value;
} else {
Wire *w = module->addWire(NEW_ID, GetSize(sig_q));
- w->attributes["\\init"] = init_value;
+ w->attributes[ID::init] = init_value;
module->connect(sig_q, w);
sig_q = w;
}
fcall->str = "\\$allconst";
if (attr_allseq)
fcall->str = "\\$allseq";
- fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
+ fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
}
} |
attr TOK_WILDCARD_CONNECT {
if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
- astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false);
+ astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
};
always_comb_or_latch:
AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1);
if ($2)
- node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
} always_cond {
AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1);
if ($2)
- node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
else
- node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false);
+ node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
AstNode *block = new AstNode(AST_BLOCK);
cell->parameters.sort();
for (auto p : cell->parameters)
{
- if (p.first == ID(A_WIDTH) && mkname_a_signed) {
+ if (p.first == ID::A_WIDTH && mkname_a_signed) {
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
- } else if (p.first == ID(B_WIDTH) && mkname_b_signed) {
+ } else if (p.first == ID::B_WIDTH && mkname_b_signed) {
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
} else {
mkname_last = name;
mkname_a_signed = false;
mkname_b_signed = false;
mkname_is_signed = false;
- if (p.first == ID(A_SIGNED)) {
+ if (p.first == ID::A_SIGNED) {
mkname_a_signed = true;
mkname_is_signed = p.second.as_bool();
}
- if (p.first == ID(B_SIGNED)) {
+ if (p.first == ID::B_SIGNED) {
mkname_b_signed = true;
mkname_is_signed = p.second.as_bool();
}
if (cell->type.in(ID($mux), ID($_MUX_)))
{
- int S = mk.inport(ID(S));
+ int S = mk.inport(ID::S);
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int width = GetSize(cell->getPort(ID::Y));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
- int carry = mk.inport(ID(CI));
- int binv = mk.inport(ID(BI));
+ int carry = mk.inport(ID::CI);
+ int binv = mk.inport(ID::BI);
for (auto &n : B)
n = mk.xor_gate(n, binv);
vector<int> X(width), CO(width);
for (int i = 0; i < width; i++)
X[i] = mk.xor_gate(A[i], B[i]);
mk.outport_vec(Y, ID::Y);
- mk.outport_vec(X, ID(X));
- mk.outport_vec(CO, ID(CO));
+ mk.outport_vec(X, ID::X);
+ mk.outport_vec(CO, ID::CO);
goto optimize;
}
{
int A = mk.inport(ID::A);
int B = mk.inport(ID::B);
- int C = mk.inport(ID(C));
+ int C = mk.inport(ID::C);
int Y = mk.nor_gate(mk.and_gate(A, B), C);
mk.outport(Y, ID::Y);
goto optimize;
{
int A = mk.inport(ID::A);
int B = mk.inport(ID::B);
- int C = mk.inport(ID(C));
+ int C = mk.inport(ID::C);
int Y = mk.nand_gate(mk.or_gate(A, B), C);
mk.outport(Y, ID::Y);
goto optimize;
{
int A = mk.inport(ID::A);
int B = mk.inport(ID::B);
- int C = mk.inport(ID(C));
- int D = mk.inport(ID(D));
+ int C = mk.inport(ID::C);
+ int D = mk.inport(ID::D);
int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
mk.outport(Y, ID::Y);
goto optimize;
{
int A = mk.inport(ID::A);
int B = mk.inport(ID::B);
- int C = mk.inport(ID(C));
- int D = mk.inport(ID(D));
+ int C = mk.inport(ID::C);
+ int D = mk.inport(ID::D);
int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
mk.outport(Y, ID::Y);
goto optimize;
void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, Y = ID::Y;
-
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- int a_width = GetSize(cell->getPort(A));
- int y_width = GetSize(cell->getPort(Y));
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+ int a_width = GetSize(cell->getPort(ID::A));
+ int y_width = GetSize(cell->getPort(ID::Y));
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
- db->add_edge(cell, A, i, Y, i, -1);
+ db->add_edge(cell, ID::A, i, ID::Y, i, -1);
else if (is_signed && a_width > 0)
- db->add_edge(cell, A, a_width-1, Y, i, -1);
+ db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
}
}
void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, B = ID::B, Y = ID::Y;
-
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- int a_width = GetSize(cell->getPort(A));
- int b_width = GetSize(cell->getPort(B));
- int y_width = GetSize(cell->getPort(Y));
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+ int a_width = GetSize(cell->getPort(ID::A));
+ int b_width = GetSize(cell->getPort(ID::B));
+ int y_width = GetSize(cell->getPort(ID::Y));
if (cell->type == ID($and) && !is_signed) {
if (a_width > b_width)
for (int i = 0; i < y_width; i++)
{
if (i < a_width)
- db->add_edge(cell, A, i, Y, i, -1);
+ db->add_edge(cell, ID::A, i, ID::Y, i, -1);
else if (is_signed && a_width > 0)
- db->add_edge(cell, A, a_width-1, Y, i, -1);
+ db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
if (i < b_width)
- db->add_edge(cell, B, i, Y, i, -1);
+ db->add_edge(cell, ID::B, i, ID::Y, i, -1);
else if (is_signed && b_width > 0)
- db->add_edge(cell, B, b_width-1, Y, i, -1);
+ db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1);
}
}
void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, Y = ID::Y;
-
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- int a_width = GetSize(cell->getPort(A));
- int y_width = GetSize(cell->getPort(Y));
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+ int a_width = GetSize(cell->getPort(ID::A));
+ int y_width = GetSize(cell->getPort(ID::Y));
if (is_signed && a_width == 1)
y_width = std::min(y_width, 1);
for (int i = 0; i < y_width; i++)
for (int k = 0; k <= i && k < a_width; k++)
- db->add_edge(cell, A, k, Y, i, -1);
+ db->add_edge(cell, ID::A, k, ID::Y, i, -1);
}
void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, B = ID::B, Y = ID::Y;
-
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
- int a_width = GetSize(cell->getPort(A));
- int b_width = GetSize(cell->getPort(B));
- int y_width = GetSize(cell->getPort(Y));
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
+ int a_width = GetSize(cell->getPort(ID::A));
+ int b_width = GetSize(cell->getPort(ID::B));
+ int y_width = GetSize(cell->getPort(ID::Y));
if (!is_signed && cell->type != ID($sub)) {
int ab_width = std::max(a_width, b_width);
for (int k = 0; k <= i; k++)
{
if (k < a_width)
- db->add_edge(cell, A, k, Y, i, -1);
+ db->add_edge(cell, ID::A, k, ID::Y, i, -1);
if (k < b_width)
- db->add_edge(cell, B, k, Y, i, -1);
+ db->add_edge(cell, ID::B, k, ID::Y, i, -1);
}
}
}
void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, Y = ID::Y;
-
- int a_width = GetSize(cell->getPort(A));
+ int a_width = GetSize(cell->getPort(ID::A));
for (int i = 0; i < a_width; i++)
- db->add_edge(cell, A, i, Y, 0, -1);
+ db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
}
void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, B = ID::B, Y = ID::Y;
-
- int a_width = GetSize(cell->getPort(A));
- int b_width = GetSize(cell->getPort(B));
+ int a_width = GetSize(cell->getPort(ID::A));
+ int b_width = GetSize(cell->getPort(ID::B));
for (int i = 0; i < a_width; i++)
- db->add_edge(cell, A, i, Y, 0, -1);
+ db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
for (int i = 0; i < b_width; i++)
- db->add_edge(cell, B, i, Y, 0, -1);
+ db->add_edge(cell, ID::B, i, ID::Y, 0, -1);
}
void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
- IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y;
-
- int a_width = GetSize(cell->getPort(A));
- int b_width = GetSize(cell->getPort(B));
- int s_width = GetSize(cell->getPort(S));
+ int a_width = GetSize(cell->getPort(ID::A));
+ int b_width = GetSize(cell->getPort(ID::B));
+ int s_width = GetSize(cell->getPort(ID::S));
for (int i = 0; i < a_width; i++)
{
- db->add_edge(cell, A, i, Y, i, -1);
+ db->add_edge(cell, ID::A, i, ID::Y, i, -1);
for (int k = i; k < b_width; k += a_width)
- db->add_edge(cell, B, k, Y, i, -1);
+ db->add_edge(cell, ID::B, k, ID::Y, i, -1);
for (int k = 0; k < s_width; k++)
- db->add_edge(cell, S, k, Y, i, -1);
+ db->add_edge(cell, ID::S, k, ID::Y, i, -1);
}
}
{
setup_internals_eval();
- IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y;
- IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT);
- IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST);
-
- setup_type(ID($tribuf), {A, EN}, {Y}, true);
-
- setup_type(ID($assert), {A, EN}, pool<RTLIL::IdString>(), true);
- setup_type(ID($assume), {A, EN}, pool<RTLIL::IdString>(), true);
- setup_type(ID($live), {A, EN}, pool<RTLIL::IdString>(), true);
- setup_type(ID($fair), {A, EN}, pool<RTLIL::IdString>(), true);
- setup_type(ID($cover), {A, EN}, pool<RTLIL::IdString>(), true);
- setup_type(ID($initstate), pool<RTLIL::IdString>(), {Y}, true);
- setup_type(ID($anyconst), pool<RTLIL::IdString>(), {Y}, true);
- setup_type(ID($anyseq), pool<RTLIL::IdString>(), {Y}, true);
- setup_type(ID($allconst), pool<RTLIL::IdString>(), {Y}, true);
- setup_type(ID($allseq), pool<RTLIL::IdString>(), {Y}, true);
- setup_type(ID($equiv), {A, B}, {Y}, true);
- setup_type(ID($specify2), {EN, SRC, DST}, pool<RTLIL::IdString>(), true);
- setup_type(ID($specify3), {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true);
- setup_type(ID($specrule), {EN_SRC, EN_DST, SRC, DST}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
+
+ setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
+ setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
+ setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
+ setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
+ setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
+ setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
+ setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
}
void setup_internals_eval()
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow),
ID($logic_and), ID($logic_or), ID($concat), ID($macc)
};
- IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y;
- IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X);
- IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN);
for (auto type : unary_ops)
- setup_type(type, {A}, {Y}, true);
+ setup_type(type, {ID::A}, {ID::Y}, true);
for (auto type : binary_ops)
- setup_type(type, {A, B}, {Y}, true);
+ setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
- setup_type(type, {A, B, S}, {Y}, true);
+ setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
- setup_type(ID($lcu), {P, G, CI}, {CO}, true);
- setup_type(ID($alu), {A, B, CI, BI}, {X, Y, CO}, true);
- setup_type(ID($fa), {A, B, C}, {X, Y}, true);
+ setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
+ setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
+ setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
}
void setup_internals_ff()
{
- IdString SET = ID(SET), CLR = ID(CLR), CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN);
- IdString Q = ID(Q), D = ID(D);
-
- setup_type(ID($sr), {SET, CLR}, {Q});
- setup_type(ID($ff), {D}, {Q});
- setup_type(ID($dff), {CLK, D}, {Q});
- setup_type(ID($dffe), {CLK, EN, D}, {Q});
- setup_type(ID($dffsr), {CLK, SET, CLR, D}, {Q});
- setup_type(ID($adff), {CLK, ARST, D}, {Q});
- setup_type(ID($dlatch), {EN, D}, {Q});
- setup_type(ID($dlatchsr), {EN, SET, CLR, D}, {Q});
-
+ setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
+ setup_type(ID($ff), {ID::D}, {ID::Q});
+ setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
+ setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
+ setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
+ setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
+ setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
+ setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
}
void setup_internals_mem()
{
setup_internals_ff();
- IdString CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN);
- IdString ADDR = ID(ADDR), DATA = ID(DATA), RD_EN = ID(RD_EN);
- IdString RD_CLK = ID(RD_CLK), RD_ADDR = ID(RD_ADDR), WR_CLK = ID(WR_CLK), WR_EN = ID(WR_EN);
- IdString WR_ADDR = ID(WR_ADDR), WR_DATA = ID(WR_DATA), RD_DATA = ID(RD_DATA);
- IdString CTRL_IN = ID(CTRL_IN), CTRL_OUT = ID(CTRL_OUT);
-
- setup_type(ID($memrd), {CLK, EN, ADDR}, {DATA});
- setup_type(ID($memwr), {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
- setup_type(ID($meminit), {ADDR, DATA}, pool<RTLIL::IdString>());
- setup_type(ID($mem), {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
+ setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
+ setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
+ setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
+ setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
- setup_type(ID($fsm), {CLK, ARST, CTRL_IN}, {CTRL_OUT});
+ setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
}
void setup_stdcells()
{
setup_stdcells_eval();
- IdString A = ID::A, E = ID(E), Y = ID::Y;
-
- setup_type(ID($_TBUF_), {A, E}, {Y}, true);
+ setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
}
void setup_stdcells_eval()
{
- IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D);
- IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H);
- IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L);
- IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P);
- IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V);
- IdString Y = ID::Y;
-
- setup_type(ID($_BUF_), {A}, {Y}, true);
- setup_type(ID($_NOT_), {A}, {Y}, true);
- setup_type(ID($_AND_), {A, B}, {Y}, true);
- setup_type(ID($_NAND_), {A, B}, {Y}, true);
- setup_type(ID($_OR_), {A, B}, {Y}, true);
- setup_type(ID($_NOR_), {A, B}, {Y}, true);
- setup_type(ID($_XOR_), {A, B}, {Y}, true);
- setup_type(ID($_XNOR_), {A, B}, {Y}, true);
- setup_type(ID($_ANDNOT_), {A, B}, {Y}, true);
- setup_type(ID($_ORNOT_), {A, B}, {Y}, true);
- setup_type(ID($_MUX_), {A, B, S}, {Y}, true);
- setup_type(ID($_NMUX_), {A, B, S}, {Y}, true);
- setup_type(ID($_MUX4_), {A, B, C, D, S, T}, {Y}, true);
- setup_type(ID($_MUX8_), {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true);
- setup_type(ID($_MUX16_), {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true);
- setup_type(ID($_AOI3_), {A, B, C}, {Y}, true);
- setup_type(ID($_OAI3_), {A, B, C}, {Y}, true);
- setup_type(ID($_AOI4_), {A, B, C, D}, {Y}, true);
- setup_type(ID($_OAI4_), {A, B, C, D}, {Y}, true);
+ setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
+ setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
+ setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
+ setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
+ setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
+ setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
+ setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
+ setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
+ setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
+ setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
+ setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
+ setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
}
void setup_stdcells_mem()
{
- IdString S = ID(S), R = ID(R), C = ID(C);
- IdString D = ID(D), Q = ID(Q), E = ID(E);
-
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
for (auto c1 : list_np)
for (auto c2 : list_np)
- setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q});
+ setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
- setup_type(ID($_FF_), {D}, {Q});
+ setup_type(ID($_FF_), {ID::D}, {ID::Q});
for (auto c1 : list_np)
- setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q});
+ setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
- setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q});
+ setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
- setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q});
+ setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
- setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q});
+ setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
for (auto c1 : list_np)
- setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q});
+ setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
- setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q});
+ setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
}
void clear()
signed1 = false, signed2 = false;
}
-#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
+#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
HANDLE_CELL_TYPE(not)
HANDLE_CELL_TYPE(and)
HANDLE_CELL_TYPE(or)
{
if (cell->type == ID($slice)) {
RTLIL::Const ret;
- int width = cell->parameters.at(ID(Y_WIDTH)).as_int();
- int offset = cell->parameters.at(ID(OFFSET)).as_int();
+ int width = cell->parameters.at(ID::Y_WIDTH).as_int();
+ int offset = cell->parameters.at(ID::OFFSET).as_int();
ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
return ret;
}
if (cell->type == ID($lut))
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
+ int width = cell->parameters.at(ID::WIDTH).as_int();
- std::vector<RTLIL::State> t = cell->parameters.at(ID(LUT)).bits;
+ std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
while (GetSize(t) < (1 << width))
t.push_back(State::S0);
t.resize(1 << width);
if (cell->type == ID($sop))
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- int depth = cell->parameters.at(ID(DEPTH)).as_int();
- std::vector<RTLIL::State> t = cell->parameters.at(ID(TABLE)).bits;
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ int depth = cell->parameters.at(ID::DEPTH).as_int();
+ std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
while (GetSize(t) < width*depth*2)
t.push_back(State::S0);
return default_ret;
}
- bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool();
- bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool();
- int result_len = cell->parameters.count(ID(Y_WIDTH)) > 0 ? cell->parameters[ID(Y_WIDTH)].as_int() : -1;
+ bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
+ bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
+ int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
}
{
if (cell->type == ID($lcu))
{
- RTLIL::SigSpec sig_p = cell->getPort(ID(P));
- RTLIL::SigSpec sig_g = cell->getPort(ID(G));
- RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
- RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO))));
+ RTLIL::SigSpec sig_p = cell->getPort(ID::P);
+ RTLIL::SigSpec sig_g = cell->getPort(ID::G);
+ RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+ RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
if (sig_co.is_fully_const())
return true;
if (sig_y.is_fully_const())
return true;
- if (cell->hasPort(ID(S))) {
- sig_s = cell->getPort(ID(S));
+ if (cell->hasPort(ID::S)) {
+ sig_s = cell->getPort(ID::S);
if (!eval(sig_s, undef, cell))
return false;
}
}
else if (cell->type == ID($fa))
{
- RTLIL::SigSpec sig_c = cell->getPort(ID(C));
- RTLIL::SigSpec sig_x = cell->getPort(ID(X));
+ RTLIL::SigSpec sig_c = cell->getPort(ID::C);
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell))
}
else if (cell->type == ID($alu))
{
- bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool();
- bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool();
+ bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
+ bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
- RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
- RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
+ RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+ RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
if (!eval(sig_a, undef, cell))
return false;
if (!eval(sig_bi, undef, cell))
return false;
- RTLIL::SigSpec sig_x = cell->getPort(ID(X));
- RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
+ RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend_u0(GetSize(sig_y), signed_a);
RTLIL::SigSpec sig_c, sig_d;
if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
- if (cell->hasPort(ID(C)))
- sig_c = cell->getPort(ID(C));
- if (cell->hasPort(ID(D)))
- sig_d = cell->getPort(ID(D));
+ if (cell->hasPort(ID::C))
+ sig_c = cell->getPort(ID::C);
+ if (cell->hasPort(ID::D))
+ sig_d = cell->getPort(ID::D);
}
if (sig_a.size() > 0 && !eval(sig_a, undef, cell))
X(A)
-X(B)
-X(S)
-X(Y)
-X(keep)
-X(src)
-X(whitebox)
-X(blackbox)
+X(abc9_box)
+X(abc9_box_id)
+X(abc9_box_seq)
+X(abc9_carry)
+X(abc9_flop)
+X(abc9_holes)
+X(abc9_init)
+X(abc9_lut)
+X(abc9_mergeability)
+X(abc9_scc)
+X(abc9_scc_id)
+X(abcgroup)
+X(ABITS)
+X(ADDR)
X(allconst)
X(allseq)
+X(always_comb)
+X(always_ff)
+X(always_latch)
X(anyconst)
X(anyseq)
+X(ARST)
+X(ARST_POLARITY)
+X(ARST_VALUE)
+X(A_SIGNED)
+X(A_WIDTH)
+X(B)
+X(BI)
+X(blackbox)
+X(B_SIGNED)
+X(B_WIDTH)
+X(C)
+X(cells_not_processed)
+X(CFG_ABITS)
+X(CFG_DBITS)
+X(CFG_INIT)
+X(CI)
+X(CLK)
+X(clkbuf_driver)
+X(clkbuf_inhibit)
+X(clkbuf_inv)
+X(clkbuf_sink)
+X(CLK_ENABLE)
+X(CLK_POLARITY)
+X(CLR)
+X(CLR_POLARITY)
+X(CO)
+X(CONFIG)
+X(CONFIG_WIDTH)
+X(CTRL_IN)
+X(CTRL_IN_WIDTH)
+X(CTRL_OUT)
+X(CTRL_OUT_WIDTH)
+X(D)
+X(DAT)
+X(DATA)
+X(DAT_DST_PEN)
+X(DAT_DST_POL)
X(defaultvalue)
+X(DELAY)
+X(DEPTH)
+X(DST)
+X(DST_EN)
+X(DST_PEN)
+X(DST_POL)
+X(DST_WIDTH)
+X(dynports)
+X(E)
+X(EDGE_EN)
+X(EDGE_POL)
+X(EN)
+X(EN_DST)
+X(EN_POLARITY)
+X(EN_SRC)
+X(equiv_merged)
+X(equiv_region)
+X(extract_order)
+X(F)
X(fsm_encoding)
+X(fsm_export)
+X(FULL)
X(full_case)
+X(G)
X(gclk)
+X(gentb_clock)
+X(gentb_constant)
+X(gentb_skip)
+X(H)
+X(hdlname)
+X(hierconn)
+X(I)
+X(INIT)
+X(init)
X(initial_top)
+X(interface_modport)
+X(interfaces_replaced_in_module)
+X(interface_type)
+X(invertible_pin)
+X(iopad_external_pin)
X(is_interface)
+X(J)
+X(K)
+X(keep)
+X(keep_hierarchy)
+X(L)
+X(lib_whitebox)
+X(localparam)
+X(LUT)
+X(lut_keep)
+X(M)
+X(maximize)
X(mem2reg)
+X(MEMID)
+X(minimize)
+X(module_not_derived)
+X(N)
+X(NAME)
X(noblackbox)
X(nolatches)
+X(nomem2init)
X(nomem2reg)
+X(nomeminit)
X(nosync)
+X(O)
+X(OFFSET)
+X(onehot)
+X(P)
X(parallel_case)
+X(parameter)
+X(PRIORITY)
+X(Q)
+X(qwp_position)
+X(R)
+X(RD_ADDR)
+X(RD_CLK)
+X(RD_CLK_ENABLE)
+X(RD_CLK_POLARITY)
+X(RD_DATA)
+X(RD_EN)
+X(RD_PORTS)
+X(RD_TRANSPARENT)
+X(reg)
+X(S)
+X(SET)
+X(SET_POLARITY)
+X(SIZE)
+X(SRC)
+X(src)
+X(SRC_DST_PEN)
+X(SRC_DST_POL)
+X(SRC_EN)
+X(SRC_PEN)
+X(SRC_POL)
+X(SRC_WIDTH)
+X(STATE_BITS)
+X(STATE_NUM)
+X(STATE_NUM_LOG2)
+X(STATE_RST)
+X(STATE_TABLE)
+X(submod)
+X(S_WIDTH)
+X(T)
+X(TABLE)
+X(techmap_autopurge)
+X(_TECHMAP_BITS_CONNMAP_)
+X(_TECHMAP_CELLTYPE_)
+X(techmap_celltype)
+X(techmap_maccmap)
+X(_TECHMAP_REPLACE_)
+X(techmap_simplemap)
+X(_techmap_special_)
+X(techmap_wrap)
+X(T_FALL_MAX)
+X(T_FALL_MIN)
+X(T_FALL_TYP)
+X(T_LIMIT)
+X(T_LIMIT2)
+X(T_LIMIT2_MAX)
+X(T_LIMIT2_MIN)
+X(T_LIMIT2_TYP)
+X(T_LIMIT_MAX)
+X(T_LIMIT_MIN)
+X(T_LIMIT_TYP)
+X(to_delete)
X(top)
+X(TRANS_NUM)
+X(TRANSPARENT)
+X(TRANS_TABLE)
+X(T_RISE_MAX)
+X(T_RISE_MIN)
+X(T_RISE_TYP)
+X(TYPE)
+X(U)
+X(unique)
+X(unused_bits)
+X(V)
X(wand)
+X(whitebox)
+X(WIDTH)
+X(wildcard_port_conns)
X(wor)
+X(WORDS)
+X(WR_ADDR)
+X(WR_CLK)
+X(WR_CLK_ENABLE)
+X(WR_CLK_POLARITY)
+X(WR_DATA)
+X(WR_EN)
+X(WR_PORTS)
+X(X)
+X(Y)
+X(Y_WIDTH)
ports.clear();
bit_ports = cell->getPort(ID::B);
- std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
+ std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
int config_cursor = 0;
#ifndef NDEBUG
- int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int();
+ int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
log_assert(GetSize(config_bits) >= config_width);
#endif
cell->setPort(ID::A, port_a);
cell->setPort(ID::B, bit_ports);
- cell->setParam(ID(CONFIG), config_bits);
- cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
- cell->setParam(ID(A_WIDTH), GetSize(port_a));
- cell->setParam(ID(B_WIDTH), GetSize(bit_ports));
+ cell->setParam(ID::CONFIG, config_bits);
+ cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
+ cell->setParam(ID::A_WIDTH, GetSize(port_a));
+ cell->setParam(ID::B_WIDTH, GetSize(bit_ports));
}
bool eval(RTLIL::Const &result) const
void RTLIL::AttrObject::set_src_attribute(const std::string &src)
{
if (src.empty())
- attributes.erase(ID(src));
+ attributes.erase(ID::src);
else
- attributes[ID(src)] = src;
+ attributes[ID::src] = src;
}
std::string RTLIL::AttrObject::get_src_attribute() const
{
std::string src;
- const auto it = attributes.find(ID(src));
+ const auto it = attributes.find(ID::src);
if (it != attributes.end())
src = it->second.decode_string();
return src;
int module_count = 0;
for (auto mod : selected_modules()) {
- if (mod->get_bool_attribute(ID(top)))
+ if (mod->get_bool_attribute(ID::top))
return mod;
module_count++;
module = mod;
error(__LINE__);
if (check_matched_sign) {
- log_assert(expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) != 0);
- bool a_is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
- bool b_is_signed = cell->parameters.at(ID(B_SIGNED)).as_bool();
+ log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
+ bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
+ bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
if (a_is_signed != b_is_signed)
error(__LINE__);
}
return;
if (cell->type.in(ID($not), ID($pos), ID($neg))) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED), /*expected=*/false);
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED, /*expected=*/false);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type.in(ID($shift), ID($shiftx))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(cell->type != ID($pow));
return;
}
if (cell->type == ID($fa)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)));
- port(ID(C), param(ID(WIDTH)));
- port(ID(X), param(ID(WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH));
+ port(ID::C, param(ID::WIDTH));
+ port(ID::X, param(ID::WIDTH));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($lcu)) {
- port(ID(P), param(ID(WIDTH)));
- port(ID(G), param(ID(WIDTH)));
- port(ID(CI), 1);
- port(ID(CO), param(ID(WIDTH)));
+ port(ID::P, param(ID::WIDTH));
+ port(ID::G, param(ID::WIDTH));
+ port(ID::CI, 1);
+ port(ID::CO, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($alu)) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID(CI), 1);
- port(ID(BI), 1);
- port(ID(X), param(ID(Y_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
- port(ID(CO), param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::CI, 1);
+ port(ID::BI, 1);
+ port(ID::X, param(ID::Y_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
+ port(ID::CO, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type == ID($macc)) {
- param(ID(CONFIG));
- param(ID(CONFIG_WIDTH));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param(ID::CONFIG);
+ param(ID::CONFIG_WIDTH);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
Macc().from_cell(cell);
return;
}
if (cell->type == ID($logic_not)) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($logic_and), ID($logic_or))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type == ID($slice)) {
- param(ID(OFFSET));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
- if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
+ param(ID::OFFSET);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
+ if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
error(__LINE__);
check_expected();
return;
}
if (cell->type == ID($concat)) {
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
check_expected();
return;
}
if (cell->type == ID($mux)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)));
- port(ID(S), 1);
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH));
+ port(ID::S, 1);
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($pmux)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
- port(ID(S), param(ID(S_WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
+ port(ID::S, param(ID::S_WIDTH));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($lut)) {
- param(ID(LUT));
- port(ID::A, param(ID(WIDTH)));
+ param(ID::LUT);
+ port(ID::A, param(ID::WIDTH));
port(ID::Y, 1);
check_expected();
return;
}
if (cell->type == ID($sop)) {
- param(ID(DEPTH));
- param(ID(TABLE));
- port(ID::A, param(ID(WIDTH)));
+ param(ID::DEPTH);
+ param(ID::TABLE);
+ port(ID::A, param(ID::WIDTH));
port(ID::Y, 1);
check_expected();
return;
}
if (cell->type == ID($sr)) {
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($ff)) {
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dff)) {
- param_bool(ID(CLK_POLARITY));
- port(ID(CLK), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dffe)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(EN_POLARITY));
- port(ID(CLK), 1);
- port(ID(EN), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dffsr)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(CLK), 1);
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($adff)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(ARST_POLARITY));
- param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
- port(ID(CLK), 1);
- port(ID(ARST), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param_bits(ID::ARST_VALUE, param(ID::WIDTH));
+ port(ID::CLK, 1);
+ port(ID::ARST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dlatch)) {
- param_bool(ID(EN_POLARITY));
- port(ID(EN), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::EN_POLARITY);
+ port(ID::EN, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dlatchsr)) {
- param_bool(ID(EN_POLARITY));
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(EN), 1);
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::EN, 1);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($fsm)) {
- param(ID(NAME));
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(ARST_POLARITY));
- param(ID(STATE_BITS));
- param(ID(STATE_NUM));
- param(ID(STATE_NUM_LOG2));
- param(ID(STATE_RST));
- param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
- param(ID(TRANS_NUM));
- param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
- port(ID(CLK), 1);
- port(ID(ARST), 1);
- port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
- port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
+ param(ID::NAME);
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param(ID::STATE_BITS);
+ param(ID::STATE_NUM);
+ param(ID::STATE_NUM_LOG2);
+ param(ID::STATE_RST);
+ param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
+ param(ID::TRANS_NUM);
+ param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
+ port(ID::CLK, 1);
+ port(ID::ARST, 1);
+ port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
+ port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
check_expected();
return;
}
if (cell->type == ID($memrd)) {
- param(ID(MEMID));
- param_bool(ID(CLK_ENABLE));
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(TRANSPARENT));
- port(ID(CLK), 1);
- port(ID(EN), 1);
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)));
+ param(ID::MEMID);
+ param_bool(ID::CLK_ENABLE);
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::TRANSPARENT);
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($memwr)) {
- param(ID(MEMID));
- param_bool(ID(CLK_ENABLE));
- param_bool(ID(CLK_POLARITY));
- param(ID(PRIORITY));
- port(ID(CLK), 1);
- port(ID(EN), param(ID(WIDTH)));
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)));
+ param(ID::MEMID);
+ param_bool(ID::CLK_ENABLE);
+ param_bool(ID::CLK_POLARITY);
+ param(ID::PRIORITY);
+ port(ID::CLK, 1);
+ port(ID::EN, param(ID::WIDTH));
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($meminit)) {
- param(ID(MEMID));
- param(ID(PRIORITY));
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
+ param(ID::MEMID);
+ param(ID::PRIORITY);
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
check_expected();
return;
}
if (cell->type == ID($mem)) {
- param(ID(MEMID));
- param(ID(SIZE));
- param(ID(OFFSET));
- param(ID(INIT));
- param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
- param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
- param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
- param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
- param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
- port(ID(RD_CLK), param(ID(RD_PORTS)));
- port(ID(RD_EN), param(ID(RD_PORTS)));
- port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
- port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
- port(ID(WR_CLK), param(ID(WR_PORTS)));
- port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
- port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
- port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
+ param(ID::MEMID);
+ param(ID::SIZE);
+ param(ID::OFFSET);
+ param(ID::INIT);
+ param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
+ param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
+ port(ID::RD_CLK, param(ID::RD_PORTS));
+ port(ID::RD_EN, param(ID::RD_PORTS));
+ port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
+ port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
+ port(ID::WR_CLK, param(ID::WR_PORTS));
+ port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
+ port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
+ port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($tribuf)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
- port(ID(EN), 1);
+ port(ID::A, param(ID::WIDTH));
+ port(ID::Y, param(ID::WIDTH));
+ port(ID::EN, 1);
check_expected();
return;
}
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
port(ID::A, 1);
- port(ID(EN), 1);
+ port(ID::EN, 1);
check_expected();
return;
}
}
if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
}
if (cell->type.in(ID($specify2), ID($specify3))) {
- param_bool(ID(FULL));
- param_bool(ID(SRC_DST_PEN));
- param_bool(ID(SRC_DST_POL));
- param(ID(T_RISE_MIN));
- param(ID(T_RISE_TYP));
- param(ID(T_RISE_MAX));
- param(ID(T_FALL_MIN));
- param(ID(T_FALL_TYP));
- param(ID(T_FALL_MAX));
- port(ID(EN), 1);
- port(ID(SRC), param(ID(SRC_WIDTH)));
- port(ID(DST), param(ID(DST_WIDTH)));
+ param_bool(ID::FULL);
+ param_bool(ID::SRC_DST_PEN);
+ param_bool(ID::SRC_DST_POL);
+ param(ID::T_RISE_MIN);
+ param(ID::T_RISE_TYP);
+ param(ID::T_RISE_MAX);
+ param(ID::T_FALL_MIN);
+ param(ID::T_FALL_TYP);
+ param(ID::T_FALL_MAX);
+ port(ID::EN, 1);
+ port(ID::SRC, param(ID::SRC_WIDTH));
+ port(ID::DST, param(ID::DST_WIDTH));
if (cell->type == ID($specify3)) {
- param_bool(ID(EDGE_EN));
- param_bool(ID(EDGE_POL));
- param_bool(ID(DAT_DST_PEN));
- param_bool(ID(DAT_DST_POL));
- port(ID(DAT), param(ID(DST_WIDTH)));
+ param_bool(ID::EDGE_EN);
+ param_bool(ID::EDGE_POL);
+ param_bool(ID::DAT_DST_PEN);
+ param_bool(ID::DAT_DST_POL);
+ port(ID::DAT, param(ID::DST_WIDTH));
}
check_expected();
return;
}
if (cell->type == ID($specrule)) {
- param(ID(TYPE));
- param_bool(ID(SRC_PEN));
- param_bool(ID(SRC_POL));
- param_bool(ID(DST_PEN));
- param_bool(ID(DST_POL));
- param(ID(T_LIMIT_MIN));
- param(ID(T_LIMIT_TYP));
- param(ID(T_LIMIT_MAX));
- param(ID(T_LIMIT2_MIN));
- param(ID(T_LIMIT2_TYP));
- param(ID(T_LIMIT2_MAX));
- port(ID(SRC_EN), 1);
- port(ID(DST_EN), 1);
- port(ID(SRC), param(ID(SRC_WIDTH)));
- port(ID(DST), param(ID(DST_WIDTH)));
+ param(ID::TYPE);
+ param_bool(ID::SRC_PEN);
+ param_bool(ID::SRC_POL);
+ param_bool(ID::DST_PEN);
+ param_bool(ID::DST_POL);
+ param(ID::T_LIMIT_MIN);
+ param(ID::T_LIMIT_TYP);
+ param(ID::T_LIMIT_MAX);
+ param(ID::T_LIMIT2_MIN);
+ param(ID::T_LIMIT2_TYP);
+ param(ID::T_LIMIT2_MAX);
+ port(ID::SRC_EN, 1);
+ port(ID::DST_EN, 1);
+ port(ID::SRC, param(ID::SRC_WIDTH));
+ port(ID::DST, param(ID::DST_WIDTH));
check_expected();
return;
}
if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
-
- if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID(E),1); check_expected(); return; }
-
- if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(S),1); port(ID(T),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(I),1); port(ID(J),1); port(ID(K),1); port(ID(L),1); port(ID(M),1); port(ID(N),1); port(ID(O),1); port(ID(P),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID(V),1); port(ID::Y,1); check_expected(); return; }
-
- if (cell->type == ID($_SR_NN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_NP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_PN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_PP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_FF_)) { port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFF_N_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
- if (cell->type == ID($_DFF_P_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
-
- if (cell->type == ID($_DFFE_NN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_NP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
-
- if (cell->type == ID($_DFF_NN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
-
- if (cell->type == ID($_DFFSR_NNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCH_N_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCH_P_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
+ if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
+
+ if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
+
+ if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
error(__LINE__);
}
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::Y, sig_y); \
cell->set_src_attribute(src); \
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(B_SIGNED)] = is_signed; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::B_SIGNED] = is_signed; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::B_WIDTH] = sig_b.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
cell->setPort(ID::Y, sig_y); \
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(B_SIGNED)] = false; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::B_SIGNED] = false; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::B_WIDTH] = sig_b.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
cell->setPort(ID::Y, sig_y); \
#define DEF_METHOD(_func, _type, _pmux) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(WIDTH)] = sig_a.size(); \
- if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
+ cell->parameters[ID::WIDTH] = sig_a.size(); \
+ if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
- cell->setPort(ID(S), sig_s); \
+ cell->setPort(ID::S, sig_s); \
cell->setPort(ID::Y, sig_y); \
cell->set_src_attribute(src); \
return cell; \
RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($pow));
- cell->parameters[ID(A_SIGNED)] = a_signed;
- cell->parameters[ID(B_SIGNED)] = b_signed;
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(B_WIDTH)] = sig_b.size();
- cell->parameters[ID(Y_WIDTH)] = sig_y.size();
+ cell->parameters[ID::A_SIGNED] = a_signed;
+ cell->parameters[ID::B_SIGNED] = b_signed;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::B_WIDTH] = sig_b.size();
+ cell->parameters[ID::Y_WIDTH] = sig_y.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
cell->setPort(ID::Y, sig_y);
RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($slice));
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(Y_WIDTH)] = sig_y.size();
- cell->parameters[ID(OFFSET)] = offset;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::Y_WIDTH] = sig_y.size();
+ cell->parameters[ID::OFFSET] = offset;
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($concat));
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(B_WIDTH)] = sig_b.size();
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::B_WIDTH] = sig_b.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
cell->setPort(ID::Y, sig_y);
RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($lut));
- cell->parameters[ID(LUT)] = lut;
- cell->parameters[ID(WIDTH)] = sig_a.size();
+ cell->parameters[ID::LUT] = lut;
+ cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($tribuf));
- cell->parameters[ID(WIDTH)] = sig_a.size();
+ cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
return cell;
{
RTLIL::Cell *cell = addCell(name, ID($assert));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($assume));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($live));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($fair));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($cover));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($sr));
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($ff));
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dff));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dffe));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dffsr));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($adff));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
- cell->parameters[ID(ARST_VALUE)] = arst_value;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(ARST), sig_arst);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::ARST_POLARITY] = arst_polarity;
+ cell->parameters[ID::ARST_VALUE] = arst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::ARST, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dlatch));
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($_FF_));
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(R), sig_arst);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($anyconst));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($anyseq));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($allconst));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($allseq));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
return;
if (type == ID($mux) || type == ID($pmux)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
if (type == ID($pmux))
- parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
+ parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
check();
return;
}
if (type == ID($lut) || type == ID($sop)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
return;
}
if (type == ID($fa)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
return;
}
if (type == ID($lcu)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
return;
}
if (connections_.count(ID::A)) {
if (signedness_ab) {
if (set_a_signed)
- parameters[ID(A_SIGNED)] = true;
- else if (parameters.count(ID(A_SIGNED)) == 0)
- parameters[ID(A_SIGNED)] = false;
+ parameters[ID::A_SIGNED] = true;
+ else if (parameters.count(ID::A_SIGNED) == 0)
+ parameters[ID::A_SIGNED] = false;
}
- parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
+ parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
}
if (connections_.count(ID::B)) {
if (signedness_ab) {
if (set_b_signed)
- parameters[ID(B_SIGNED)] = true;
- else if (parameters.count(ID(B_SIGNED)) == 0)
- parameters[ID(B_SIGNED)] = false;
+ parameters[ID::B_SIGNED] = true;
+ else if (parameters.count(ID::B_SIGNED) == 0)
+ parameters[ID::B_SIGNED] = false;
}
- parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
+ parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
}
if (connections_.count(ID::Y))
- parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
- if (connections_.count(ID(Q)))
- parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
+ if (connections_.count(ID::Q))
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
check();
}
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
{
bool is_signed = forced_signed;
- if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0)
- is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
+ if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)
+ is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
{
- bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool());
+ bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());
while (vec_a.size() < vec_y.size())
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_y.size() < vec_a.size())
int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
- int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0);
- int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0);
+ int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
+ int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int yy = model_undef ? ez->literal() : y;
{
int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
- int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0);
- int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0);
+ int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
+ int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
if (aoi_mode)
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
+ std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
+ std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
+ std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
+ std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
int maybe_a = ez->CONST_TRUE;
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{
- bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
+ bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
int extend_bit = ez->CONST_FALSE;
- if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
+ if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = a.back();
while (y.size() < a.size())
shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr))
- shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
+ shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type.in(ID($shift), ID($shiftx)))
- shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
+ shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
ez->assume(ez->vec_eq(shifted_a, yy));
std::vector<int> undef_a_shifted;
extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
- if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
+ if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = undef_a.back();
while (undef_y.size() < undef_a.size())
undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shift))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shiftx))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> a_u, b_u;
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
} else {
std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
if (cell->type == ID($div)) {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
else
ez->assume(ez->vec_eq(y_tmp, y_u));
} else {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
else
ez->assume(ez->vec_eq(y_tmp, chain_buf));
} else {
std::vector<int> div_zero_result;
if (cell->type == ID($div)) {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
only_first_one.at(0) = ez->CONST_TRUE;
} else {
int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
else
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> lut;
- for (auto bit : cell->getParam(ID(LUT)).bits)
+ for (auto bit : cell->getParam(ID::LUT).bits)
lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->CONST_FALSE);
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
- int width = cell->getParam(ID(WIDTH)).as_int();
- int depth = cell->getParam(ID(DEPTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int depth = cell->getParam(ID::DEPTH).as_int();
- vector<State> table_raw = cell->getParam(ID(TABLE)).bits;
+ vector<State> table_raw = cell->getParam(ID::TABLE).bits;
while (GetSize(table_raw) < 2*width*depth)
table_raw.push_back(State::S0);
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep);
+ std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
- std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
+ std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep);
+ std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
- std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
+ std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y));
if (cell->type == ID($lcu))
{
- std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep);
- std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep);
- std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
+ std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
+ std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
if (model_undef)
{
- std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep);
- std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep);
- std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
+ std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
+ std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
- std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
- std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep);
- std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
+ std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
+ std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(a, b, y, cell);
extendSignalWidth(a, b, x, cell);
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
- std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep);
+ std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
- std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
- std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
+ std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell);
{
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
- ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep));
+ ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
return true;
}
{
if (timestep == 1)
{
- initial_state.add((*sigmap)(cell->getPort(ID(Q))));
+ initial_state.add((*sigmap)(cell->getPort(ID::Q)));
}
else
{
- std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1);
- std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep);
+ std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
+ std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
- std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1);
- std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep);
+ std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
+ std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
- asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
+ asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true;
}
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
- assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
+ assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true;
}
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
- auto src = cell->getPort(ID(SRC));
- auto dst = cell->getPort(ID(DST));
+ auto src = cell->getPort(ID::SRC);
+ auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
- int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
- int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+ int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
+ int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
- if (cell->getParam(ID(FULL)).as_bool()) {
+ if (cell->getParam(ID::FULL).as_bool()) {
for (const auto &s : src)
for (const auto &d : dst) {
auto r = t.comb.insert(BitBit(s,d));
}
}
else if (cell->type == ID($specify3)) {
- auto src = cell->getPort(ID(SRC));
- auto dst = cell->getPort(ID(DST));
+ auto src = cell->getPort(ID::SRC);
+ auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
- int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
- int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+ int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
+ int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
}
}
else if (cell->type == ID($specrule)) {
- auto type = cell->getParam(ID(TYPE)).decode_string();
+ auto type = cell->getParam(ID::TYPE).decode_string();
if (type != "$setup" && type != "$setuphold")
continue;
- auto src = cell->getPort(ID(SRC));
- auto dst = cell->getPort(ID(DST));
+ auto src = cell->getPort(ID::SRC);
+ auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
- int max = cell->getParam(ID(T_LIMIT_MAX)).as_int();
+ int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
if (max <= 0) {
#define NEW_ID \
YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)
-// Create a statically allocated IdString object, using for example ID(A) or ID($add).
+// Create a statically allocated IdString object, using for example ID::A or ID($add).
//
-// Recipe for Converting old code that is using conversion of strings like "\\A" and
+// Recipe for Converting old code that is using conversion of strings like ID::A and
// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary.
//
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
- formal_cell->setPort(ID(A), wire);
+ formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
- formal_cell->setPort(ID(EN), State::S1);
+ formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
}
else {
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
- formal_cell->setPort(ID(EN), enable_wire);
+ formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
}
}
log_assert(module != nullptr);
if (!design->selected_whole_module(module->name))
continue;
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_bool_attribute(ID::blackbox))
continue;
selected_anything = true;
module->remove(remove_wires);
- module->set_bool_attribute("\\blackbox");
+ module->set_bool_attribute(ID::blackbox);
}
}
} BlackboxPass;
for (auto wire : mod->wires())
{
- if (!stage2 && wire->get_bool_attribute("$bugpoint"))
+ if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
continue;
if (wire->port_input || wire->port_output)
{
log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
- wire->set_bool_attribute("$bugpoint");
+ wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);
cell->unsetPort(it.first);
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
pool<IdString> fftypes;
- fftypes.insert("$sr");
- fftypes.insert("$ff");
- fftypes.insert("$dff");
- fftypes.insert("$dffe");
- fftypes.insert("$dffsr");
- fftypes.insert("$adff");
- fftypes.insert("$dlatch");
- fftypes.insert("$dlatchsr");
- fftypes.insert("$_DFFE_NN_");
- fftypes.insert("$_DFFE_NP_");
- fftypes.insert("$_DFFE_PN_");
- fftypes.insert("$_DFFE_PP_");
- fftypes.insert("$_DFFSR_NNN_");
- fftypes.insert("$_DFFSR_NNP_");
- fftypes.insert("$_DFFSR_NPN_");
- fftypes.insert("$_DFFSR_NPP_");
- fftypes.insert("$_DFFSR_PNN_");
- fftypes.insert("$_DFFSR_PNP_");
- fftypes.insert("$_DFFSR_PPN_");
- fftypes.insert("$_DFFSR_PPP_");
- fftypes.insert("$_DFF_NN0_");
- fftypes.insert("$_DFF_NN1_");
- fftypes.insert("$_DFF_NP0_");
- fftypes.insert("$_DFF_NP1_");
- fftypes.insert("$_DFF_N_");
- fftypes.insert("$_DFF_PN0_");
- fftypes.insert("$_DFF_PN1_");
- fftypes.insert("$_DFF_PP0_");
- fftypes.insert("$_DFF_PP1_");
- fftypes.insert("$_DFF_P_");
- fftypes.insert("$_DLATCHSR_NNN_");
- fftypes.insert("$_DLATCHSR_NNP_");
- fftypes.insert("$_DLATCHSR_NPN_");
- fftypes.insert("$_DLATCHSR_NPP_");
- fftypes.insert("$_DLATCHSR_PNN_");
- fftypes.insert("$_DLATCHSR_PNP_");
- fftypes.insert("$_DLATCHSR_PPN_");
- fftypes.insert("$_DLATCHSR_PPP_");
- fftypes.insert("$_DLATCH_N_");
- fftypes.insert("$_DLATCH_P_");
- fftypes.insert("$_FF_");
+ fftypes.insert(ID($sr));
+ fftypes.insert(ID($ff));
+ fftypes.insert(ID($dff));
+ fftypes.insert(ID($dffe));
+ fftypes.insert(ID($dffsr));
+ fftypes.insert(ID($adff));
+ fftypes.insert(ID($dlatch));
+ fftypes.insert(ID($dlatchsr));
+ fftypes.insert(ID($_DFFE_NN_));
+ fftypes.insert(ID($_DFFE_NP_));
+ fftypes.insert(ID($_DFFE_PN_));
+ fftypes.insert(ID($_DFFE_PP_));
+ fftypes.insert(ID($_DFFSR_NNN_));
+ fftypes.insert(ID($_DFFSR_NNP_));
+ fftypes.insert(ID($_DFFSR_NPN_));
+ fftypes.insert(ID($_DFFSR_NPP_));
+ fftypes.insert(ID($_DFFSR_PNN_));
+ fftypes.insert(ID($_DFFSR_PNP_));
+ fftypes.insert(ID($_DFFSR_PPN_));
+ fftypes.insert(ID($_DFFSR_PPP_));
+ fftypes.insert(ID($_DFF_NN0_));
+ fftypes.insert(ID($_DFF_NN1_));
+ fftypes.insert(ID($_DFF_NP0_));
+ fftypes.insert(ID($_DFF_NP1_));
+ fftypes.insert(ID($_DFF_N_));
+ fftypes.insert(ID($_DFF_PN0_));
+ fftypes.insert(ID($_DFF_PN1_));
+ fftypes.insert(ID($_DFF_PP0_));
+ fftypes.insert(ID($_DFF_PP1_));
+ fftypes.insert(ID($_DFF_P_));
+ fftypes.insert(ID($_DLATCHSR_NNN_));
+ fftypes.insert(ID($_DLATCHSR_NNP_));
+ fftypes.insert(ID($_DLATCHSR_NPN_));
+ fftypes.insert(ID($_DLATCHSR_NPP_));
+ fftypes.insert(ID($_DLATCHSR_PNN_));
+ fftypes.insert(ID($_DLATCHSR_PNP_));
+ fftypes.insert(ID($_DLATCHSR_PPN_));
+ fftypes.insert(ID($_DLATCHSR_PPP_));
+ fftypes.insert(ID($_DLATCH_N_));
+ fftypes.insert(ID($_DLATCH_P_));
+ fftypes.insert(ID($_FF_));
for (auto module : design->selected_whole_modules_warn())
{
if (wire->port_input && !wire->port_output)
for (auto bit : sigmap(wire))
if (bit.wire) wire_drivers_count[bit]++;
- if (wire->attributes.count("\\init")) {
- Const initval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sigmap(SigBit(wire, i)));
if (fftypes.count(cell->type) == 0)
continue;
- for (auto bit : sigmap(cell->getPort("\\Q")))
+ for (auto bit : sigmap(cell->getPort(ID::Q)))
init_bits.erase(bit);
}
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-assert") {
- constr_types.insert("$assert");
+ constr_types.insert(ID($assert));
continue;
}
if (args[argidx] == "-assume") {
- constr_types.insert("$assume");
+ constr_types.insert(ID($assume));
continue;
}
if (args[argidx] == "-live") {
- constr_types.insert("$live");
+ constr_types.insert(ID($live));
continue;
}
if (args[argidx] == "-fair") {
- constr_types.insert("$fair");
+ constr_types.insert(ID($fair));
continue;
}
if (args[argidx] == "-cover") {
- constr_types.insert("$cover");
+ constr_types.insert(ID($cover));
continue;
}
if (mode == 0 && args[argidx] == "-remove") {
extra_args(args, argidx, design);
if (constr_types.empty()) {
- constr_types.insert("$assert");
- constr_types.insert("$assume");
- constr_types.insert("$live");
- constr_types.insert("$fair");
- constr_types.insert("$cover");
+ constr_types.insert(ID($assert));
+ constr_types.insert(ID($assume));
+ constr_types.insert(ID($live));
+ constr_types.insert(ID($fair));
+ constr_types.insert(ID($cover));
}
if (mode == 0)
for (auto wire : module->wires())
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec initsig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) {
if (initval[i] == State::S0)
for (auto cell : module->selected_cells())
{
- if (cell->type == "$ff") {
- SigSpec D = sigmap(cell->getPort("\\D"));
- SigSpec Q = sigmap(cell->getPort("\\Q"));
+ if (cell->type == ID($ff)) {
+ SigSpec D = sigmap(cell->getPort(ID::D));
+ SigSpec Q = sigmap(cell->getPort(ID::Q));
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
}
- if (cell->type == "$dff") {
- SigSpec D = sigmap(cell->getPort("\\D"));
- SigSpec Q = sigmap(cell->getPort("\\Q"));
- SigSpec C = sigmap(cell->getPort("\\CLK"));
- bool clockpol = cell->getParam("\\CLK_POLARITY").as_bool();
+ if (cell->type == ID($dff)) {
+ SigSpec D = sigmap(cell->getPort(ID::D));
+ SigSpec Q = sigmap(cell->getPort(ID::Q));
+ SigSpec C = sigmap(cell->getPort(ID::CLK));
+ bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
}
while (true)
{
SigSpec A = sigmap(cell->getPort(ID::A));
- SigSpec EN = sigmap(cell->getPort("\\EN"));
+ SigSpec EN = sigmap(cell->getPort(ID::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break;
if (!init_zero.count(EN)) {
- if (cell->type == "$cover") break;
- if (cell->type.in("$assert", "$assume") && !init_one.count(A)) break;
+ if (cell->type == ID($cover)) break;
+ if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
}
const auto &A_map = ffmap.at(A);
break;
cell->setPort(ID::A, A_map.first);
- cell->setPort("\\EN", EN_map.first);
+ cell->setPort(ID::EN, EN_map.first);
}
}
else
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort(ID::A);
- SigSpec orig_en = cell->getPort("\\EN");
+ SigSpec orig_en = cell->getPort(ID::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
- new_en->attributes["\\init"] = State::S0;
+ new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
- cell->setPort("\\EN", new_en);
+ cell->setPort(ID::EN, new_en);
}
}
else
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
- w->attributes["\\init"] = State::S0;
+ w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
- cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN")));
+ cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
}
else
if (mode == 'c')
{
for (auto cell : constr_cells)
- if (assert2assume && cell->type == "$assert")
- cell->type = "$assume";
- else if (assume2assert && cell->type == "$assume")
- cell->type = "$assert";
- else if (live2fair && cell->type == "$live")
- cell->type = "$fair";
- else if (fair2live && cell->type == "$fair")
- cell->type = "$live";
+ if (assert2assume && cell->type == ID($assert))
+ cell->type = ID($assume);
+ else if (assume2assert && cell->type == ID($assume))
+ cell->type = ID($assert);
+ else if (live2fair && cell->type == ID($live))
+ cell->type = ID($fair);
+ else if (fair2live && cell->type == ID($fair))
+ cell->type = ID($live);
}
}
}
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
delete_cells.insert(it.second);
- if (it.second->type.in("$memrd", "$memwr") &&
- delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
+ if (it.second->type.in(ID($memrd), ID($memwr)) &&
+ delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0)
delete_cells.insert(it.second);
}
for (auto &node : nodes)
if (node.cell != nullptr)
- node.cell->attributes["\\qwp_position"] = stringf("%f %f", node.pos, node.alt_pos);
+ node.cell->attributes[ID::qwp_position] = stringf("%f %f", node.pos, node.alt_pos);
vector<double> edge_lengths;
vector<double> weighted_edge_lengths;
if (!design->selected(module))
continue;
- if (module->get_bool_attribute("\\blackbox"))
+ if (module->get_bool_attribute(ID::blackbox))
continue;
- module->set_bool_attribute("\\whitebox", !module->get_bool_attribute("\\whitebox"));
+ module->set_bool_attribute(ID::whitebox, !module->get_bool_attribute(ID::whitebox));
}
}
} WbflipPass;
pool<Wire*> initwires;
pool<IdString> fftypes;
- fftypes.insert("$dff");
- fftypes.insert("$dffe");
- fftypes.insert("$dffsr");
- fftypes.insert("$adff");
+ fftypes.insert(ID($dff));
+ fftypes.insert(ID($dffe));
+ fftypes.insert(ID($dffsr));
+ fftypes.insert(ID($adff));
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
if (!fftypes.count(cell->type))
continue;
- for (auto bit : sigmap(cell->getPort("\\Q")))
+ for (auto bit : sigmap(cell->getPort(ID::Q)))
ffbits.insert(bit);
}
for (auto wire : initwires)
{
- Const &initval = wire->attributes["\\init"];
+ Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
}
if (initval.is_fully_undef())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
initwires.clear();
if (wire->name[0] == (wire_types ? '\\' : '$'))
continue;
- if (!wire->attributes.count("\\init"))
+ if (!wire->attributes.count(ID::init))
continue;
- Const &initval = wire->attributes["\\init"];
+ Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
continue;
}
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
- cell->parameters["\\OFFSET"] = offset;
- cell->parameters["\\A_WIDTH"] = sig_a.size();
- cell->parameters["\\Y_WIDTH"] = sig.size();
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
+ cell->parameters[ID::OFFSET] = offset;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
- cell->parameters["\\A_WIDTH"] = new_sig.size();
- cell->parameters["\\B_WIDTH"] = sig2.size();
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
+ cell->parameters[ID::A_WIDTH] = new_sig.size();
+ cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
if (wire->attributes.count(ID::src))
new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
- if (wire->attributes.count("\\keep"))
- new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
+ if (wire->attributes.count(ID::keep))
+ new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
- if (wire->attributes.count("\\init")) {
- Const old_init = wire->attributes.at("\\init"), new_init;
+ if (wire->attributes.count(ID::init)) {
+ Const old_init = wire->attributes.at(ID::init), new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
- new_wire->attributes["\\init"] = new_init;
+ new_wire->attributes[ID::init] = new_init;
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
if (width_mode)
{
- if (cell_type.in("$not", "$pos", "$neg",
- "$logic_not", "$logic_and", "$logic_or",
- "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
- "$lut", "$and", "$or", "$xor", "$xnor",
- "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
- "$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) {
+ if (cell_type.in(ID($not), ID($pos), ID($neg),
+ ID($logic_not), ID($logic_and), ID($logic_or),
+ ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
+ ID($lut), ID($and), ID($or), ID($xor), ID($xnor),
+ ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
+ ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
+ ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) {
int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
- else if (cell_type.in("$mux", "$pmux"))
+ else if (cell_type.in(ID($mux), ID($pmux)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
- else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
- cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
+ else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Q)));
}
if (!cell_area.empty()) {
if (tech == "xilinx")
{
- int lut6_cnt = num_cells_by_type["\\LUT6"];
- int lut5_cnt = num_cells_by_type["\\LUT5"];
- int lut4_cnt = num_cells_by_type["\\LUT4"];
- int lut3_cnt = num_cells_by_type["\\LUT3"];
- int lut2_cnt = num_cells_by_type["\\LUT2"];
- int lut1_cnt = num_cells_by_type["\\LUT1"];
+ int lut6_cnt = num_cells_by_type[ID(LUT6)];
+ int lut5_cnt = num_cells_by_type[ID(LUT5)];
+ int lut4_cnt = num_cells_by_type[ID(LUT4)];
+ int lut3_cnt = num_cells_by_type[ID(LUT3)];
+ int lut2_cnt = num_cells_by_type[ID(LUT2)];
+ int lut1_cnt = num_cells_by_type[ID(LUT1)];
int lc_cnt = 0;
lc_cnt += lut6_cnt;
if (gate_costs.count(ctype))
tran_cnt += cnum * gate_costs.at(ctype);
- else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
+ else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
tran_cnt += cnum * 16;
else
tran_cnt_exact = false;
continue;
if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
- if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
+ if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
continue;
- if (cell->type == "$memrd" && conn.first == "\\DATA")
+ if (cell->type == ID($memrd) && conn.first == ID::DATA)
continue;
}
for (int i = 0; i < GetSize(gold_signal); i++) {
Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
- equiv_cell->set_bool_attribute("\\keep");
+ equiv_cell->set_bool_attribute(ID::keep);
to_equiv_bits[gold_signal[i]] = equiv_signal[i];
to_equiv_bits[gate_signal[i]] = equiv_signal[i];
added_equiv_cells.insert(equiv_cell);
log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
cell_warn_cache.insert(cell);
}
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
if (bit_a != bit_b) {
pool<Cell*> unproven_equiv_cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.insert(cell);
}
void init_bit2driven()
{
for (auto cell : equiv_mod->cells()) {
- if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+ if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue;
for (auto &conn : cell->connections())
{
{
for (auto cell : module->cells())
{
- if (cell->type == "$equiv")
+ if (cell->type == ID($equiv))
equiv_cells.insert(cell->name);
for (auto &port : cell->connections())
for (auto cell : module->cells())
{
- if (cell_regions.count(cell->name) || cell->type != "$equiv")
+ if (cell_regions.count(cell->name) || cell->type != ID($equiv))
continue;
SigSpec sig_a = sigmap(cell->getPort(ID::A));
{
if (cell_regions.count(cell->name)) {
int r = final_region_map.at(cell_regions.at(cell->name));
- cell->attributes["\\equiv_region"] = Const(r);
+ cell->attributes[ID::equiv_region] = Const(r);
region_cell_count[r]++;
} else
- cell->attributes.erase("\\equiv_region");
+ cell->attributes.erase(ID::equiv_region);
}
for (auto wire : module->wires())
if (GetSize(regions) == 1) {
int r = final_region_map.at(*regions.begin());
- wire->attributes["\\equiv_region"] = Const(r);
+ wire->attributes[ID::equiv_region] = Const(r);
region_wire_count[r]++;
} else
- wire->attributes.erase("\\equiv_region");
+ wire->attributes.erase(ID::equiv_region);
}
for (int i = 0; i < next_final_region; i++)
if (cone.count(c))
return;
- if (c->type == "$equiv" && !seed_cells.count(c)) {
+ if (c->type == ID($equiv) && !seed_cells.count(c)) {
leaves.insert(c);
return;
}
for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first))
continue;
- if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode)
+ if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode)
continue;
for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit))
// find seed cells
for (auto c : source_module->selected_cells())
- if (c->type == "$equiv") {
+ if (c->type == ID($equiv)) {
log("Seed $equiv cell: %s\n", log_id(c));
seed_cells.insert(c);
}
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
- if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B))
+ if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) {
- string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y));
+ string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';
}
if (mode_trigger) {
- auto w = miter_module->addWire("\\trigger");
+ auto w = miter_module->addWire(ID(trigger));
w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w);
}
for (auto cell : module->cells())
{
- if (cell->type != "$equiv") {
+ if (cell->type != ID($equiv)) {
for (auto &port : cell->connections()) {
if (cell->input(port.first))
for (auto bit : sigmap(port.second))
rewrite_sigmap.add(chunk, make_input(chunk));
for (auto cell : module->cells())
- if (cell->type == "$equiv")
+ if (cell->type == ID($equiv))
cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports();
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
+ if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell);
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : sigmap(conn.second)) {
- if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) {
- if (!conn.first.in("\\CLK", "\\C"))
+ if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
+ if (!conn.first.in(ID::CLK, ID::C))
next_seed.insert(bit);
} else
find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) {
+ if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
auto bit = sigmap(cell->getPort(ID::Y).as_bit());
auto bit_group = bit;
if (!nogroup && bit_group.wire)
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
for (auto cell : module->cells()) {
- if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+ if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue;
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
int proven_equiv_cells = 0;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.push_back(cell);
else
module->connect(sig_b, sig_a);
}
- auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged");
+ auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b));
- cell_a->add_strpool_attribute("\\equiv_merged", merged_attr);
+ cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b);
}
pool<IdString> cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a);
}
for (auto cell : module->selected_cells())
- if (cell->type == "$equiv") {
+ if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
}
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{
- pool<IdString> fwonly_cells({ "$equiv" });
+ pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false;
bool mode_fwd = false;
int max_iter = -1;
sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list)
{
- if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) {
+ if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) {
goto ret_false;
}
RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0)
continue;
- if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig)
+ if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
continue;
if (cellport.second != ID::A && cellport.second != ID::B)
return false;
{
bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
- bool has_init_attr = wire->attributes.count("\\init") > 0;
+ bool has_init_attr = wire->attributes.count(ID::init) > 0;
bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
bool looks_like_state_reg = false, looks_like_good_state_reg = false;
bool is_self_resetting = false;
for (auto &cellport : cellport_list)
{
- if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
+ if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q)
continue;
muxtree_cells.clear();
pool<Cell*> recursion_monitor;
- RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
- RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
+ RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
+ RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire))
RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false;
- if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
+ if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
set_output = true;
- if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
+ if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
clr_output = true;
if (set_output || clr_output) {
ct.setup_stdcells();
ct.setup_stdcells_mem();
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- module = mod_it.second;
+ module = mod;
assign_map.set(module);
sig2driver.clear();
sig2user.clear();
sig_at_port.clear();
- for (auto &cell_it : module->cells_)
- for (auto &conn_it : cell_it.second->connections()) {
- if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
+ for (auto cell : module->cells())
+ for (auto &conn_it : cell->connections()) {
+ if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
}
- if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) {
+ if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
- sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
+ sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
}
}
- for (auto &wire_it : module->wires_)
- if (wire_it.second->port_id != 0)
- sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
+ for (auto wire : module->wires())
+ if (wire->port_id != 0)
+ sig_at_port.add(assign_map(wire));
- for (auto &wire_it : module->wires_)
- if (design->selected(module, wire_it.second))
- detect_fsm(wire_it.second);
+ for (auto wire : module->selected_wires())
+ detect_fsm(wire);
}
assign_map.clear();
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
- if (full_mode || cell->type == "$_MUX_")
+ if (full_mode || cell->type == ID($_MUX_))
return true;
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
if (cell->getPort(ID::A).size() < 2)
return true;
new_signals.sort_and_unify();
new_signals.remove_const();
- new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
- new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
+ new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
+ new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
if (new_signals.size() > 3)
return false;
{
std::vector<RTLIL::Cell*> cell_list;
- for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
+ for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
cell_list.push_back(c);
- for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
+ for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
cell_list.push_back(c);
current_set.clear();
if (already_optimized)
return;
- int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
if (trans_num > limit_transitions)
{
log(" grown transition table to %d entries -> optimize.\n", trans_num);
FsmData::optimize_fsm(fsm_cell, module);
already_optimized = true;
- trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
log(" transition table size after optimizaton: %d\n", trans_num);
limit_transitions = 16 * trans_num;
}
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size();
- RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
new_ctrl_in.append(input_sig);
- fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
+ fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size();
- RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
new_ctrl_out.append(output_sig);
- fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
+ fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
already_optimized = false;
- limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int();
+ limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
for (create_current_set(); current_set.size() > 0; create_current_set()) {
for (auto c : current_set)
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
- continue;
+ for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_cells.push_back(cell_it.second);
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_cells.push_back(cell);
for (auto c : fsm_cells) {
- FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
+ FsmExpand fsm_expand(c, design, mod, full_mode);
fsm_expand.execute();
}
}
std::string kiss_name;
size_t i;
- attr_it = cell->attributes.find("\\fsm_export");
+ attr_it = cell->attributes.find(ID::fsm_export);
if (!filename.empty()) {
kiss_name.assign(filename);
} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
- attr_it = cell_it.second->attributes.find("\\fsm_export");
- if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
- write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc);
- filename.clear();
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm)) {
+ attr_it = cell->attributes.find(ID::fsm_export);
+ if (!flag_noauto || (attr_it != cell->attributes.end())) {
+ write_kiss2(mod, cell, filename, flag_origenc);
+ filename.clear();
}
+ }
}
} FsmExportPass;
for (auto &cellport : cellport_list)
{
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) {
+ if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false;
}
sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first);
- if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
+ if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
- RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
- RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
- clk = cell->getPort("\\CLK");
- clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
- if (cell->type == "$adff") {
- arst = cell->getPort("\\ARST");
- arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
- reset_state = cell->parameters["\\ARST_VALUE"];
+ RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
+ RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
+ clk = cell->getPort(ID::CLK);
+ clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
+ if (cell->type == ID($adff)) {
+ arst = cell->getPort(ID::ARST);
+ arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
+ reset_state = cell->parameters[ID::ARST_VALUE];
}
sig_q.replace(dff_out, sig_d, &dff_in);
break;
// create fsm cell
- RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
- fsm_cell->setPort("\\CLK", clk);
- fsm_cell->setPort("\\ARST", arst);
- fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0;
- fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0;
- fsm_cell->setPort("\\CTRL_IN", ctrl_in);
- fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
- fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
+ RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm));
+ fsm_cell->setPort(ID::CLK, clk);
+ fsm_cell->setPort(ID::ARST, arst);
+ fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
+ fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
+ fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
+ fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
+ fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell);
CellTypes ct(design);
- for (auto &mod_it : design->modules_)
+ for (auto mod : design->selected_modules())
{
- if (!design->selected(mod_it.second))
- continue;
-
- module = mod_it.second;
+ module = mod;
assign_map.set(module);
sig2driver.clear();
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
- if (cell->type == "$pmux") {
+ if (cell->type == ID($pmux)) {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
}
std::vector<RTLIL::Wire*> wire_list;
- for (auto &wire_it : module->wires_)
- if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none")
- if (design->selected(module, wire_it.second))
- wire_list.push_back(wire_it.second);
+ for (auto wire : module->selected_wires())
+ if (wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes[ID::fsm_encoding].decode_string() != "none")
+ wire_list.push_back(wire);
for (auto wire : wire_list)
extract_fsm(wire);
}
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
- log("\n");
- log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());
- FsmData fsm_data;
- fsm_data.copy_from_cell(cell_it.second);
- fsm_data.log_info(cell_it.second);
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm)) {
+ log("\n");
+ log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
+ FsmData fsm_data;
+ fsm_data.copy_from_cell(cell);
+ fsm_data.log_info(cell);
+ }
}
} FsmInfoPass;
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(eq_wire));
- RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(eq_sig_b.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
std::set<int> complete_in_state_cache = it.second;
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(or_wire));
- RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
- or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
- or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
+ or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
}
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
cases_vector.append(RTLIL::SigSpec(and_wire));
- RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
+ RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
- and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
- and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
- and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
+ and_cell->parameters[ID::B_WIDTH] = RTLIL::Const(1);
+ and_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
break;
}
case 1:
}
if (cases_vector.size() > 1) {
- RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output);
- or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
- or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
+ or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} else if (cases_vector.size() == 1) {
module->connect(RTLIL::SigSig(output, cases_vector));
} else {
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
- RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
- RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
+ RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
// create state register
- RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
+ RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
- if (fsm_cell->getPort("\\ARST").is_fully_const()) {
- state_dff->type = "$dff";
+ if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
+ state_dff->type = ID($dff);
} else {
- state_dff->type = "$adff";
- state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
- state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
- for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
+ state_dff->type = ID($adff);
+ state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
+ state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
+ for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
- state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
+ state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
}
- state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
- state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
- state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
- state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
- state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
+ state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
+ state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
+ state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
+ state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
+ state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
// decode state register
{
encoding_is_onehot = false;
- RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(sig_b.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
}
}
if (encoding_is_onehot)
- state_wire->set_bool_attribute("\\onehot");
+ state_wire->set_bool_attribute(ID::onehot);
// generate next_state signal
}
}
- RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
+ RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
- mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
+ mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
+ mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
}
}
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_) {
- if (!design->selected(mod_it.second))
- continue;
+ for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_cells.push_back(cell_it.second);
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_cells.push_back(cell);
for (auto cell : fsm_cells)
- map_fsm(cell, mod_it.second);
+ map_fsm(cell, mod);
}
}
} FsmMapPass;
{
RTLIL::SigBit bit = sig.as_bit();
- if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
+ if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0)
return false;
- char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
+ char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str());
for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
if (tok[0] && bit.offset == atoi(tok)) {
free(str);
void opt_const_and_unused_inputs()
{
- RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table;
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
if (!ctrl_in_used[i]) {
- log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
+ log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
for (auto &tr : new_transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_in);
tmp.remove(i, 1);
tr.ctrl_in = tmp.as_const();
}
- RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
new_ctrl_in.remove(i, 1);
- cell->setPort("\\CTRL_IN", new_ctrl_in);
+ cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_inputs--;
}
}
void opt_unused_outputs()
{
for (int i = 0; i < fsm_data.num_outputs; i++) {
- RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
+ RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
if (signal_is_unused(sig)) {
log(" Removing unused output signal %s.\n", log_signal(sig));
- RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
new_ctrl_out.remove(i, 1);
- cell->setPort("\\CTRL_OUT", new_ctrl_out);
+ cell->setPort(ID::CTRL_OUT, new_ctrl_out);
for (auto &tr : fsm_data.transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_out);
tmp.remove(i, 1);
void opt_alias_inputs()
{
- RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
+ RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
for (int i = 0; i < ctrl_in.size(); i++)
for (int j = i+1; j < ctrl_in.size(); j++)
void opt_feedback_inputs()
{
- RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
- RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
+ RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
+ RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT];
for (int j = 0; j < ctrl_out.size(); j++)
for (int i = 0; i < ctrl_in.size(); i++)
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules_) {
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- FsmData::optimize_fsm(cell_it.second, mod_it.second);
- }
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ FsmData::optimize_fsm(cell, mod);
}
} FsmOptPass;
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
{
- std::string name = cell->parameters["\\NAME"].decode_string();
+ std::string name = cell->parameters[ID::NAME].decode_string();
fprintf(f, "set_fsm_state_vector {");
for (int i = fsm_data.state_bits-1; i >= 0; i--)
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
if (encfile)
- fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str());
+ fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
for (int i = 0; i < int(fsm_data.state_table.size()); i++)
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules_)
- if (design->selected(mod_it.second))
- for (auto &cell_it : mod_it.second->cells_)
- if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
- fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, encfile, default_encoding);
+ for (auto mod : design->selected_modules())
+ for (auto cell : mod->selected_cells())
+ if (cell->type == ID($fsm))
+ fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
if (fm_set_fsm_file != NULL)
fclose(fm_set_fsm_file);
void copy_to_cell(RTLIL::Cell *cell)
{
- cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs);
- cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs);
+ cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);
+ cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);
int state_num_log2 = 0;
for (int i = state_table.size(); i > 0; i = i >> 1)
state_num_log2++;
state_num_log2 = max(state_num_log2, 1);
- cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
- cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
- cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2);
- cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state);
- cell->parameters["\\STATE_TABLE"] = RTLIL::Const();
+ cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);
+ cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
+ cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
+ cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
+ cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) {
- std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits;
+ std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
}
- cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size());
- cell->parameters["\\TRANS_TABLE"] = RTLIL::Const();
+ cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
+ cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++)
{
- std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits;
+ std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
void copy_from_cell(RTLIL::Cell *cell)
{
- num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int();
- num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int();
+ num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();
+ num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();
- state_bits = cell->parameters["\\STATE_BITS"].as_int();
- reset_state = cell->parameters["\\STATE_RST"].as_int();
+ state_bits = cell->parameters[ID::STATE_BITS].as_int();
+ reset_state = cell->parameters[ID::STATE_RST].as_int();
- int state_num = cell->parameters["\\STATE_NUM"].as_int();
- int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int();
- int trans_num = cell->parameters["\\TRANS_NUM"].as_int();
+ int state_num = cell->parameters[ID::STATE_NUM].as_int();
+ int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();
+ int trans_num = cell->parameters[ID::TRANS_NUM].as_int();
if (reset_state < 0 || reset_state >= state_num)
reset_state = -1;
- RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"];
- RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"];
+ RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
+ RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
{
log("-------------------------------------\n");
log("\n");
- log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
+ log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
log("\n");
log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs);
log("\n");
log(" Input signals:\n");
- RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
+ RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
- RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
+ RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
- mod->attributes["\\blackbox"] = RTLIL::Const(1);
+ mod->attributes[ID::blackbox] = RTLIL::Const(1);
design->add(mod);
for (auto &decl : ports) {
// If any of the ports are actually interface ports, we will always need to
// reprocess the module:
- if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+ if(!module->get_bool_attribute(ID::interfaces_replaced_in_module)) {
for (auto wire : module->wires()) {
if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface))
has_interface_ports = true;
// some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) {
if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list
- //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
+ //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type);
//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
//}
// Find if the sub-module has set a modport for the current interface connection:
- const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport");
+ const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport);
std::string interface_modport = "";
for (auto &d : interface_modport_pool) {
interface_modport = "\\" + d;
interface_name_str = "\\" + interface_name_str;
RTLIL::IdString interface_name = interface_name_str;
bool not_found_interface = false;
- if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
+ if(module->get_bool_attribute(ID::interfaces_replaced_in_module)) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
// Check if the interface instance is present in module:
// Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'.
// Check for both of them here
// which will delay the expansion of this cell:
if (not_found_interface) {
// If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error:
- if(!(module->get_bool_attribute("\\cells_not_processed"))) {
+ if(!(module->get_bool_attribute(ID::cells_not_processed))) {
log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module));
}
else {
// If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type
// for the cell:
- if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) {
+ if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute(ID::module_not_derived)))) {
// If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:",
// so that the signals of the interface are added to the parent module.
if (mod->get_bool_attribute(ID::is_interface)) {
// We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter
// an interface instance:
- if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute("\\module_not_derived")) {
+ if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute(ID::module_not_derived)) {
cell->set_bool_attribute(ID::is_interface);
RTLIL::Module *derived_module = design->module(cell->type);
interfaces_in_module[cell->name] = derived_module;
did_something = true;
}
// We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
- cell->attributes.erase("\\module_not_derived");
+ cell->attributes.erase(ID::module_not_derived);
}
// Clear the attribute 'cells_not_processed' such that it can be known that we
// have been through all cells at least once, and that we can know whether
// to flag an error because of interface instances not found:
- module->attributes.erase("\\cells_not_processed");
+ module->attributes.erase(ID::cells_not_processed);
// If any interface instances or interface ports were found in the module, we need to rederive it completely:
- if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+ if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute(ID::interfaces_replaced_in_module)) {
module->reprocess_module(design, interfaces_in_module);
return did_something;
}
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type);
- if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover"))
+ if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return cache[mod] = true;
}
return cache[mod];
// Delete modules marked as 'to_delete':
std::vector<RTLIL::Module *> modules_to_delete;
for(auto mod : design->modules()) {
- if (mod->get_bool_attribute("\\to_delete")) {
+ if (mod->get_bool_attribute(ID::to_delete)) {
modules_to_delete.push_back(mod);
}
}
for (auto mod : design->modules())
if (set_keep_assert(cache, mod)) {
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod));
- mod->set_bool_attribute("\\keep");
+ mod->set_bool_attribute(ID::keep);
}
}
{
for (auto cell : module->cells())
{
- if (!cell->get_bool_attribute(ID(wildcard_port_conns)))
+ if (!cell->get_bool_attribute(ID::wildcard_port_conns))
continue;
Module *m = design->module(cell->type);
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
- if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
+ if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true);
if (new_m_name.empty())
continue;
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
cell->setPort(wire->name, parent_wire);
}
- cell->attributes.erase(ID(wildcard_port_conns));
+ cell->attributes.erase(ID::wildcard_port_conns);
}
}
if (m == nullptr)
continue;
- if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
+ if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true);
if (new_m_name.empty())
continue;
new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes;
if (!flags.is_int_driven.is_fully_zero()) {
- new_wire->attributes.erase(ID(init));
+ new_wire->attributes.erase(ID::init);
auto sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++) {
if (flags.is_int_driven[i] == State::S0)
continue;
if (!sig[i].wire)
continue;
- auto it = sig[i].wire->attributes.find(ID(init));
+ auto it = sig[i].wire->attributes.find(ID::init);
if (it != sig[i].wire->attributes.end()) {
- auto jt = new_wire->attributes.insert(std::make_pair(ID(init), Const(State::Sx, GetSize(sig)))).first;
+ auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first;
jt->second[i] = it->second[sig[i].offset];
it->second[sig[i].offset] = State::Sx;
}
if (opt_name.empty())
{
for (auto &it : module->wires_)
- it.second->attributes.erase("\\submod");
+ it.second->attributes.erase(ID::submod);
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
- if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
- cell->attributes.erase("\\submod");
+ if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) {
+ cell->attributes.erase(ID::submod);
continue;
}
- std::string submod_str = cell->attributes["\\submod"].decode_string();
- cell->attributes.erase("\\submod");
+ std::string submod_str = cell->attributes[ID::submod].decode_string();
+ cell->attributes.erase(ID::submod);
if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str;
for (auto module : design->selected_modules())
{
- if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute(ID::top))
+ if (!module->get_bool_attribute(ID::unique) && !module->get_bool_attribute(ID::top))
continue;
for (auto cell : module->selected_cells())
if (tmod->get_blackbox_attribute())
continue;
- if (tmod->get_bool_attribute("\\unique") && newname == tmod->name)
+ if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name)
continue;
log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));
auto smod = tmod->clone();
smod->name = newname;
cell->type = newname;
- smod->set_bool_attribute("\\unique");
- if (smod->attributes.count("\\hdlname") == 0)
- smod->attributes["\\hdlname"] = string(log_id(tmod->name));
+ smod->set_bool_attribute(ID::unique);
+ if (smod->attributes.count(ID::hdlname) == 0)
+ smod->attributes[ID::hdlname] = string(log_id(tmod->name));
design->add(smod);
did_something = true;
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant);
if (abits != other.abits)
- variant_params["\\CFG_ABITS"] = abits;
+ variant_params[ID::CFG_ABITS] = abits;
if (dbits != other.dbits)
- variant_params["\\CFG_DBITS"] = dbits;
+ variant_params[ID::CFG_DBITS] = dbits;
if (init != other.init)
- variant_params["\\CFG_INIT"] = init;
+ variant_params[ID::CFG_INIT] = init;
for (int i = 0; i < groups; i++)
{
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
// bram.dump_config();
- int mem_size = cell->getParam("\\SIZE").as_int();
- int mem_abits = cell->getParam("\\ABITS").as_int();
- int mem_width = cell->getParam("\\WIDTH").as_int();
- // int mem_offset = cell->getParam("\\OFFSET").as_int();
+ int mem_size = cell->getParam(ID::SIZE).as_int();
+ int mem_abits = cell->getParam(ID::ABITS).as_int();
+ int mem_width = cell->getParam(ID::WIDTH).as_int();
+ // int mem_offset = cell->getParam(ID::OFFSET).as_int();
- bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+ bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
vector<Const> initdata;
if (cell_init) {
- Const initparam = cell->getParam("\\INIT");
+ Const initparam = cell->getParam(ID::INIT);
initdata.reserve(mem_size);
for (int i=0; i < mem_size; i++)
initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx));
}
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
- auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE"));
- auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY"));
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
+ auto wr_clken = SigSpec(cell->getParam(ID::WR_CLK_ENABLE));
+ auto wr_clkpol = SigSpec(cell->getParam(ID::WR_CLK_POLARITY));
wr_clken.extend_u0(wr_ports);
wr_clkpol.extend_u0(wr_ports);
- SigSpec wr_en = cell->getPort("\\WR_EN");
- SigSpec wr_clk = cell->getPort("\\WR_CLK");
- SigSpec wr_data = cell->getPort("\\WR_DATA");
- SigSpec wr_addr = cell->getPort("\\WR_ADDR");
+ SigSpec wr_en = cell->getPort(ID::WR_EN);
+ SigSpec wr_clk = cell->getPort(ID::WR_CLK);
+ SigSpec wr_data = cell->getPort(ID::WR_DATA);
+ SigSpec wr_addr = cell->getPort(ID::WR_ADDR);
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- auto rd_clken = SigSpec(cell->getParam("\\RD_CLK_ENABLE"));
- auto rd_clkpol = SigSpec(cell->getParam("\\RD_CLK_POLARITY"));
- auto rd_transp = SigSpec(cell->getParam("\\RD_TRANSPARENT"));
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ auto rd_clken = SigSpec(cell->getParam(ID::RD_CLK_ENABLE));
+ auto rd_clkpol = SigSpec(cell->getParam(ID::RD_CLK_POLARITY));
+ auto rd_transp = SigSpec(cell->getParam(ID::RD_TRANSPARENT));
rd_clken.extend_u0(rd_ports);
rd_clkpol.extend_u0(rd_ports);
rd_transp.extend_u0(rd_ports);
- SigSpec rd_en = cell->getPort("\\RD_EN");
- SigSpec rd_clk = cell->getPort("\\RD_CLK");
- SigSpec rd_data = cell->getPort("\\RD_DATA");
- SigSpec rd_addr = cell->getPort("\\RD_ADDR");
+ SigSpec rd_en = cell->getPort(ID::RD_EN);
+ SigSpec rd_clk = cell->getPort(ID::RD_CLK);
+ SigSpec rd_data = cell->getPort(ID::RD_DATA);
+ SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
{
else
initparam[i*bram.dbits+j] = padding;
}
- c->setParam("\\INIT", initparam);
+ c->setParam(ID::INIT, initparam);
}
for (auto &pi : portinfos)
{
log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
- bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef();
+ bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
dict<string, int> match_properties;
- match_properties["words"] = cell->getParam("\\SIZE").as_int();
- match_properties["abits"] = cell->getParam("\\ABITS").as_int();
- match_properties["dbits"] = cell->getParam("\\WIDTH").as_int();
- match_properties["wports"] = cell->getParam("\\WR_PORTS").as_int();
- match_properties["rports"] = cell->getParam("\\RD_PORTS").as_int();
+ match_properties["words"] = cell->getParam(ID::SIZE).as_int();
+ match_properties["abits"] = cell->getParam(ID::ABITS).as_int();
+ match_properties["dbits"] = cell->getParam(ID::WIDTH).as_int();
+ match_properties["wports"] = cell->getParam(ID::WR_PORTS).as_int();
+ match_properties["rports"] = cell->getParam(ID::RD_PORTS).as_int();
match_properties["bits"] = match_properties["words"] * match_properties["dbits"];
match_properties["ports"] = match_properties["wports"] + match_properties["rports"];
for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells())
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
handle_cell(cell, rules);
}
} MemoryBramPass;
bool memcells_cmp(Cell *a, Cell *b)
{
- if (a->type == "$memrd" && b->type == "$memrd")
+ if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name;
- if (a->type == "$memrd" || b->type == "$memrd")
- return (a->type == "$memrd") < (b->type == "$memrd");
- return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
+ if (a->type == ID($memrd) || b->type == ID($memrd))
+ return (a->type == ID($memrd)) < (b->type == ID($memrd));
+ return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
}
Cell *handle_memory(Module *module, RTLIL::Memory *memory)
for (auto &cell_it : module->cells_) {
Cell *cell = cell_it.second;
- if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
+ if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) {
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
for (int i = 0; i < GetSize(addr); i++)
if (addr[i] != State::S0)
addr_bits = std::max(addr_bits, i+1);
{
log(" %s (%s)\n", log_id(cell), log_id(cell->type));
- if (cell->type == "$meminit")
+ if (cell->type == ID($meminit))
{
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
continue;
}
- if (cell->type == "$memwr")
+ if (cell->type == ID($memwr))
{
- SigSpec clk = sigmap(cell->getPort("\\CLK"));
- SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
- SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
- SigSpec en = sigmap(cell->getPort("\\EN"));
+ SigSpec clk = sigmap(cell->getPort(ID::CLK));
+ SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
+ SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
+ SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero())
{
continue;
}
- if (cell->type == "$memrd")
+ if (cell->type == ID($memrd))
{
- SigSpec clk = sigmap(cell->getPort("\\CLK"));
- SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
- SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
- SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]);
- SigSpec addr = sigmap(cell->getPort("\\ADDR"));
- SigSpec data = sigmap(cell->getPort("\\DATA"));
- SigSpec en = sigmap(cell->getPort("\\EN"));
+ SigSpec clk = sigmap(cell->getPort(ID::CLK));
+ SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
+ SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
+ SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]);
+ SigSpec addr = sigmap(cell->getPort(ID::ADDR));
+ SigSpec data = sigmap(cell->getPort(ID::DATA));
+ SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero())
{
std::stringstream sstr;
sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
- Cell *mem = module->addCell(sstr.str(), "$mem");
- mem->parameters["\\MEMID"] = Const(memory->name.str());
- mem->parameters["\\WIDTH"] = Const(memory->width);
- mem->parameters["\\OFFSET"] = Const(memory->start_offset);
- mem->parameters["\\SIZE"] = Const(memory->size);
- mem->parameters["\\ABITS"] = Const(addr_bits);
- mem->parameters["\\INIT"] = init_data;
+ Cell *mem = module->addCell(sstr.str(), ID($mem));
+ mem->parameters[ID::MEMID] = Const(memory->name.str());
+ mem->parameters[ID::WIDTH] = Const(memory->width);
+ mem->parameters[ID::OFFSET] = Const(memory->start_offset);
+ mem->parameters[ID::SIZE] = Const(memory->size);
+ mem->parameters[ID::ABITS] = Const(addr_bits);
+ mem->parameters[ID::INIT] = init_data;
log_assert(sig_wr_clk.size() == wr_ports);
log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
log_assert(sig_wr_data.size() == wr_ports * memory->width);
log_assert(sig_wr_en.size() == wr_ports * memory->width);
- mem->parameters["\\WR_PORTS"] = Const(wr_ports);
- mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
- mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
+ mem->parameters[ID::WR_PORTS] = Const(wr_ports);
+ mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
+ mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
- mem->setPort("\\WR_CLK", sig_wr_clk);
- mem->setPort("\\WR_ADDR", sig_wr_addr);
- mem->setPort("\\WR_DATA", sig_wr_data);
- mem->setPort("\\WR_EN", sig_wr_en);
+ mem->setPort(ID::WR_CLK, sig_wr_clk);
+ mem->setPort(ID::WR_ADDR, sig_wr_addr);
+ mem->setPort(ID::WR_DATA, sig_wr_data);
+ mem->setPort(ID::WR_EN, sig_wr_en);
log_assert(sig_rd_clk.size() == rd_ports);
log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
log_assert(sig_rd_data.size() == rd_ports * memory->width);
- mem->parameters["\\RD_PORTS"] = Const(rd_ports);
- mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
- mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
- mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
+ mem->parameters[ID::RD_PORTS] = Const(rd_ports);
+ mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
+ mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
+ mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
- mem->setPort("\\RD_CLK", sig_rd_clk);
- mem->setPort("\\RD_ADDR", sig_rd_addr);
- mem->setPort("\\RD_DATA", sig_rd_data);
- mem->setPort("\\RD_EN", sig_rd_en);
+ mem->setPort(ID::RD_CLK, sig_rd_clk);
+ mem->setPort(ID::RD_ADDR, sig_rd_addr);
+ mem->setPort(ID::RD_DATA, sig_rd_data);
+ mem->setPort(ID::RD_EN, sig_rd_en);
// Copy attributes from RTLIL memory to $mem
for (auto attr : memory->attributes)
MemoryDffWorker(Module *module) : module(module), sigmap(module)
{
for (auto wire : module->wires()) {
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec sig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sig[i]);
if (after && forward_merged_dffs.count(cell))
continue;
- SigSpec this_clk = cell->getPort("\\CLK");
- bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
+ SigSpec this_clk = cell->getPort(ID::CLK);
+ bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (invbits.count(this_clk)) {
this_clk = invbits.at(this_clk);
continue;
}
- RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
+ RTLIL::SigSpec q_norm = cell->getPort(after ? ID::D : ID::Q);
sigmap.apply(q_norm);
- RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
+ RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? ID::Q : ID::D));
if (d.size() != 1)
continue;
bool clk_polarity = 0;
candidate_dffs.clear();
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
log("no (compatible) $dff for address input found.\n");
return;
}
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
log("no (compatible) $dff for data input found.\n");
return;
}
- RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
log("no (compatible) $dff for enable input found.\n");
return;
for (auto cell : candidate_dffs)
forward_merged_dffs.insert(cell);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\ADDR", sig_addr);
- cell->setPort("\\DATA", sig_data);
- cell->setPort("\\EN", sig_en);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::ADDR, sig_addr);
+ cell->setPort(ID::DATA, sig_data);
+ cell->setPort(ID::EN, sig_en);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
log("merged $dff to cell.\n");
return;
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto cell : module->cells())
- if (cell->type == "$dff") {
- RTLIL::SigSpec new_q = cell->getPort("\\Q");
+ if (cell->type == ID($dff)) {
+ RTLIL::SigSpec new_q = cell->getPort(ID::Q);
new_q.replace(sig, new_sig);
- cell->setPort("\\Q", new_q);
+ cell->setPort(ID::Q, new_q);
}
}
bool clk_polarity = 0;
RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+ RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
for (auto bit : sigmap(sig_data))
if (sigbit_users_count[bit] > 1)
std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
{
disconnect_dff(sig_data);
- cell->setPort("\\CLK", clk_data);
- cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
- cell->setPort("\\DATA", sig_data);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, clk_data);
+ cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
+ cell->setPort(ID::DATA, sig_data);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff with rd enable to cell.\n");
return;
}
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
{
disconnect_dff(sig_data);
- cell->setPort("\\CLK", clk_data);
- cell->setPort("\\EN", State::S1);
- cell->setPort("\\DATA", sig_data);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+ cell->setPort(ID::CLK, clk_data);
+ cell->setPort(ID::EN, State::S1);
+ cell->setPort(ID::DATA, sig_data);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff to cell.\n");
return;
}
skip_ff_after_read_merging:;
RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
- RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+ RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
{
- cell->setPort("\\CLK", clk_addr);
- cell->setPort("\\EN", State::S1);
- cell->setPort("\\ADDR", sig_addr);
- cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
- cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
+ cell->setPort(ID::CLK, clk_addr);
+ cell->setPort(ID::EN, State::S1);
+ cell->setPort(ID::ADDR, sig_addr);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+ cell->parameters[ID::TRANSPARENT] = RTLIL::Const(1);
log("merged address $dff to cell.\n");
return;
}
}
for (auto cell : module->cells()) {
- if (cell->type == "$dff")
+ if (cell->type == ID($dff))
dff_cells.push_back(cell);
- if (cell->type == "$mux") {
+ if (cell->type == ID($mux)) {
mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
}
- if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort(ID::A)) == 1)) {
+ if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
- if (cell->type == "$not")
- sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
- if (cell->type == "$logic_not")
+ if (cell->type == ID($not))
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+ if (cell->type == ID($logic_not))
sig_y.extend_u0(1);
for (int i = 0; i < GetSize(sig_y); i++)
invbits[sig_y[i]] = sig_a[i];
}
for (auto cell : module->selected_cells())
- if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_wr_cell(cell);
if (!flag_wr_only)
for (auto cell : module->selected_cells())
- if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+ if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_rd_cell(cell);
}
};
std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map;
- int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
- int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
+ int wr_ports = cell->parameters[ID::WR_PORTS].as_int();
+ int rd_ports = cell->parameters[ID::RD_PORTS].as_int();
- int mem_size = cell->parameters["\\SIZE"].as_int();
- int mem_width = cell->parameters["\\WIDTH"].as_int();
- int mem_offset = cell->parameters["\\OFFSET"].as_int();
- int mem_abits = cell->parameters["\\ABITS"].as_int();
+ int mem_size = cell->parameters[ID::SIZE].as_int();
+ int mem_width = cell->parameters[ID::WIDTH].as_int();
+ int mem_offset = cell->parameters[ID::OFFSET].as_int();
+ int mem_abits = cell->parameters[ID::ABITS].as_int();
- SigSpec init_data = cell->getParam("\\INIT");
+ SigSpec init_data = cell->getParam(ID::INIT);
init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell
}
// all write ports must share the same clock
- RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
- RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
- RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
+ RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
+ RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
+ RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
clocks_pol.bits.resize(wr_ports);
clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) {
- RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i);
continue;
}
if (clocks_en.bits[i] != RTLIL::State::S1) {
- RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width);
if (wr_addr.is_fully_const()) {
// FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en
}
else
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
- c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff));
+ c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
if (clocks_pol.bits.size() > 0) {
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
- c->setPort("\\CLK", clocks.extract(0, 1));
+ c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]);
+ c->setPort(ID::CLK, clocks.extract(0, 1));
} else {
- c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
- c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
+ c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
+ c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
}
RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
data_reg_in.push_back(RTLIL::SigSpec(w_in));
- c->setPort("\\D", data_reg_in.back());
+ c->setPort(ID::D, data_reg_in.back());
- std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
+ std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i);
if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q");
SigSpec w_init = init_data.extract(i*mem_width, mem_width);
if (!w_init.is_fully_undef())
- w_out->attributes["\\init"] = w_init.as_const();
+ w_out->attributes[ID::init] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out));
- c->setPort("\\Q", data_reg_out.back());
+ c->setPort(ID::Q, data_reg_out.back());
}
}
int count_dff = 0, count_mux = 0, count_wrmux = 0;
- for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
+ for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++)
{
- RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits);
if (mem_offset)
rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
std::vector<RTLIL::SigSpec> rd_signals;
- rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
+ rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width));
- if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
+ if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1)
{
RTLIL::Cell *dff_cell = nullptr;
- if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
+ if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1)
{
- dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
- dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- dff_cell->setPort("\\D", rd_addr);
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
+ dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits);
+ dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
+ dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
+ dff_cell->setPort(ID::D, rd_addr);
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
- dff_cell->setPort("\\Q", RTLIL::SigSpec(w));
+ dff_cell->setPort(ID::Q, RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w);
}
else
{
- dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
- dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
- dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
- dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
- dff_cell->setPort("\\Q", rd_signals.back());
+ dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
+ dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
+ dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
+ dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
+ dff_cell->setPort(ID::Q, rd_signals.back());
count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w));
- dff_cell->setPort("\\D", rd_signals.back());
+ dff_cell->setPort(ID::D, rd_signals.back());
}
- SigBit en_bit = cell->getPort("\\RD_EN").extract(i);
+ SigBit en_bit = cell->getPort(ID::RD_EN).extract(i);
if (en_bit != State::S1) {
SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
- dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit);
- dff_cell->setPort("\\D", new_d);
+ dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit);
+ dff_cell->setPort(ID::D, new_d);
}
}
for (size_t k = 0; k < rd_signals.size(); k++)
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
- c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux));
+ c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
count_mux++;
RTLIL::SigSpec sig = data_reg_out[i];
- for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
+ for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++)
{
- RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
- RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
- RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width);
if (mem_offset)
wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
if (wr_bit != State::S1)
{
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
- c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
- c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
- c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and));
+ c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
+ c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
+ c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
+ c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
c->setPort(ID::A, w);
c->setPort(ID::B, wr_bit);
c->setPort(ID::Y, RTLIL::SigSpec(w));
}
- RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
- c->parameters["\\WIDTH"] = wr_width;
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux));
+ c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
c->setPort(ID::S, RTLIL::SigSpec(w));
{
std::vector<RTLIL::Cell*> cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$mem" && design->selected(module, cell))
+ if (cell->type == ID($mem))
cells.push_back(cell);
for (auto cell : cells)
handle_cell(cell);
vector<Cell*> mem_port_cells;
for (auto cell : module->selected_cells())
- if (cell->type.in("$memrd", "$memwr"))
+ if (cell->type.in(ID($memrd), ID($memwr)))
mem_port_cells.push_back(cell);
for (auto cell : mem_port_cells)
{
- IdString memid = cell->getParam("\\MEMID").decode_string();
+ IdString memid = cell->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
int lowest_addr = mem->start_offset;
int highest_addr = mem->start_offset + mem->size - 1;
- SigSpec addr = cell->getPort("\\ADDR");
+ SigSpec addr = cell->getPort(ID::ADDR);
addr.extend_u0(32);
SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1}));
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr));
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr));
- if (cell->type == "$memrd")
+ if (cell->type == ID($memrd))
{
- if (cell->getParam("\\CLK_ENABLE").as_bool())
+ if (cell->getParam(ID::CLK_ENABLE).as_bool())
log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n",
log_id(module), log_id(cell), log_id(cell->type));
- SigSpec rdata = cell->getPort("\\DATA");
+ SigSpec rdata = cell->getPort(ID::DATA);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata);
- cell->setPort("\\DATA", raw_rdata);
+ cell->setPort(ID::DATA, raw_rdata);
}
- if (cell->type == "$memwr")
+ if (cell->type == ID($memwr))
{
- SigSpec en = cell->getPort("\\EN");
+ SigSpec en = cell->getPort(ID::EN);
en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en)));
- cell->setPort("\\EN", en);
+ cell->setPort(ID::EN, en);
}
}
}
for (auto module : design->selected_modules())
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type != "$mem")
+ if (cell->type != ID($mem))
continue;
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- SigSpec rd_addr = cell->getPort("\\RD_ADDR");
- SigSpec rd_data = cell->getPort("\\RD_DATA");
- SigSpec rd_clk = cell->getPort("\\RD_CLK");
- SigSpec rd_en = cell->getPort("\\RD_EN");
- Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE");
- Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY");
+ SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
+ SigSpec rd_data = cell->getPort(ID::RD_DATA);
+ SigSpec rd_clk = cell->getPort(ID::RD_CLK);
+ SigSpec rd_en = cell->getPort(ID::RD_EN);
+ Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
+ Const rd_clk_polarity = cell->getParam(ID::RD_CLK_POLARITY);
for (int i = 0; i < rd_ports; i++)
{
if (clk_enable)
{
- bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1;
- bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1;
+ bool clk_polarity = cell->getParam(ID::RD_CLK_POLARITY)[i] == State::S1;
+ bool transparent = cell->getParam(ID::RD_TRANSPARENT)[i] == State::S1;
- SigSpec clk = cell->getPort("\\RD_CLK")[i] ;
- SigSpec en = cell->getPort("\\RD_EN")[i];
+ SigSpec clk = cell->getPort(ID::RD_CLK)[i] ;
+ SigSpec en = cell->getPort(ID::RD_EN)[i];
Cell *c;
if (transparent)
rd_clk_polarity[i] = State::S1;
}
- cell->setPort("\\RD_ADDR", rd_addr);
- cell->setPort("\\RD_DATA", rd_data);
- cell->setPort("\\RD_CLK", rd_clk);
- cell->setPort("\\RD_EN", rd_en);
- cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable);
- cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity);
+ cell->setPort(ID::RD_ADDR, rd_addr);
+ cell->setPort(ID::RD_DATA, rd_data);
+ cell->setPort(ID::RD_CLK, rd_clk);
+ cell->setPort(ID::RD_EN, rd_en);
+ cell->setParam(ID::RD_CLK_ENABLE, rd_clk_enable);
+ cell->setParam(ID::RD_CLK_POLARITY, rd_clk_polarity);
}
}
} MemoryNordffPass;
bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{
- if (a->type == "$memrd" && b->type == "$memrd")
+ if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name;
- if (a->type == "$memrd" || b->type == "$memrd")
- return (a->type == "$memrd") < (b->type == "$memrd");
- return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
+ if (a->type == ID($memrd) || b->type == ID($memrd))
+ return (a->type == ID($memrd)) < (b->type == ID($memrd));
+ return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
}
struct MemoryShareWorker
{
bool ignore_data_port = false;
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
continue;
}
- if (cell->type.in("$memwr", "$memrd") &&
- cell->parameters.at("\\MEMID").decode_string() == memid)
+ if (cell->type.in(ID($memwr), ID($memrd)) &&
+ cell->parameters.at(ID::MEMID).decode_string() == memid)
ignore_data_port = true;
for (auto conn : cell->connections())
{
- if (ignore_data_port && conn.first == "\\DATA")
+ if (ignore_data_port && conn.first == ID::DATA)
continue;
std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
non_feedback_nets.insert(bits.begin(), bits.end());
for (auto cell : rd_ports)
{
- if (cell->parameters.at("\\CLK_ENABLE").as_bool())
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
- RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR"));
- std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA"));
+ RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR));
+ std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA));
for (int i = 0; i < int(sig_data.size()); i++)
if (non_feedback_nets.count(sig_data[i]))
for (auto cell : wr_ports)
{
- RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR"));
+ RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR));
if (!async_rd_bits.count(sig_addr))
continue;
log(" Analyzing write port %s.\n", log_id(cell));
- std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA");
- std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN");
+ std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN);
int created_conditions = 0;
for (int i = 0; i < int(cell_data.size()); i++)
if (created_conditions) {
log(" Added enable logic for %d different cases.\n", created_conditions);
- cell->setPort("\\EN", cell_en);
+ cell->setPort(ID::EN, cell_en);
}
}
}
for (int i = 0; i < int(wr_ports.size()); i++)
{
RTLIL::Cell *cell = wr_ports.at(i);
- RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR"));
+ RTLIL::SigSpec addr = sigmap_xmux(cell->getPort(ID::ADDR));
- if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
- cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
+ (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
+ cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{
- cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
- cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->getPort("\\CLK"));
+ cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
+ cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ cache_clk = sigmap(cell->getPort(ID::CLK));
last_port_by_addr.clear();
if (cache_clk_enable)
log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--) {
active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
// Force this ports addr input to addr directly (skip don't care muxes)
- cell->setPort("\\ADDR", addr);
+ cell->setPort(ID::ADDR, addr);
// If any of the ports between `last_i' and `i' write to the same address, this
// will have priority over whatever `last_i` wrote. So we need to revisit those
// ports and mask the EN bits accordingly.
- RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN"));
+ RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort(ID::EN));
for (int j = last_i+1; j < i; j++)
{
found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j);
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
- module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr);
- merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN")));
+ module->addEq(NEW_ID, addr, wr_ports[j]->getPort(ID::ADDR), is_same_addr);
+ merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort(ID::EN)));
}
}
// Then we need to merge the (masked) EN and the DATA signals.
- RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA");
+ RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort(ID::DATA);
if (found_overlapping_bits) {
log(" Creating logic for merging DATA and EN ports.\n");
- merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA")));
+ merge_en_data(merged_en, merged_data, sigmap(cell->getPort(ID::EN)), sigmap(cell->getPort(ID::DATA)));
} else {
- RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN"));
- RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA"));
+ RTLIL::SigSpec cell_en = sigmap(cell->getPort(ID::EN));
+ RTLIL::SigSpec cell_data = sigmap(cell->getPort(ID::DATA));
for (int k = 0; k < int(en_bits.size()); k++)
if (!active_bits_on_port[last_i][k]) {
merged_en.replace(k, cell_en.extract(k, 1));
// Connect the new EN and DATA signals and remove the old write port.
- cell->setPort("\\EN", merged_en);
- cell->setPort("\\DATA", merged_data);
+ cell->setPort(ID::EN, merged_en);
+ cell->setPort(ID::DATA, merged_data);
module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL;
log(" Active bits: ");
- std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--)
log("%c", active_bits_on_port[i][k] ? '1' : '0');
std::set<int> considered_port_pairs;
for (int i = 0; i < int(wr_ports.size()); i++) {
- std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
for (auto bit : bits)
if (bit == RTLIL::State::S1)
goto port_is_always_active;
{
RTLIL::Cell *cell = wr_ports.at(i);
- if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable ||
- (cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk ||
- cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity)))
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
+ (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
+ cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{
- cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool();
- cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool();
- cache_clk = sigmap(cell->getPort("\\CLK"));
+ cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
+ cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ cache_clk = sigmap(cell->getPort(ID::CLK));
}
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
considered_port_pairs.insert(i);
for (int i = 0; i < int(wr_ports.size()); i++)
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
{
- RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
std::vector<RTLIL::SigBit> bits = sig;
while (!bits_queue.empty())
{
for (auto bit : bits_queue)
- if (bit.wire && bit.wire->get_bool_attribute("\\onehot"))
+ if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
one_hot_wires.insert(bit.wire);
pool<ModWalker::PortBit> portbits;
log(" Merging port %d into port %d.\n", i-1, i);
port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
- RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR");
- RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA");
- std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN"));
+ RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort(ID::ADDR);
+ RTLIL::SigSpec last_data = wr_ports[i-1]->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort(ID::EN));
- RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR");
- RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA");
- std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN"));
+ RTLIL::SigSpec this_addr = wr_ports[i]->getPort(ID::ADDR);
+ RTLIL::SigSpec this_data = wr_ports[i]->getPort(ID::DATA);
+ std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
else
this_addr.extend_u0(GetSize(last_addr));
- wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
- wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
- wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
+ wr_ports[i]->setParam(ID::ABITS, GetSize(this_addr));
+ wr_ports[i]->setPort(ID::ADDR, module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
+ wr_ports[i]->setPort(ID::DATA, module->Mux(NEW_ID, last_data, this_data, this_en_active));
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
}
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
- wr_ports[i]->setPort("\\EN", en);
+ wr_ports[i]->setPort(ID::EN, en);
module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL;
sigmap_xmux = sigmap;
for (auto cell : module->cells())
{
- if (cell->type == "$memrd")
- memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell);
+ if (cell->type == ID($memrd))
+ memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell);
- if (cell->type == "$memwr")
- memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell);
+ if (cell->type == ID($memwr))
+ memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell);
- if (cell->type == "$mux")
+ if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
}
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < int(sig_y.size()); i++)
}
cone_ct.setup_internals();
- cone_ct.cell_types.erase("$mul");
- cone_ct.cell_types.erase("$mod");
- cone_ct.cell_types.erase("$div");
- cone_ct.cell_types.erase("$pow");
- cone_ct.cell_types.erase("$shl");
- cone_ct.cell_types.erase("$shr");
- cone_ct.cell_types.erase("$sshl");
- cone_ct.cell_types.erase("$sshr");
- cone_ct.cell_types.erase("$shift");
- cone_ct.cell_types.erase("$shiftx");
+ cone_ct.cell_types.erase(ID($mul));
+ cone_ct.cell_types.erase(ID($mod));
+ cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($pow));
+ cone_ct.cell_types.erase(ID($shl));
+ cone_ct.cell_types.erase(ID($shr));
+ cone_ct.cell_types.erase(ID($sshl));
+ cone_ct.cell_types.erase(ID($sshr));
+ cone_ct.cell_types.erase(ID($shift));
+ cone_ct.cell_types.erase(ID($shiftx));
modwalker.setup(module, &cone_ct);
log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str());
- RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
+ RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at(ID::MEMID).decode_string());
while (module->memories.count(mem_name) != 0)
mem_name = mem_name.str() + stringf("_%d", autoidx++);
RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = mem_name;
- mem->width = memory->parameters.at("\\WIDTH").as_int();
- mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
- mem->size = memory->parameters.at("\\SIZE").as_int();
+ mem->width = memory->parameters.at(ID::WIDTH).as_int();
+ mem->start_offset = memory->parameters.at(ID::OFFSET).as_int();
+ mem->size = memory->parameters.at(ID::SIZE).as_int();
module->memories[mem_name] = mem;
- int abits = memory->parameters.at("\\ABITS").as_int();
- int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
- int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
+ int abits = memory->parameters.at(ID::ABITS).as_int();
+ int num_rd_ports = memory->parameters.at(ID::RD_PORTS).as_int();
+ int num_wr_ports = memory->parameters.at(ID::WR_PORTS).as_int();
for (int i = 0; i < num_rd_ports; i++)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
- cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
- cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const();
- cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1));
- cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1));
- cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits));
- cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width));
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memrd));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_ENABLE)).extract(i, 1).as_const();
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_POLARITY)).extract(i, 1).as_const();
+ cell->parameters[ID::TRANSPARENT] = RTLIL::SigSpec(memory->parameters.at(ID::RD_TRANSPARENT)).extract(i, 1).as_const();
+ cell->setPort(ID::CLK, memory->getPort(ID::RD_CLK).extract(i, 1));
+ cell->setPort(ID::EN, memory->getPort(ID::RD_EN).extract(i, 1));
+ cell->setPort(ID::ADDR, memory->getPort(ID::RD_ADDR).extract(i*abits, abits));
+ cell->setPort(ID::DATA, memory->getPort(ID::RD_DATA).extract(i*mem->width, mem->width));
}
for (int i = 0; i < num_wr_ports; i++)
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
- cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
- cell->parameters["\\PRIORITY"] = i;
- cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1));
- cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width));
- cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits));
- cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width));
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memwr));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_ENABLE)).extract(i, 1).as_const();
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_POLARITY)).extract(i, 1).as_const();
+ cell->parameters[ID::PRIORITY] = i;
+ cell->setPort(ID::CLK, memory->getPort(ID::WR_CLK).extract(i, 1));
+ cell->setPort(ID::EN, memory->getPort(ID::WR_EN).extract(i*mem->width, mem->width));
+ cell->setPort(ID::ADDR, memory->getPort(ID::WR_ADDR).extract(i*abits, abits));
+ cell->setPort(ID::DATA, memory->getPort(ID::WR_DATA).extract(i*mem->width, mem->width));
}
- Const initval = memory->parameters.at("\\INIT");
+ Const initval = memory->parameters.at(ID::INIT);
RTLIL::Cell *last_init_cell = nullptr;
SigSpec last_init_data;
int last_init_addr=0;
continue;
found_non_undef_initval:
if (last_init_cell && last_init_addr+1 == i/mem->width) {
- last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1;
+ last_init_cell->parameters[ID::WORDS] = last_init_cell->parameters[ID::WORDS].as_int() + 1;
last_init_data.append(val);
last_init_addr++;
} else {
if (last_init_cell)
- last_init_cell->setPort("\\DATA", last_init_data);
- RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
- cell->parameters["\\MEMID"] = mem_name.str();
- cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
- cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
- cell->parameters["\\WORDS"] = 1;
- cell->parameters["\\PRIORITY"] = i/mem->width;
- cell->setPort("\\ADDR", SigSpec(i/mem->width, abits));
+ last_init_cell->setPort(ID::DATA, last_init_data);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, ID($meminit));
+ cell->parameters[ID::MEMID] = mem_name.str();
+ cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
+ cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
+ cell->parameters[ID::WORDS] = 1;
+ cell->parameters[ID::PRIORITY] = i/mem->width;
+ cell->setPort(ID::ADDR, SigSpec(i/mem->width, abits));
last_init_cell = cell;
last_init_addr = i/mem->width;
last_init_data = val;
}
if (last_init_cell)
- last_init_cell->setPort("\\DATA", last_init_data);
+ last_init_cell->setPort(ID::DATA, last_init_data);
module->remove(memory);
}
{
std::vector<RTLIL::IdString> memcells;
for (auto &cell_it : module->cells_)
- if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
+ if (cell_it.second->type == ID($mem) && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first);
for (auto &it : memcells)
handle_memory(module, module->cells_.at(it));
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
- SigSpec s_sig = sigmap(cell->getPort(ID(S)));
- s_sig.append(sigmap(prev_cell->getPort(ID(S))));
+ SigSpec s_sig = sigmap(cell->getPort(ID::S));
+ s_sig.append(sigmap(prev_cell->getPort(ID::S)));
if (!excl_db.query(s_sig))
goto start_cell;
}
first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B);
- SigSpec s_sig = first_cell->getPort(ID(S));
+ SigSpec s_sig = first_cell->getPort(ID::S);
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
- s_sig.append(cursor_cell->getPort(ID(S)));
+ s_sig.append(cursor_cell->getPort(ID::S));
}
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
- s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID(S))));
+ s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
}
remove_cells.insert(cursor_cell);
}
first_cell->setPort(ID::B, b_sig);
- first_cell->setPort(ID(S), s_sig);
- first_cell->setParam(ID(S_WIDTH), GetSize(s_sig));
+ first_cell->setPort(ID::S, s_sig);
+ first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
cursor += cases;
int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count(ID(src));
- count -= w->attributes.count(ID(unused_bits));
+ count -= w->attributes.count(ID::src);
+ count -= w->attributes.count(ID::unused_bits);
return count;
}
log_assert(GetSize(s1) == GetSize(s2));
Const initval;
- if (wire->attributes.count(ID(init)))
- initval = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init))
+ initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports
}
if (new_conn.first.size() > 0) {
if (initval.is_fully_undef())
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at(ID(init)) = initval;
+ wire->attributes.at(ID::init) = initval;
used_signals.add(new_conn.first);
used_signals.add(new_conn.second);
module->connect(new_conn);
}
}
if (unused_bits.empty() || wire->port_id != 0)
- wire->attributes.erase(ID(unused_bits));
+ wire->attributes.erase(ID::unused_bits);
else
- wire->attributes[ID(unused_bits)] = RTLIL::Const(unused_bits);
+ wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits);
} else {
- wire->attributes.erase(ID(unused_bits));
+ wire->attributes.erase(ID::unused_bits);
}
}
}
dict<SigBit, State> qbits;
for (auto cell : module->cells())
- if (fftypes.cell_known(cell->type) && cell->hasPort(ID(Q)))
+ if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
{
- SigSpec sig = cell->getPort(ID(Q));
+ SigSpec sig = cell->getPort(ID::Q);
for (int i = 0; i < GetSize(sig); i++)
{
SigBit bit = sig[i];
- if (bit.wire == nullptr || bit.wire->attributes.count(ID(init)) == 0)
+ if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
continue;
- Const init = bit.wire->attributes.at(ID(init));
+ Const init = bit.wire->attributes.at(ID::init);
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue;
if (!purge_mode && wire->name[0] == '\\')
continue;
- if (wire->attributes.count(ID(init)) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
- Const init = wire->attributes.at(ID(init));
+ Const init = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{
if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
did_something = true;
next_wire:;
}
std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
- bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed);
}
for (auto wire : module->wires()) {
- if (wire->attributes.count(ID(init))) {
+ if (wire->attributes.count(ID::init)) {
SigSpec sig = sigmap(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[sig[i]] = make_pair(wire, initval[i]);
for (auto wire : revisit_initwires) {
SigSpec sig = sm2(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval[i] = State::Sx;
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
did_something = true;
- } else if (initval != wire->attributes.at(ID(init))) {
+ } else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
- wire->attributes[ID(init)] = initval;
+ wire->attributes[ID::init] = initval;
did_something = true;
}
}
{
IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A;
- bool a_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
+ bool a_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool();
RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID::A));
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort(ID::A, new_a);
- c->parameters[ID(A_WIDTH)] = new_a.size();
- c->parameters[ID(A_SIGNED)] = false;
+ c->parameters[ID::A_WIDTH] = new_a.size();
+ c->parameters[ID::A_SIGNED] = false;
if (b_name == ID::B) {
c->setPort(ID::B, new_b);
- c->parameters[ID(B_WIDTH)] = new_b.size();
- c->parameters[ID(B_SIGNED)] = false;
+ c->parameters[ID::B_WIDTH] = new_b.size();
+ c->parameters[ID::B_SIGNED] = false;
}
c->setPort(ID::Y, new_y);
- c->parameters[ID(Y_WIDTH)] = new_y->width;
+ c->parameters[ID::Y_WIDTH] = new_y->width;
c->check();
module->connect(new_conn);
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
- invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID(S)));
+ invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
if (ct_combinational.cell_known(cell->type))
for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = assign_map(conn.second);
if (clkinv)
{
if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
- handle_polarity_inv(cell, ID(CLK), ID(CLK_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
- handle_polarity_inv(cell, ID(SET), ID(SET_POLARITY), assign_map, invert_map);
- handle_polarity_inv(cell, ID(CLR), ID(CLR_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
+ handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
}
if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
- handle_polarity_inv(cell, ID(EN), ID(EN_POLARITY), assign_map, invert_map);
+ handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID(C), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID(E), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID(C), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID(E), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID(E), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID(S), assign_map, invert_map);
- handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID(R), assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
}
bool detect_const_and = false;
if (cell->type.in(ID($reduce_and), ID($_AND_)))
detect_const_and = true;
- if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
+ if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_and = true;
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
detect_const_or = true;
- if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())
+ if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_or = true;
if (detect_const_and || detect_const_or)
}
}
- if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()))
+ if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
{
SigBit sig_a = assign_map(cell->getPort(ID::A));
SigBit sig_b = assign_map(cell->getPort(ID::B));
SigSpec sig_y;
if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
- int width = cell->getParam(ID(Y_WIDTH)).as_int();
+ int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1));
}
else if (cell->type == ID($_XNOR_))
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a);
- cell->parameters.at(ID(A_WIDTH)) = GetSize(new_sig_a);
+ cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true;
}
}
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b);
- cell->parameters.at(ID(B_WIDTH)) = GetSize(new_sig_b);
+ cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true;
}
}
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
- cell->parameters.at(ID(A_WIDTH)) = 1;
+ cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
}
}
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a);
- cell->parameters.at(ID(A_WIDTH)) = 1;
+ cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true;
}
}
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b);
- cell->parameters.at(ID(B_WIDTH)) = 1;
+ cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true;
}
}
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
- RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
- RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
- RTLIL::SigSpec sig_x = cell->getPort(ID(X));
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
+ RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
+ RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
cover("opt.opt_expr.fine.$alu");
cell->setPort(ID::A, sig_a.extract_end(i));
cell->setPort(ID::B, sig_b.extract_end(i));
- cell->setPort(ID(X), sig_x.extract_end(i));
+ cell->setPort(ID::X, sig_x.extract_end(i));
cell->setPort(ID::Y, sig_y.extract_end(i));
- cell->setPort(ID(CO), sig_co.extract_end(i));
+ cell->setPort(ID::CO, sig_co.extract_end(i));
cell->fixup_parameters();
did_something = true;
}
cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a);
- cell->setParam(ID(A_WIDTH), width);
+ cell->setParam(ID::A_WIDTH, width);
did_something = true;
goto next_cell;
}
goto next_cell;
}
- if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID(S)))) != 0) {
+ if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp);
- cell->setPort(ID(S), invert_map.at(assign_map(cell->getPort(ID(S)))));
+ cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S))));
did_something = true;
goto next_cell;
}
if (cell->type == ID($_MUX_)) {
RTLIL::SigSpec input;
- input.append(cell->getPort(ID(S)));
+ input.append(cell->getPort(ID::S));
input.append(cell->getPort(ID::B));
input.append(cell->getPort(ID::A));
assign_map.apply(input);
cell->type = ID($_NOT_);
cell->setPort(ID::A, input.extract(0, 1));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
goto next_cell;
}
if (input.match("11 ")) ACTION_DO_Y(1);
}
if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
- RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID(E) : ID(EN));
+ RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID::E : ID::EN);
RTLIL::SigSpec a = cell->getPort(ID::A);
assign_map.apply(input);
assign_map.apply(a);
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
- if (cell->parameters[ID(A_WIDTH)].as_int() != cell->parameters[ID(B_WIDTH)].as_int()) {
- int width = max(cell->parameters[ID(A_WIDTH)].as_int(), cell->parameters[ID(B_WIDTH)].as_int());
- a.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
- b.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool());
+ if (cell->parameters[ID::A_WIDTH].as_int() != cell->parameters[ID::B_WIDTH].as_int()) {
+ int width = max(cell->parameters[ID::A_WIDTH].as_int(), cell->parameters[ID::B_WIDTH].as_int());
+ a.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
+ b.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
}
RTLIL::SigSpec new_a, new_b;
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
- new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
+ new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
goto next_cell;
}
if (new_a.size() == 0) {
cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
- new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false);
+ new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "empty", ID::Y, new_y);
goto next_cell;
}
cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
- cell->parameters[ID(A_WIDTH)] = new_a.size();
- cell->parameters[ID(B_WIDTH)] = new_b.size();
+ cell->parameters[ID::A_WIDTH] = new_a.size();
+ cell->parameters[ID::B_WIDTH] = new_b.size();
}
}
- if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID(Y_WIDTH)].as_int() == 1 &&
- cell->parameters[ID(A_WIDTH)].as_int() == 1 && cell->parameters[ID(B_WIDTH)].as_int() == 1)
+ if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
+ cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1)
{
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->type = ID($not);
- cell->parameters.erase(ID(B_WIDTH));
- cell->parameters.erase(ID(B_SIGNED));
+ cell->parameters.erase(ID::B_WIDTH);
+ cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B);
did_something = true;
}
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
- cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
+ cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
+ cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
}
cell->unsetPort(ID::B);
- cell->unsetParam(ID(B_SIGNED));
- cell->unsetParam(ID(B_WIDTH));
+ cell->unsetParam(ID::B_SIGNED);
+ cell->unsetParam(ID::B_WIDTH);
did_something = true;
goto next_cell;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const())
{
- bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID(A_SIGNED)).as_bool();
- int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID(B_SIGNED)).as_bool());
+ bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
+ int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool());
if (cell->type.in(ID($shl), ID($sshl)))
shift_bits *= -1;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
- RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID(Y_WIDTH)).as_int());
+ RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
if (GetSize(sig_a) < GetSize(sig_y))
- sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID(A_SIGNED)).as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits;
bool sub = cell->type == ID($sub);
if (cell->type == ID($alu)) {
- RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
- RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
sub = (sig_ci == State::S1 && sig_bi == State::S1);
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
- if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID(A_SIGNED)).as_bool(), arith_inverse))
+ if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID::A_SIGNED).as_bool(), arith_inverse))
identity_wrt_b = true;
else
- if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID(B_SIGNED)).as_bool(), arith_inverse))
+ if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID::B_SIGNED).as_bool(), arith_inverse))
identity_wrt_a = true;
}
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (cell->type == ID($alu)) {
- int y_width = GetSize(cell->getPort(ID(Y)));
- module->connect(cell->getPort(ID(X)), RTLIL::Const(State::S0, y_width));
- module->connect(cell->getPort(ID(CO)), RTLIL::Const(State::S0, y_width));
- cell->unsetPort(ID(BI));
- cell->unsetPort(ID(CI));
- cell->unsetPort(ID(X));
- cell->unsetPort(ID(CO));
+ int y_width = GetSize(cell->getPort(ID::Y));
+ module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width));
+ module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
+ cell->unsetPort(ID::BI);
+ cell->unsetPort(ID::CI);
+ cell->unsetPort(ID::X);
+ cell->unsetPort(ID::CO);
}
if (!identity_wrt_a) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
- cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
+ cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
+ cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
}
cell->type = arith_inverse ? ID($neg) : ID($pos);
cell->unsetPort(ID::B);
- cell->parameters.erase(ID(B_WIDTH));
- cell->parameters.erase(ID(B_SIGNED));
+ cell->parameters.erase(ID::B_WIDTH);
+ cell->parameters.erase(ID::B_SIGNED);
cell->check();
did_something = true;
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
- replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID(S)));
+ replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S));
goto next_cell;
}
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::A, cell->getPort(ID(S)));
+ cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($not);
} else
cell->type = ID($_NOT_);
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::A, cell->getPort(ID(S)));
- cell->unsetPort(ID(S));
+ cell->setPort(ID::A, cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(B_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters[ID(B_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::B_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters[ID::B_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($and);
} else
cell->type = ID($_AND_);
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
- cell->setPort(ID::B, cell->getPort(ID(S)));
- cell->unsetPort(ID(S));
+ cell->setPort(ID::B, cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
if (cell->type == ID($mux)) {
- Const width = cell->parameters[ID(WIDTH)];
- cell->parameters[ID(A_WIDTH)] = width;
- cell->parameters[ID(B_WIDTH)] = width;
- cell->parameters[ID(Y_WIDTH)] = width;
- cell->parameters[ID(A_SIGNED)] = 0;
- cell->parameters[ID(B_SIGNED)] = 0;
- cell->parameters.erase(ID(WIDTH));
+ Const width = cell->parameters[ID::WIDTH];
+ cell->parameters[ID::A_WIDTH] = width;
+ cell->parameters[ID::B_WIDTH] = width;
+ cell->parameters[ID::Y_WIDTH] = width;
+ cell->parameters[ID::A_SIGNED] = 0;
+ cell->parameters[ID::B_SIGNED] = 0;
+ cell->parameters.erase(ID::WIDTH);
cell->type = ID($or);
} else
cell->type = ID($_OR_);
RTLIL::SigSpec new_a, new_b, new_s;
int width = GetSize(cell->getPort(ID::A));
if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
- cell->getPort(ID(S)).is_fully_undef()) {
+ cell->getPort(ID::S).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
goto next_cell;
}
- for (int i = 0; i < cell->getPort(ID(S)).size(); i++) {
+ for (int i = 0; i < cell->getPort(ID::S).size(); i++) {
RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width);
- RTLIL::SigSpec old_s = cell->getPort(ID(S)).extract(i, 1);
+ RTLIL::SigSpec old_s = cell->getPort(ID::S).extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef())
continue;
new_b.append(old_b);
replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s);
goto next_cell;
}
- if (cell->getPort(ID(S)).size() != new_s.size()) {
+ if (cell->getPort(ID::S).size() != new_s.size()) {
cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
- GetSize(cell->getPort(ID(S))) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
+ GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b);
- cell->setPort(ID(S), new_s);
+ cell->setPort(ID::S, new_s);
if (new_s.size() > 1) {
cell->type = ID($pmux);
- cell->parameters[ID(S_WIDTH)] = new_s.size();
+ cell->parameters[ID::S_WIDTH] = new_s.size();
} else {
cell->type = ID($mux);
- cell->parameters.erase(ID(S_WIDTH));
+ cell->parameters.erase(ID::S_WIDTH);
}
did_something = true;
}
}
#define FOLD_1ARG_CELL(_t) \
- if (cell->type == "$" #_t) { \
+ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \
assign_map.apply(a); \
if (a.is_fully_const()) { \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
- cell->parameters[ID(A_SIGNED)].as_bool(), false, \
- cell->parameters[ID(Y_WIDTH)].as_int())); \
+ cell->parameters[ID::A_SIGNED].as_bool(), false, \
+ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \
goto next_cell; \
} \
}
#define FOLD_2ARG_CELL(_t) \
- if (cell->type == "$" #_t) { \
+ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \
RTLIL::SigSpec b = cell->getPort(ID::B); \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
- cell->parameters[ID(A_SIGNED)].as_bool(), \
- cell->parameters[ID(B_SIGNED)].as_bool(), \
- cell->parameters[ID(Y_WIDTH)].as_int())); \
+ cell->parameters[ID::A_SIGNED].as_bool(), \
+ cell->parameters[ID::B_SIGNED].as_bool(), \
+ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
goto next_cell; \
// be very conservative with optimizing $mux cells as we do not want to break mux trees
if (cell->type == ID($mux)) {
- RTLIL::SigSpec input = assign_map(cell->getPort(ID(S)));
+ RTLIL::SigSpec input = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B));
if (input.is_fully_const())
if (!keepdc && cell->type == ID($mul))
{
- bool a_signed = cell->parameters[ID(A_SIGNED)].as_bool();
- bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
+ bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
+ bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
bool swapped_ab = false;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
if (!swapped_ab) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
- cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
+ cell->parameters.at(ID::A_WIDTH) = cell->parameters.at(ID::B_WIDTH);
+ cell->parameters.at(ID::A_SIGNED) = cell->parameters.at(ID::B_SIGNED);
}
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
new_b.pop_back();
cell->type = ID($shl);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
- cell->parameters[ID(B_SIGNED)] = false;
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
+ cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
cell->check();
if (!keepdc && cell->type.in(ID($div), ID($mod)))
{
- bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool();
+ bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
SigSpec sig_b = assign_map(cell->getPort(ID::B));
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
new_b.pop_back();
cell->type = ID($shr);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
- cell->parameters[ID(B_SIGNED)] = false;
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
+ cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
cell->check();
}
new_b.push_back(State::S0);
cell->type = ID($and);
- cell->parameters[ID(B_WIDTH)] = GetSize(new_b);
+ cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->setPort(ID::B, new_b);
cell->check();
}
contradiction_cache.promote(State::S0);
contradiction_cache.promote(State::S1);
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width);
SigSpec sig_a = cell->getPort(ID::A);
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
- cell->setParam(ID(A_WIDTH), GetSize(sig_a));
- cell->setParam(ID(B_WIDTH), GetSize(sig_b));
+ cell->setParam(ID::A_WIDTH, GetSize(sig_a));
+ cell->setParam(ID::B_WIDTH, GetSize(sig_b));
did_something = true;
goto next_cell;
IdString cmp_type = cell->type;
SigSpec var_sig = cell->getPort(ID::A);
SigSpec const_sig = cell->getPort(ID::B);
- int var_width = cell->parameters[ID(A_WIDTH)].as_int();
- int const_width = cell->parameters[ID(B_WIDTH)].as_int();
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ int var_width = cell->parameters[ID::A_WIDTH].as_int();
+ int const_width = cell->parameters[ID::B_WIDTH].as_int();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
if (!const_sig.is_fully_const())
{
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
SigSpec lut_input = sigmap(lut->getPort(ID::A));
- int lut_width = lut->getParam(ID(WIDTH)).as_int();
- Const lut_table = lut->getParam(ID(LUT));
+ int lut_width = lut->getParam(ID::WIDTH).as_int();
+ Const lut_table = lut->getParam(ID::LUT);
int lut_index = 0;
for (int i = 0; i < lut_width; i++)
if (lut_output.wire->get_bool_attribute(ID::keep))
continue;
- int lut_width = cell->getParam(ID(WIDTH)).as_int();
+ int lut_width = cell->getParam(ID::WIDTH).as_int();
SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0;
auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
- int lutA_width = lutA->getParam(ID(WIDTH)).as_int();
+ int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
auto lutB = port.cell;
SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
- int lutB_width = lutB->getParam(ID(WIDTH)).as_int();
+ int lutB_width = lutB->getParam(ID::WIDTH).as_int();
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
else if (lutB_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
- else if (lutB->get_bool_attribute(ID(lut_keep)))
+ else if (lutB->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_A;
log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
else if (lutA_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
- else if (lutA->get_bool_attribute(ID(lut_keep)))
+ else if (lutA->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
else
combine_mask |= COMBINE_B;
lutR_unique.insert(bit);
}
- int lutM_width = lutM->getParam(ID(WIDTH)).as_int();
+ int lutM_width = lutM->getParam(ID::WIDTH).as_int();
SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++)
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
}
- log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID(LUT)).as_string().c_str());
- log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID(LUT)).as_string().c_str());
+ log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
+ log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
- lutM->setParam(ID(LUT), lutM_new_table);
+ lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs);
lutM->setPort(ID::Y, lutB_output);
continue;
inputs = cell->getPort(ID::A).bits();
output = cell->getPort(ID::Y);
- lut = cell->getParam(ID(LUT));
+ lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin") {
if (cell->type == ID(LUT1)) {
inputs = {
// Not a LUT.
continue;
}
- lut = cell->getParam(ID(INIT));
+ lut = cell->getParam(ID::INIT);
if (techname == "xilinx")
- output = cell->getPort(ID(O));
+ output = cell->getPort(ID::O);
else
- output = cell->getPort(ID(F));
+ output = cell->getPort(ID::F);
} else if (techname == "ecp5") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
cell->getPort(ID::B),
- cell->getPort(ID(C)),
- cell->getPort(ID(D)),
+ cell->getPort(ID::C),
+ cell->getPort(ID::D),
};
- lut = cell->getParam(ID(INIT));
+ lut = cell->getParam(ID::INIT);
output = cell->getPort(ID(Z));
ignore_const = true;
} else {
module->connect(output, new_lut[0]);
} else {
if (techname == "") {
- cell->setParam(ID(LUT), new_lut);
- cell->setParam(ID(WIDTH), GetSize(new_inputs));
+ cell->setParam(ID::LUT, new_lut);
+ cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs);
} else if (techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4);
- cell->setParam(ID(INIT), new_lut);
+ cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]);
cell->setPort(ID::B, new_inputs[1]);
- cell->setPort(ID(C), new_inputs[2]);
- cell->setPort(ID(D), new_inputs[3]);
+ cell->setPort(ID::C, new_inputs[2]);
+ cell->setPort(ID::D, new_inputs[3]);
} else {
// xilinx, gowin
- cell->setParam(ID(INIT), new_lut);
+ cell->setParam(ID::INIT, new_lut);
if (techname == "xilinx")
log_assert(GetSize(new_inputs) <= 6);
else
for (auto cell : module->cells())
{
if (cell->type == ID($memrd)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
memrd.at(id).push_back(cell->name);
}
if (cell->type == ID($memwr)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
memwr.at(id).push_back(cell->name);
}
if (cell->type == ID($meminit)) {
- IdString id = cell->getParam(ID(MEMID)).decode_string();
+ IdString id = cell->getParam(ID::MEMID).decode_string();
meminit.at(id).push_back(cell->name);
}
}
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{
- SigSpec sig_s = conn.at(ID(S));
+ SigSpec sig_s = conn.at(ID::S);
SigSpec sig_b = conn.at(ID::B);
int s_width = GetSize(sig_s);
std::sort(sb_pairs.begin(), sb_pairs.end());
- conn[ID(S)] = SigSpec();
+ conn[ID::S] = SigSpec();
conn[ID::B] = SigSpec();
for (auto &it : sb_pairs) {
- conn[ID(S)].append(it.first);
+ conn[ID::S].append(it.first);
conn[ID::B].append(it.second);
}
}
alt_conn = *conn;
assign_map.apply(alt_conn.at(ID::A));
assign_map.apply(alt_conn.at(ID::B));
- assign_map.apply(alt_conn.at(ID(S)));
+ assign_map.apply(alt_conn.at(ID::S));
sort_pmux_conn(alt_conn);
conn = &alt_conn;
}
for (auto &it : *conn) {
RTLIL::SigSpec sig;
if (cell->output(it.first)) {
- if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
// For the 'Q' output of state elements,
// use its (* init *) attribute value
for (const auto &b : dff_init_map(it.second))
for (const auto &it : cell1->connections_) {
if (cell1->output(it.first)) {
- if (it.first == ID(Q) && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
+ if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
- cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
// For the 'Q' output of state elements,
// use the (* init *) attribute value
auto &sig1 = conn1[it.first];
dff_init_map.set(module);
for (auto &it : module->wires_)
- if (it.second->attributes.count(ID(init)) != 0) {
- Const initval = it.second->attributes.at(ID(init));
+ if (it.second->attributes.count(ID::init) != 0) {
+ Const initval = it.second->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]);
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
- if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
+ if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
+ cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
for (auto c : it.second.chunks()) {
- auto jt = c.wire->attributes.find(ID(init));
+ auto jt = c.wire->attributes.find(ID::init);
if (jt == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset + c.width; i++)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
- RTLIL::SigSpec sig_s = cell->getPort(ID(S));
+ RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
muxinfo_t muxinfo;
RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B);
- RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S));
+ RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y);
RTLIL::SigSpec sig_ports = sig_b;
mi.cell->setPort(ID::A, new_sig_a);
mi.cell->setPort(ID::B, new_sig_b);
- mi.cell->setPort(ID(S), new_sig_s);
+ mi.cell->setPort(ID::S, new_sig_s);
if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux);
- mi.cell->parameters.erase(ID(S_WIDTH));
+ mi.cell->parameters.erase(ID::S_WIDTH);
} else {
- mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s));
+ mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s));
}
}
}
idict<int> ctrl_bits;
if (portname == ID::B)
width = GetSize(muxinfo.cell->getPort(ID::A));
- for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false))
+ for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false))
ctrl_bits(bit);
int port_idx = 0, port_off = 0;
}
cell->setPort(ID::A, new_sig_a);
- cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return;
}
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
- RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
+ RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
- reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
- reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
- reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
+ reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
+ reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
else
{
cell->setPort(ID::B, new_sig_b);
- cell->setPort(ID(S), new_sig_s);
+ cell->setPort(ID::S, new_sig_s);
if (new_sig_s.size() > 1) {
- cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
+ cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
cell->type = ID($mux);
- cell->parameters.erase(ID(S_WIDTH));
+ cell->parameters.erase(ID::S_WIDTH);
}
}
}
}
cell->setPort(ID::B, RTLIL::SigSpec());
- for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
+ for (int i = 1; i <= cell->getPort(ID::S).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.append(in_tuple.at(i));
cell->setPort(ID::B, new_b);
}
- cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size());
cell->setPort(ID::Y, new_sig_y);
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mem))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
if (cell->type == ID($memwr))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
- mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
+ if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
+ mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
}
bool keep_expanding_mem_wren_sigs = true;
for (auto bit : assign_map(sig))
if (init_attributes.count(bit))
for (auto wbit : init_attributes.at(bit))
- wbit.wire->attributes.at(ID(init))[wbit.offset] = State::Sx;
+ wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx;
}
bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
SigSpec sig_set, sig_clr;
State pol_set, pol_clr;
- if (cell->hasPort(ID(S)))
- sig_set = cell->getPort(ID(S));
+ if (cell->hasPort(ID::S))
+ sig_set = cell->getPort(ID::S);
- if (cell->hasPort(ID(R)))
- sig_clr = cell->getPort(ID(R));
+ if (cell->hasPort(ID::R))
+ sig_clr = cell->getPort(ID::R);
- if (cell->hasPort(ID(SET)))
- sig_set = cell->getPort(ID(SET));
+ if (cell->hasPort(ID::SET))
+ sig_set = cell->getPort(ID::SET);
- if (cell->hasPort(ID(CLR)))
- sig_clr = cell->getPort(ID(CLR));
+ if (cell->hasPort(ID::CLR))
+ sig_clr = cell->getPort(ID::CLR);
log_assert(GetSize(sig_set) == GetSize(sig_clr));
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else
if (cell->type.in(ID($dffsr), ID($dlatchsr))) {
- pol_set = cell->parameters[ID(SET_POLARITY)].as_bool() ? State::S1 : State::S0;
- pol_clr = cell->parameters[ID(CLR_POLARITY)].as_bool() ? State::S1 : State::S0;
+ pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0;
+ pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0;
} else
log_abort();
State npol_set = pol_set == State::S0 ? State::S1 : State::S0;
State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0;
- SigSpec sig_d = cell->getPort(ID(D));
- SigSpec sig_q = cell->getPort(ID(Q));
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
bool did_something = false;
bool proper_sr = false;
if (cell->type.in(ID($dffsr), ID($dlatchsr)))
{
- cell->setParam(ID(WIDTH), GetSize(sig_d));
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setParam(ID::WIDTH, GetSize(sig_d));
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
}
else
{
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
}
if (proper_sr)
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod));
cell->type = ID($adff);
- cell->setParam(ID(ARST_POLARITY), unified_pol);
- cell->setParam(ID(ARST_VALUE), reset_val);
- cell->setPort(ID(ARST), sig_reset);
-
- cell->unsetParam(ID(SET_POLARITY));
- cell->unsetParam(ID(CLR_POLARITY));
- cell->unsetPort(ID(SET));
- cell->unsetPort(ID(CLR));
+ cell->setParam(ID::ARST_POLARITY, unified_pol);
+ cell->setParam(ID::ARST_VALUE, reset_val);
+ cell->setPort(ID::ARST, sig_reset);
+
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
}
else
{
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod));
cell->type = ID($dff);
- cell->unsetParam(ID(SET_POLARITY));
- cell->unsetParam(ID(CLR_POLARITY));
- cell->unsetPort(ID(SET));
- cell->unsetPort(ID(CLR));
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
}
return true;
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod));
cell->type = new_type;
- cell->unsetPort(ID(S));
- cell->unsetPort(ID(R));
+ cell->unsetPort(ID::S);
+ cell->unsetPort(ID::R);
return true;
}
State on_state, off_state;
if (dlatch->type == ID($dlatch)) {
- sig_e = assign_map(dlatch->getPort(ID(EN)));
- on_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S1 : State::S0;
- off_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S0 : State::S1;
+ sig_e = assign_map(dlatch->getPort(ID::EN));
+ on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0;
+ off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1;
} else
if (dlatch->type == ID($_DLATCH_P_)) {
- sig_e = assign_map(dlatch->getPort(ID(E)));
+ sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S1;
off_state = State::S0;
} else
if (dlatch->type == ID($_DLATCH_N_)) {
- sig_e = assign_map(dlatch->getPort(ID(E)));
+ sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S0;
off_state = State::S1;
} else
if (sig_e == off_state)
{
RTLIL::Const val_init;
- for (auto bit : dff_init_map(dlatch->getPort(ID(Q))))
+ for (auto bit : dff_init_map(dlatch->getPort(ID::Q)))
val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
- mod->connect(dlatch->getPort(ID(Q)), val_init);
+ mod->connect(dlatch->getPort(ID::Q), val_init);
goto delete_dlatch;
}
if (sig_e == on_state)
{
- mod->connect(dlatch->getPort(ID(Q)), dlatch->getPort(ID(D)));
+ mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D));
goto delete_dlatch;
}
delete_dlatch:
log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
- remove_init_attr(dlatch->getPort(ID(Q)));
+ remove_init_attr(dlatch->getPort(ID::Q));
mod->remove(dlatch);
return true;
}
RTLIL::Const val_cp, val_rp, val_rv, val_ep;
if (dff->type == ID($_FF_)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
}
else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1);
}
else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
- sig_r = dff->getPort(ID(R));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
+ sig_r = dff->getPort(ID::R);
val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1);
else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == 'N' || dff->type[8] == 'P')) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(C));
- sig_e = dff->getPort(ID(E));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::C);
+ sig_e = dff->getPort(ID::E);
val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
}
else if (dff->type == ID($ff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
}
else if (dff->type == ID($dff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
}
else if (dff->type == ID($dffe)) {
- sig_e = dff->getPort(ID(EN));
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
- val_ep = RTLIL::Const(dff->parameters[ID(EN_POLARITY)].as_bool(), 1);
+ sig_e = dff->getPort(ID::EN);
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
+ val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1);
}
else if (dff->type == ID($adff)) {
- sig_d = dff->getPort(ID(D));
- sig_q = dff->getPort(ID(Q));
- sig_c = dff->getPort(ID(CLK));
- sig_r = dff->getPort(ID(ARST));
- val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1);
- val_rp = RTLIL::Const(dff->parameters[ID(ARST_POLARITY)].as_bool(), 1);
- val_rv = dff->parameters[ID(ARST_VALUE)];
+ sig_d = dff->getPort(ID::D);
+ sig_q = dff->getPort(ID::Q);
+ sig_c = dff->getPort(ID::CLK);
+ sig_r = dff->getPort(ID::ARST);
+ val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
+ val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1);
+ val_rv = dff->parameters[ID::ARST_VALUE];
}
else
log_abort();
if (dff->type == ID($adff)) {
dff->type = ID($dff);
- dff->unsetPort(ID(ARST));
- dff->unsetParam(ID(ARST_POLARITY));
- dff->unsetParam(ID(ARST_VALUE));
+ dff->unsetPort(ID::ARST);
+ dff->unsetParam(ID::ARST_POLARITY);
+ dff->unsetParam(ID::ARST_VALUE);
return true;
}
log_assert(dff->type.begins_with("$_DFF_"));
dff->type = stringf("$_DFF_%c_", + dff->type[6]);
- dff->unsetPort(ID(R));
+ dff->unsetPort(ID::R);
}
// If enable signal is present, and is fully constant
if (dff->type == ID($dffe)) {
dff->type = ID($dff);
- dff->unsetPort(ID(EN));
- dff->unsetParam(ID(EN_POLARITY));
+ dff->unsetPort(ID::EN);
+ dff->unsetParam(ID::EN_POLARITY);
return true;
}
log_assert(dff->type.begins_with("$_DFFE_"));
dff->type = stringf("$_DFF_%c_", + dff->type[7]);
- dff->unsetPort(ID(E));
+ dff->unsetPort(ID::E);
}
if (sat && has_init && (!sig_r.size() || val_init == val_rv))
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0,
position, log_id(dff), log_id(dff->type), log_id(mod));
- SigSpec tmp = dff->getPort(ID(D));
+ SigSpec tmp = dff->getPort(ID::D);
tmp[position] = sigbit_init_val;
- dff->setPort(ID(D), tmp);
+ dff->setPort(ID::D, tmp);
removed_sigbits = true;
}
delete_dff:
log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
- remove_init_attr(dff->getPort(ID(Q)));
+ remove_init_attr(dff->getPort(ID::Q));
mod->remove(dff);
for (auto &entry : bit2driver)
for (auto wire : module->wires())
{
- if (wire->attributes.count(ID(init)) != 0) {
- Const initval = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init) != 0) {
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(wire, i), initval[i]);
bool cell_supported(RTLIL::Cell *cell)
{
if (cell->type.in(ID($alu))) {
- RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
- RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
+ RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
+ RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
if (cell->type == ID($alu) && port_name == ID::B)
- return cell->getPort(ID(BI));
+ return cell->getPort(ID::BI);
else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1);
auto shared_op = ports[0].op;
if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
- max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int());
+ max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
for (auto &operand : muxed_operands)
RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B);
- RTLIL::SigSpec mux_s = mux->getPort(ID(S));
+ RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
RTLIL::SigSpec shared_pmux_b;
mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b);
mux->setPort(ID::Y, mux_y);
- mux->setPort(ID(S), mux_s);
+ mux->setPort(ID::S, mux_s);
for (const auto &op : muxed_operands)
shared_pmux_b.append(op.sig);
auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
if (shared_op->type.in(ID($alu))) {
- RTLIL::SigSpec alu_x = shared_op->getPort(ID(X));
- RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO));
+ RTLIL::SigSpec alu_x = shared_op->getPort(ID::X);
+ RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO);
- shared_op->setPort(ID(X), alu_x.extract(0, conn_width));
- shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
+ shared_op->setPort(ID::X, alu_x.extract(0, conn_width));
+ shared_op->setPort(ID::CO, alu_co.extract(0, conn_width));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
if (!is_fine)
- shared_op->setParam(ID(Y_WIDTH), conn_width);
+ shared_op->setParam(ID::Y_WIDTH, conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
if (!is_fine)
- shared_op->setParam(ID(B_WIDTH), max_width);
+ shared_op->setParam(ID::B_WIDTH, max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
if (!is_fine)
- shared_op->setParam(ID(A_WIDTH), max_width);
+ shared_op->setParam(ID::A_WIDTH, max_width);
}
}
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
- remove_connected_ops(cell->getPort(ID(S)));
+ remove_connected_ops(cell->getPort(ID::S));
find_op_mux_conns(cell);
} else {
for (auto &conn : cell->connections())
continue;
if (cell->type == ID($alu)) {
- for (RTLIL::IdString port_name : {ID(X), ID(CO)}) {
+ for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
auto mux_insig = assign_map(cell->getPort(port_name));
outsig_to_operator[mux_insig] = cell;
for (auto outbit : mux_insig)
if (p.mux->type.in(ID($mux), ID($_MUX_)))
mux_port_num = 2;
else
- mux_port_num = p.mux->getPort(ID(S)).size();
+ mux_port_num = p.mux->getPort(ID::S).size();
mux_port_conns.resize(mux_port_num);
}
for (auto wire : module->wires())
{
- auto it = wire->attributes.find(ID(init));
+ auto it = wire->attributes.find(ID::init);
if (it == wire->attributes.end())
continue;
if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
{
- output = cell->getPort(ID(Q));
+ output = cell->getPort(ID::Q);
if (cell->type == ID($adff))
- inputs.push_back(cell->getParam(ID(ARST_VALUE)));
- inputs.push_back(cell->getPort(ID(D)));
+ inputs.push_back(cell->getParam(ID::ARST_VALUE));
+ inputs.push_back(cell->getPort(ID::D));
}
if (cell->type.in(ID($mux), ID($pmux)))
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
+ bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
+ bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed);
}
continue;
string src = cell->get_src_attribute();
- int width = cell->getParam(ID(WIDTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
int width_bits = ceil_log2(width);
int extwidth = width;
SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B);
- SigSpec S = sigmap(cell->getPort(ID(S)));
+ SigSpec S = sigmap(cell->getPort(ID::S));
for (int i = 0; i < GetSize(S); i++)
{
if (!eqdb.count(S[i]))
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
- SigSpec updated_S = cell->getPort(ID(S));
+ SigSpec updated_S = cell->getPort(ID::S);
SigSpec updated_B = cell->getPort(ID::B);
while (!seldb.empty())
}
// update $pmux cell
- cell->setPort(ID(S), updated_S);
+ cell->setPort(ID::S, updated_S);
cell->setPort(ID::B, updated_B);
- cell->setParam(ID(S_WIDTH), GetSize(updated_S));
+ cell->setParam(ID::S_WIDTH, GetSize(updated_S));
}
}
}
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
- int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) {
- bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
+ bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed);
}
if (b_width < a_width) {
- bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
+ bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed);
}
for (auto &pbit : portbits) {
if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
- pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool();
+ pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
- supercell->setParam(ID(Y_WIDTH), width);
+ supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
supermacc.optimize(width);
}
if (cell->type == ID($memrd)) {
- if (cell->parameters.at(ID(CLK_ENABLE)).as_bool())
+ if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
- if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const())
+ if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
shareable_cells.insert(cell);
continue;
}
if (cell->type.in(ID($mul), ID($div), ID($mod))) {
- if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4)
+ if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
shareable_cells.insert(cell);
continue;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
- if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8)
+ if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
shareable_cells.insert(cell);
continue;
}
if (c1->type == ID($memrd))
{
- if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string())
+ if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
return false;
return true;
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
{
if (!config.opt_aggressive)
{
- int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int();
- int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int();
- int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int();
+ int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
+ int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
+ int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
- int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int();
- int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int();
- int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int();
+ int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
+ int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
+ int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
int min1_width = min(a1_width, b1_width);
int max1_width = max(a1_width, b1_width);
if (config.generic_uni_ops.count(c1->type))
{
- if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
- unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::A_SIGNED) = true;
unsigned_cell->check();
}
- bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
- log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
+ bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
+ log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters[ID(A_SIGNED)] = a_signed;
- supercell->parameters[ID(A_WIDTH)] = a_width;
- supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->parameters[ID::A_SIGNED] = a_signed;
+ supercell->parameters[ID::A_WIDTH] = a_width;
+ supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
if (config.generic_cbin_ops.count(c1->type))
{
- int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) +
- max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int());
+ int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
+ max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
- int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) +
- max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int());
+ int score_flipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()) +
+ max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int());
if (score_flipped < score_unflipped)
{
c2->setPort(ID::A, c2->getPort(ID::B));
c2->setPort(ID::B, tmp);
- std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH)));
- std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED)));
+ std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH));
+ std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED));
modified_src_cells = true;
}
}
- if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
}
- unsigned_cell->parameters.at(ID(A_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::A_SIGNED) = true;
modified_src_cells = true;
}
- if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool())
+ if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool())
{
- RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1;
+ RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
- unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1;
+ unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b);
}
- unsigned_cell->parameters.at(ID(B_SIGNED)) = true;
+ unsigned_cell->parameters.at(ID::B_SIGNED) = true;
modified_src_cells = true;
}
c2->check();
}
- bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool();
- bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool();
+ bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
+ bool b_signed = c1->parameters.at(ID::B_SIGNED).as_bool();
- log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool());
- log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool());
+ log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
+ log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
- supercell->parameters[ID(A_SIGNED)] = a_signed;
- supercell->parameters[ID(B_SIGNED)] = b_signed;
- supercell->parameters[ID(A_WIDTH)] = a_width;
- supercell->parameters[ID(B_WIDTH)] = b_width;
- supercell->parameters[ID(Y_WIDTH)] = y_width;
+ supercell->parameters[ID::A_SIGNED] = a_signed;
+ supercell->parameters[ID::B_SIGNED] = b_signed;
+ supercell->parameters[ID::A_WIDTH] = a_width;
+ supercell->parameters[ID::B_WIDTH] = b_width;
+ supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci));
- supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi));
- supercell->setPort(ID(CI), ci);
- supercell->setPort(ID(BI), bi);
- supercell->setPort(ID(CO), co);
- supercell->setPort(ID(X), x);
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
+ supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
+ supercell->setPort(ID::CI, ci);
+ supercell->setPort(ID::BI, bi);
+ supercell->setPort(ID::CO, co);
+ supercell->setPort(ID::X, x);
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
if (c1->type == ID($alu)) {
- supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO))));
- supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO))));
- supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X))));
- supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X))));
+ supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
+ supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
+ supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
}
supercell_aux.insert(supercell);
if (c1->type == ID($memrd))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
- RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR));
- RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR));
+ RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
+ RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
- supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
- supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1));
- supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA))));
+ supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
+ supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
+ supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
for (auto &bit : pbits) {
- if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S))
- forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1));
+ if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S)
+ forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
bool used_in_a = false;
std::set<int> used_in_b_parts;
- int width = c->parameters.at(ID(WIDTH)).as_int();
+ int width = c->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B));
- std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S)));
+ std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))
for (auto cell : module->cells())
if (cell->type == ID($pmux))
- for (auto bit : cell->getPort(ID(S)))
- for (auto other_bit : cell->getPort(ID(S)))
+ for (auto bit : cell->getPort(ID::S))
+ for (auto other_bit : cell->getPort(ID::S))
if (bit < other_bit)
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
- SigSpec sig_s = mi.sigmap(cell->getPort(ID(S)));
+ SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
std::vector<SigBit> bits_removed;
{
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
- SigSpec sig_d = mi.sigmap(cell->getPort(ID(D)));
- SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q)));
+ SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
+ SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
bool is_adff = (cell->type == ID($adff));
Const initval, arst_value;
if (width_before == 0)
return;
- if (cell->parameters.count(ID(ARST_VALUE))) {
- arst_value = cell->parameters[ID(ARST_VALUE)];
+ if (cell->parameters.count(ID::ARST_VALUE)) {
+ arst_value = cell->parameters[ID::ARST_VALUE];
}
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
work_queue_bits.insert(bit);
// Narrow ARST_VALUE parameter to new size.
- if (cell->parameters.count(ID(ARST_VALUE))) {
+ if (cell->parameters.count(ID::ARST_VALUE)) {
arst_value.bits.resize(GetSize(sig_q));
- cell->setParam(ID(ARST_VALUE), arst_value);
+ cell->setParam(ID::ARST_VALUE, arst_value);
}
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->fixup_parameters();
}
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam(ID(A_SIGNED), 0);
- cell->setParam(ID(B_SIGNED), 0);
+ cell->setParam(ID::A_SIGNED, 0);
+ cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false;
port_b_signed = false;
did_something = true;
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type));
- cell->setParam(ID(A_SIGNED), 0);
+ cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false;
did_something = true;
}
if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
{
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub);
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0;
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{
int count = w->attributes.size();
- count -= w->attributes.count(ID(src));
- count -= w->attributes.count(ID(unused_bits));
+ count -= w->attributes.count(ID::src);
+ count -= w->attributes.count(ID::unused_bits);
return count;
}
if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w))
keep_bits.insert(bit);
- if (w->attributes.count(ID(init))) {
- Const initval = w->attributes.at(ID(init));
+ if (w->attributes.count(ID::init)) {
+ Const initval = w->attributes.at(ID::init);
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++)
if (!remove_init_bits.empty()) {
for (auto w : module->wires()) {
- if (w->attributes.count(ID(init))) {
- Const initval = w->attributes.at(ID(init));
+ if (w->attributes.count(ID::init)) {
+ Const initval = w->attributes.at(ID::init);
Const new_initval(State::Sx, GetSize(w));
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
- w->attributes.at(ID(init)) = new_initval;
+ w->attributes.at(ID::init) = new_initval;
}
}
}
SigSpec sig = c->getPort(ID::Y);
if (!sig.has_const()) {
c->setPort(ID::Y, sig[0]);
- c->setParam(ID(Y_WIDTH), 1);
+ c->setParam(ID::Y_WIDTH, 1);
sig.remove(0);
module->connect(sig, Const(0, GetSize(sig)));
}
{
SigSpec A = c->getPort(ID::A);
int original_a_width = GetSize(A);
- if (c->getParam(ID(A_SIGNED)).as_bool()) {
+ if (c->getParam(ID::A_SIGNED).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
A.remove(GetSize(A)-1, 1);
} else {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::A, A);
- c->setParam(ID(A_WIDTH), GetSize(A));
+ c->setParam(ID::A_WIDTH, GetSize(A));
}
SigSpec B = c->getPort(ID::B);
int original_b_width = GetSize(B);
- if (c->getParam(ID(B_SIGNED)).as_bool()) {
+ if (c->getParam(ID::B_SIGNED).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
B.remove(GetSize(B)-1, 1);
} else {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::B, B);
- c->setParam(ID(B_WIDTH), GetSize(B));
+ c->setParam(ID::B_WIDTH, GetSize(B));
}
}
if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
- IdString memid = c->getParam(ID(MEMID)).decode_string();
+ IdString memid = c->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) {
- int cur_addrbits = c->getParam(ID(ABITS)).as_int();
+ int cur_addrbits = c->getParam(ID::ABITS).as_int();
int max_addrbits = ceil_log2(mem->start_offset + mem->size);
if (cur_addrbits > max_addrbits) {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid));
- c->setParam(ID(ABITS), max_addrbits);
- c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits));
+ c->setParam(ID::ABITS, max_addrbits);
+ c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
}
}
}
// SB_MAC16 Input Interface
SigSpec A = st.sigA;
- A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
+ A.extend_u0(16, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
log_assert(GetSize(A) == 16);
SigSpec B = st.sigB;
- B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
+ B.extend_u0(16, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
log_assert(GetSize(B) == 16);
SigSpec CD = st.sigCD;
cell->setPort(ID::A, A);
cell->setPort(ID::B, B);
- cell->setPort(ID(C), CD.extract(16, 16));
- cell->setPort(ID(D), CD.extract(0, 16));
+ cell->setPort(ID::C, CD.extract(16, 16));
+ cell->setPort(ID::D, CD.extract(0, 16));
cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
SigSpec AHOLD, BHOLD, CDHOLD;
if (st.ffAholdmux)
- AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID(S)));
+ AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S));
else
AHOLD = State::S0;
if (st.ffBholdmux)
- BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID(S)));
+ BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S));
else
BHOLD = State::S0;
if (st.ffCDholdmux)
- CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID(S)));
+ CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S));
else
CDHOLD = State::S0;
cell->setPort(ID(AHOLD), AHOLD);
SigSpec IRSTTOP, IRSTBOT;
if (st.ffArstmux)
- IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID(S)));
+ IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S));
else
IRSTTOP = State::S0;
if (st.ffBrstmux)
- IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID(S)));
+ IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S));
else
IRSTBOT = State::S0;
cell->setPort(ID(IRSTTOP), IRSTTOP);
if (st.clock != SigBit())
{
- cell->setPort(ID(CLK), st.clock);
+ cell->setPort(ID::CLK, st.clock);
cell->setPort(ID(CE), State::S1);
cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
}
else
{
- cell->setPort(ID(CLK), State::S0);
+ cell->setPort(ID::CLK, State::S0);
cell->setPort(ID(CE), State::S0);
cell->setParam(ID(NEG_TRIGGER), State::S0);
}
cell->setPort(ID(SIGNEXTIN), State::Sx);
cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
- cell->setPort(ID(CI), State::Sx);
+ cell->setPort(ID::CI, State::Sx);
cell->setPort(ID(ACCUMCI), State::Sx);
cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
if (O_width == 33) {
log_assert(st.add);
// If we have a signed multiply-add, then perform sign extension
- if (st.add->getParam(ID(A_SIGNED)).as_bool() && st.add->getParam(ID(B_SIGNED)).as_bool())
+ if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool())
pm.module->connect(O[32], O[31]);
else
- cell->setPort(ID(CO), O[32]);
+ cell->setPort(ID::CO, O[32]);
O.remove(O_width-1);
}
else
- cell->setPort(ID(CO), pm.module->addWire(NEW_ID));
+ cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
log_assert(GetSize(O) <= 32);
if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
- cell->setPort(ID(O), O);
+ cell->setPort(ID::O, O);
bool accum = false;
if (st.add) {
SigSpec OHOLD;
if (st.ffOholdmux)
- OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID(S)));
+ OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S));
else
OHOLD = State::S0;
cell->setPort(ID(OHOLDTOP), OHOLD);
SigSpec ORST;
if (st.ffOrstmux)
- ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID(S)));
+ ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S));
else
ORST = State::S0;
cell->setPort(ID(ORSTTOP), ORST);
SigSpec acc_reset = State::S0;
if (st.mux) {
if (st.muxAB == ID::A)
- acc_reset = st.mux->getPort(ID(S));
+ acc_reset = st.mux->getPort(ID::S);
else
- acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID(S)));
+ acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
}
cell->setPort(ID(OLOADTOP), acc_reset);
cell->setPort(ID(OLOADBOT), acc_reset);
cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
cell->setParam(ID(MODE_8x8), State::S0);
- cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool());
- cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool());
+ cell->setParam(ID::A_SIGNED, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
+ cell->setParam(ID::B_SIGNED, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
if (st.ffO) {
if (st.o_lo)
else
cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
- st.ffO->connections_.at(ID(Q)).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
+ st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
}
else {
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
- Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER");
+ Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry);
- cell->setPort(ID::A, st.carry->getPort("\\I0"));
- cell->setPort(ID::B, st.carry->getPort("\\I1"));
- auto CI = st.carry->getPort("\\CI");
- cell->setPort("\\CI", CI);
- cell->setPort("\\CO", st.carry->getPort("\\CO"));
+ cell->setPort(ID::A, st.carry->getPort(ID(I0)));
+ cell->setPort(ID::B, st.carry->getPort(ID(I1)));
+ auto CI = st.carry->getPort(ID::CI);
+ cell->setPort(ID::CI, CI);
+ cell->setPort(ID::CO, st.carry->getPort(ID::CO));
- cell->setPort("\\I0", st.lut->getPort("\\I0"));
- auto I3 = st.lut->getPort("\\I3");
+ cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
+ auto I3 = st.lut->getPort(ID(I3));
if (pm.sigmap(CI) == pm.sigmap(I3)) {
- cell->setParam("\\I3_IS_CI", State::S1);
+ cell->setParam(ID(I3_IS_CI), State::S1);
I3 = State::Sx;
}
else
- cell->setParam("\\I3_IS_CI", State::S0);
- cell->setPort("\\I3", I3);
- cell->setPort("\\O", st.lut->getPort("\\O"));
- cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT"));
+ cell->setParam(ID(I3_IS_CI), State::S0);
+ cell->setPort(ID(I3), I3);
+ cell->setPort(ID::O, st.lut->getPort(ID::O));
+ cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
for (const auto &a : st.carry->attributes)
cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second;
continue;
auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
- carry->setPort(ID(I0), cell->getPort(ID(A)));
- carry->setPort(ID(I1), cell->getPort(ID(B)));
- carry->setPort(ID(CI), cell->getPort(ID(CI)));
- carry->setPort(ID(CO), cell->getPort(ID(CO)));
+ carry->setPort(ID(I0), cell->getPort(ID::A));
+ carry->setPort(ID(I1), cell->getPort(ID::B));
+ carry->setPort(ID::CI, cell->getPort(ID::CI));
+ carry->setPort(ID::CO, cell->getPort(ID::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut));
- lut->setParam(ID(WIDTH), 4);
- lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
- auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
- lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) });
- lut->setPort(ID(Y), cell->getPort(ID(O)));
+ lut->setParam(ID::WIDTH, 4);
+ lut->setParam(ID::LUT, cell->getParam(ID::LUT));
+ auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
+ lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) });
+ lut->setPort(ID::Y, cell->getPort(ID::O));
Const src;
for (const auto &a : cell->attributes)
carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
else if (a.first.begins_with("\\SB_LUT4.\\"))
lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
- else if (a.first == ID(src))
+ else if (a.first == ID::src)
src = a.second;
- else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
+ else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
continue;
else
log_abort();
if (!src.empty()) {
- carry->attributes.insert(std::make_pair(ID(src), src));
- lut->attributes.insert(std::make_pair(ID(src), src));
+ carry->attributes.insert(std::make_pair(ID::src, src));
+ lut->attributes.insert(std::make_pair(ID::src, src));
}
module->remove(cell);
peepopt_pm pm(module);
for (auto w : module->wires()) {
- auto it = w->attributes.find(ID(init));
+ auto it = w->attributes.find(ID::init);
if (it != w->attributes.end()) {
SigSpec sig = pm.sigmap(w);
Const val = it->second;
pm.run_dffmux();
for (auto w : module->wires()) {
- auto it = w->attributes.find(ID(init));
+ auto it = w->attributes.find(ID::init);
if (it != w->attributes.end()) {
SigSpec sig = pm.sigmap(w);
Const &val = it->second;
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
SigSpec A;
- SigSpec Y = ud.longest_chain.front().first->getPort(ID(Y));
+ SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
auto last_cell = ud.longest_chain.back().first;
for (auto it : ud.longest_chain) {
auto cell = it.first;
if (cell == last_cell) {
- A.append(cell->getPort(ID(A)));
- A.append(cell->getPort(ID(B)));
+ A.append(cell->getPort(ID::A));
+ A.append(cell->getPort(ID::B));
} else {
- A.append(cell->getPort(it.second == ID(A) ? ID(B) : ID(A)));
+ A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
}
log(" %s\n", log_id(cell));
pm.autoremove(cell);
return;
SigSpec A = ud.leaves;
- SigSpec Y = st.first->getPort(ID(Y));
+ SigSpec Y = st.first->getPort(ID::Y);
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
cell->setParam(ID(USE_SIMD), Const("ONE48"));
cell->setParam(ID(USE_DPORT), Const("FALSE"));
- cell->setPort(ID(D), Const(0, 25));
+ cell->setPort(ID::D, Const(0, 25));
cell->setPort(ID(INMODE), Const(0, 5));
cell->setPort(ID(ALUMODE), Const(0, 4));
cell->setPort(ID(OPMODE), Const(0, 7));
for (auto cell : selected_cells) {
if (!cell->type.in(ID($add), ID($sub)))
continue;
- SigSpec Y = cell->getPort(ID(Y));
+ SigSpec Y = cell->getPort(ID::Y);
if (!Y.is_chunk())
continue;
if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
continue;
if (GetSize(Y) > 25)
continue;
- SigSpec A = cell->getPort(ID(A));
- SigSpec B = cell->getPort(ID(B));
+ SigSpec A = cell->getPort(ID::A);
+ SigSpec B = cell->getPort(ID::B);
if (GetSize(Y) <= 13) {
if (GetSize(A) > 12)
continue;
}
auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
- SigSpec A = lane->getPort(ID(A));
- SigSpec B = lane->getPort(ID(B));
- SigSpec Y = lane->getPort(ID(Y));
- A.extend_u0(12, lane->getParam(ID(A_SIGNED)).as_bool());
- B.extend_u0(12, lane->getParam(ID(B_SIGNED)).as_bool());
+ SigSpec A = lane->getPort(ID::A);
+ SigSpec B = lane->getPort(ID::B);
+ SigSpec Y = lane->getPort(ID::Y);
+ A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
+ B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
AB.append(A);
C.append(B);
if (GetSize(Y) < 13)
log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4);
- cell->setPort(ID(A), AB.extract(18, 30));
- cell->setPort(ID(B), AB.extract(0, 18));
- cell->setPort(ID(C), C);
- cell->setPort(ID(P), P);
+ cell->setPort(ID::A, AB.extract(18, 30));
+ cell->setPort(ID::B, AB.extract(0, 18));
+ cell->setPort(ID::C, C);
+ cell->setPort(ID::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
g12(simd12_sub);
auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
- SigSpec A = lane->getPort(ID(A));
- SigSpec B = lane->getPort(ID(B));
- SigSpec Y = lane->getPort(ID(Y));
- A.extend_u0(24, lane->getParam(ID(A_SIGNED)).as_bool());
- B.extend_u0(24, lane->getParam(ID(B_SIGNED)).as_bool());
+ SigSpec A = lane->getPort(ID::A);
+ SigSpec B = lane->getPort(ID::B);
+ SigSpec Y = lane->getPort(ID::Y);
+ A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
+ B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
C.append(A);
AB.append(B);
if (GetSize(Y) < 25)
log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4);
- cell->setPort(ID(A), AB.extract(18, 30));
- cell->setPort(ID(B), AB.extract(0, 18));
- cell->setPort(ID(C), C);
- cell->setPort(ID(P), P);
+ cell->setPort(ID::A, AB.extract(18, 30));
+ cell->setPort(ID::B, AB.extract(0, 18));
+ cell->setPort(ID::C, C);
+ cell->setPort(ID::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011"));
if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
- bool A_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
- bool D_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
- if (st.sigA == st.preAdd->getPort(ID(B)))
+ bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+ bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
+ if (st.sigA == st.preAdd->getPort(ID::B))
std::swap(A_SIGNED, D_SIGNED);
st.sigA.extend_u0(30, A_SIGNED);
st.sigD.extend_u0(25, D_SIGNED);
- cell->setPort(ID(A), st.sigA);
- cell->setPort(ID(D), st.sigD);
+ cell->setPort(ID::A, st.sigA);
+ cell->setPort(ID::D, st.sigD);
cell->setPort(ID(INMODE), Const::from_string("00100"));
if (st.ffAD) {
if (st.ffADcemux) {
- SigSpec S = st.ffADcemux->getPort(ID(S));
+ SigSpec S = st.ffADcemux->getPort(ID::S);
cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
}
else
SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) {
log_assert(st.ffP);
- opmode[4] = st.postAddMux->getPort(ID(S));
+ opmode[4] = st.postAddMux->getPort(ID::S);
pm.autoremove(st.postAddMux);
}
else if (st.ffP && st.sigC == st.sigP)
opmode[5] = State::S1;
if (opmode[4] != State::S0) {
- if (st.postAddMuxAB == ID(A))
- st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+ if (st.postAddMuxAB == ID::A)
+ st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else
- st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
- cell->setPort(ID(C), st.sigC);
+ st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+ cell->setPort(ID::C, st.sigC);
}
pm.autoremove(st.postAdd);
cell->setParam(ID(SEL_MASK), Const("MASK"));
if (st.overflow->type == ID($ge)) {
- Const B = st.overflow->getPort(ID(B)).as_const();
+ Const B = st.overflow->getPort(ID::B).as_const();
log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting
cell->setParam(ID(MASK), B);
cell->setParam(ID(PATTERN), Const(0, 48));
- cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID(Y)));
+ cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
}
else log_abort();
if (st.clock != SigBit())
{
- cell->setPort(ID(CLK), st.clock);
+ cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
- SigSpec D = ff->getPort(ID(D));
- SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+ SigSpec D = ff->getPort(ID::D);
+ SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstmux) {
- SigSpec Y = rstmux->getPort(ID(Y));
- SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+ SigSpec Y = rstmux->getPort(ID::Y);
+ SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty())
A.replace(Y, AB);
if (rstport != IdString()) {
- SigSpec S = rstmux->getPort(ID(S));
+ SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
}
}
else if (rstport != IdString())
cell->setPort(rstport, State::S0);
if (cemux) {
- SigSpec Y = cemux->getPort(ID(Y));
- SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
- SigSpec S = cemux->getPort(ID(S));
+ SigSpec Y = cemux->getPort(ID::Y);
+ SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+ SigSpec S = cemux->getPort(ID::S);
if (!A.empty())
A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) {
- auto it = c.wire->attributes.find(ID(init));
+ auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
};
if (st.ffA2) {
- SigSpec A = cell->getPort(ID(A));
+ SigSpec A = cell->getPort(ID::A);
f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA));
if (st.ffA1) {
f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString());
cell->setParam(ID(ACASCREG), 1);
}
pm.add_siguser(A, cell);
- cell->setPort(ID(A), A);
+ cell->setPort(ID::A, A);
}
if (st.ffB2) {
- SigSpec B = cell->getPort(ID(B));
+ SigSpec B = cell->getPort(ID::B);
f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB));
if (st.ffB1) {
f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString());
cell->setParam(ID(BCASCREG), 1);
}
pm.add_siguser(B, cell);
- cell->setPort(ID(B), B);
+ cell->setPort(ID::B, B);
}
if (st.ffD) {
- SigSpec D = cell->getPort(ID(D));
+ SigSpec D = cell->getPort(ID::D);
f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
pm.add_siguser(D, cell);
- cell->setPort(ID(D), D);
+ cell->setPort(ID::D, D);
cell->setParam(ID(DREG), 1);
}
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
- st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+ st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
- st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+ st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
- cell->setPort(ID(P), P);
+ cell->setPort(ID::P, P);
pm.blacklist(cell);
}
if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
- bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool();
- bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool();
+ bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
+ bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED);
st.sigD.extend_u0(18, D_SIGNED);
- cell->setPort(ID(B), st.sigB);
- cell->setPort(ID(D), st.sigD);
+ cell->setPort(ID::B, st.sigB);
+ cell->setPort(ID::D, st.sigD);
opmode[4] = State::S1;
if (st.preAdd->type == ID($add))
opmode[6] = State::S0;
if (st.postAddMux) {
log_assert(st.ffP);
- opmode[2] = st.postAddMux->getPort(ID(S));
+ opmode[2] = st.postAddMux->getPort(ID::S);
pm.autoremove(st.postAddMux);
}
else if (st.ffP && st.sigC == st.sigP)
opmode[3] = State::S1;
if (opmode[2] != State::S0) {
- if (st.postAddMuxAB == ID(A))
- st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool());
+ if (st.postAddMuxAB == ID::A)
+ st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else
- st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool());
- cell->setPort(ID(C), st.sigC);
+ st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
+ cell->setPort(ID::C, st.sigC);
}
pm.autoremove(st.postAdd);
if (st.clock != SigBit())
{
- cell->setPort(ID(CLK), st.clock);
+ cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
- SigSpec D = ff->getPort(ID(D));
- SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+ SigSpec D = ff->getPort(ID::D);
+ SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstmux) {
- SigSpec Y = rstmux->getPort(ID(Y));
- SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+ SigSpec Y = rstmux->getPort(ID::Y);
+ SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty())
A.replace(Y, AB);
if (rstport != IdString()) {
- SigSpec S = rstmux->getPort(ID(S));
+ SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
}
}
else if (rstport != IdString())
cell->setPort(rstport, State::S0);
if (cemux) {
- SigSpec Y = cemux->getPort(ID(Y));
- SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
- SigSpec S = cemux->getPort(ID(S));
+ SigSpec Y = cemux->getPort(ID::Y);
+ SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+ SigSpec S = cemux->getPort(ID::S);
if (!A.empty())
A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) {
- auto it = c.wire->attributes.find(ID(init));
+ auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
};
if (st.ffA0 || st.ffA1) {
- SigSpec A = cell->getPort(ID(A));
+ SigSpec A = cell->getPort(ID::A);
if (st.ffA1) {
f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA));
cell->setParam(ID(A1REG), 1);
cell->setParam(ID(A0REG), 1);
}
pm.add_siguser(A, cell);
- cell->setPort(ID(A), A);
+ cell->setPort(ID::A, A);
}
if (st.ffB0 || st.ffB1) {
- SigSpec B = cell->getPort(ID(B));
+ SigSpec B = cell->getPort(ID::B);
if (st.ffB1) {
f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB));
cell->setParam(ID(B1REG), 1);
cell->setParam(ID(B0REG), 1);
}
pm.add_siguser(B, cell);
- cell->setPort(ID(B), B);
+ cell->setPort(ID::B, B);
}
if (st.ffD) {
- SigSpec D = cell->getPort(ID(D));
+ SigSpec D = cell->getPort(ID::D);
f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
pm.add_siguser(D, cell);
- cell->setPort(ID(D), D);
+ cell->setPort(ID::D, D);
cell->setParam(ID(DREG), 1);
}
if (st.ffM) {
SigSpec M; // unused
f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
- st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
+ st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1);
}
if (st.ffP) {
SigSpec P; // unused
f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
- st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
+ st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1);
}
SigSpec P = st.sigP;
if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
- cell->setPort(ID(P), P);
+ cell->setPort(ID::P, P);
pm.blacklist(cell);
}
if (st.clock != SigBit())
{
- cell->setPort(ID(CLK), st.clock);
+ cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
- SigSpec D = ff->getPort(ID(D));
- SigSpec Q = pm.sigmap(ff->getPort(ID(Q)));
+ SigSpec D = ff->getPort(ID::D);
+ SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty())
A.replace(Q, D);
if (rstmux) {
- SigSpec Y = rstmux->getPort(ID(Y));
- SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B));
+ SigSpec Y = rstmux->getPort(ID::Y);
+ SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty())
A.replace(Y, AB);
if (rstport != IdString()) {
- SigSpec S = rstmux->getPort(ID(S));
+ SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
}
}
else if (rstport != IdString())
cell->setPort(rstport, State::S0);
if (cemux) {
- SigSpec Y = cemux->getPort(ID(Y));
- SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A));
- SigSpec S = cemux->getPort(ID(S));
+ SigSpec Y = cemux->getPort(ID::Y);
+ SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
+ SigSpec S = cemux->getPort(ID::S);
if (!A.empty())
A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) {
- auto it = c.wire->attributes.find(ID(init));
+ auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset+c.width; i++) {
};
if (st.ffC) {
- SigSpec C = cell->getPort(ID(C));
+ SigSpec C = cell->getPort(ID::C);
f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
pm.add_siguser(C, cell);
- cell->setPort(ID(C), C);
+ cell->setPort(ID::C, C);
cell->setParam(ID(CREG), 1);
}
for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
- SigBit Q = cell->getPort(ID(Q));
+ SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire);
- auto it = Q.wire->attributes.find(ID(init));
+ auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
initval.append(i);
initval.append(State::Sx);
}
else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
- if (cell->parameters.at(ID(INIT), State::S0).as_bool())
+ if (cell->parameters.at(ID::INIT, State::S0).as_bool())
initval.append(State::S1);
else
initval.append(State::S0);
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
- c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
- c->setParam(ID(INIT), initval.as_const());
+ c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
+ c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1);
- else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
+ else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) {
if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
else
c->setParam(ID(ENPOL), 2);
- c->setPort(ID(C), first_cell->getPort(ID(C)));
- c->setPort(ID(D), first_cell->getPort(ID(D)));
- c->setPort(ID(Q), last_cell->getPort(ID(Q)));
- c->setPort(ID(L), GetSize(ud.longest_chain)-1);
+ c->setPort(ID::C, first_cell->getPort(ID::C));
+ c->setPort(ID::D, first_cell->getPort(ID::D));
+ c->setPort(ID::Q, last_cell->getPort(ID::Q));
+ c->setPort(ID::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
- c->setPort(ID(E), State::S1);
+ c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(E), first_cell->getPort(ID(E)));
+ c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
- c->setPort(ID(E), first_cell->getPort(ID(CE)));
+ c->setPort(ID::E, first_cell->getPort(ID(CE)));
else
log_abort();
}
auto slice = i.second;
log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
- SigBit Q = cell->getPort(ID(Q))[slice];
+ SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire);
- auto it = Q.wire->attributes.find(ID(init));
+ auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset];
initval.append(i);
pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
- c->setParam(ID(DEPTH), GetSize(ud.chain));
- c->setParam(ID(INIT), initval.as_const());
+ c->setParam(ID::DEPTH, GetSize(ud.chain));
+ c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
clkpol = 1;
- else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
+ else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe)))
- clkpol = first_cell->getParam(ID(CLK_POLARITY));
+ clkpol = first_cell->getParam(ID::CLK_POLARITY);
else
log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
enpol = 0;
else if (first_cell->type.in(ID($dffe)))
- enpol = first_cell->getParam(ID(EN_POLARITY));
+ enpol = first_cell->getParam(ID::EN_POLARITY);
else
enpol = 2;
c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(C), first_cell->getPort(ID(C)));
+ c->setPort(ID::C, first_cell->getPort(ID::C));
else if (first_cell->type.in(ID($dff), ID($dffe)))
- c->setPort(ID(C), first_cell->getPort(ID(CLK)));
+ c->setPort(ID::C, first_cell->getPort(ID::CLK));
else
log_abort();
- c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]);
- c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
- c->setPort(ID(L), st.shiftx->getPort(ID(B)));
+ c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
+ c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
+ c->setPort(ID::L, st.shiftx->getPort(ID::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
- c->setPort(ID(E), State::S1);
+ c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
- c->setPort(ID(E), first_cell->getPort(ID(E)));
+ c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID($dffe)))
- c->setPort(ID(E), first_cell->getPort(ID(EN)));
+ c->setPort(ID::E, first_cell->getPort(ID::EN));
else
log_abort();
}
for (auto cell : mod->cells())
{
- if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal)
+ if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal)
+ if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
- if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) {
+ if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type == "$not" && cell->getPort(ID::Y) == signal) {
+ if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
- if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) {
+ if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool())
polarity = !polarity;
}
}
- if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) {
+ if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool())
polarity = !polarity;
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks())
- if (chunk.wire && chunk.wire->attributes.count("\\init")) {
- RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
+ if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
+ RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
}
for (auto wire : delete_initattr_wires)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
} ProcArstPass;
log_abort();
if (sync_low_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
}
if (sync_low_signals.size() > 0) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, mod->addWire(NEW_ID));
sync_high_signals.append(cell->getPort(ID::Y));
}
if (sync_high_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_high_signals);
cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
}
- RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
- inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
- inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
+ RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
+ inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
+ inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
inv_cell->setPort(ID::A, sync_value);
inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
- RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
- mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
+ RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
+ mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
mux_set_cell->setPort(ID::A, sig_sr_set);
mux_set_cell->setPort(ID::B, sync_value);
mux_set_cell->setPort(ID::S, sync_high_signals);
mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
- RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
- mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
+ RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
+ mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
mux_clr_cell->setPort(ID::A, sig_sr_clr);
mux_clr_cell->setPort(ID::B, sync_value_inv);
mux_clr_cell->setPort(ID::S, sync_high_signals);
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
- cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
- cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
- cell->setPort("\\D", sig_d);
- cell->setPort("\\Q", sig_q);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\SET", sig_sr_set);
- cell->setPort("\\CLR", sig_sr_clr);
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
+ cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::SET, sig_sr_set);
+ cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
- RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not");
- inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
- inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
+ RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not));
+ inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size());
+ inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size());
inv_set->setPort(ID::A, sig_set);
inv_set->setPort(ID::Y, sig_set_inv);
- RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
- mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux));
+ mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
mux_sr_set->setPort(ID::Y, sig_sr_set);
mux_sr_set->setPort(ID::S, set);
- RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
- mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux));
+ mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
mux_sr_clr->setPort(ID::Y, sig_sr_clr);
mux_sr_clr->setPort(ID::S, set);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
- cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
- cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
- cell->setPort("\\D", sig_in);
- cell->setPort("\\Q", sig_out);
- cell->setPort("\\CLK", clk);
- cell->setPort("\\SET", sig_sr_set);
- cell->setPort("\\CLR", sig_sr_clr);
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
+ cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
+ cell->setPort(ID::D, sig_in);
+ cell->setPort(ID::Q, sig_out);
+ cell->setPort(ID::CLK, clk);
+ cell->setPort(ID::SET, sig_sr_set);
+ cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? "$ff" : arst ? "$adff" : "$dff");
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
cell->attributes = proc->attributes;
- cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
+ cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
if (arst) {
- cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1);
- cell->parameters["\\ARST_VALUE"] = val_rst;
+ cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
+ cell->parameters[ID::ARST_VALUE] = val_rst;
}
if (!clk.empty()) {
- cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
+ cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
}
- cell->setPort("\\D", sig_in);
- cell->setPort("\\Q", sig_out);
+ cell->setPort(ID::D, sig_in);
+ cell->setPort(ID::Q, sig_out);
if (arst)
- cell->setPort("\\ARST", *arst);
+ cell->setPort(ID::ARST, *arst);
if (!clk.empty())
- cell->setPort("\\CLK", clk);
+ cell->setPort(ID::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
}
log_assert(inputs.size() == compare.size());
- RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
- cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
- cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);
- cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
- cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
- cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
+ cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
+ cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
+ cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
+ cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
+ cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, inputs);
cell->setPort(ID::B, compare);
cell->setPort(ID::Y, sync_level->signal);
{
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
auto sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++)
cell->setPort(ID::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
- cell->type = "$mux";
- cell->unsetParam("\\S_WIDTH");
+ cell->type = ID($mux);
+ cell->unsetParam(ID::S_WIDTH);
} else {
- cell->type = "$pmux";
- cell->setParam("\\S_WIDTH", GetSize(sig_new_s));
+ cell->type = ID($pmux);
+ cell->setParam(ID::S_WIDTH, GetSize(sig_new_s));
}
cell->setPort(ID::B, sig_new_b);
pool<Cell*> next_queue;
for (auto cell : queue) {
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
fixup_mux(cell);
for (auto bit : upstream_cell2net[cell])
for (auto cell : upstream_net2cell[bit])
continue;
}
- if (proc->get_bool_attribute(ID(always_ff)))
+ if (proc->get_bool_attribute(ID::always_ff))
log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n",
db.module->name.c_str(), proc->name.c_str());
int offset = 0;
for (auto chunk : nolatches_bits.first.chunks()) {
SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width);
- if (proc->get_bool_attribute(ID(always_latch)))
+ if (proc->get_bool_attribute(ID::always_latch))
log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
cell->set_src_attribute(src);
db.generated_dlatches.insert(cell);
- if (proc->get_bool_attribute(ID(always_comb)))
+ if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else
log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
Const value = valuesig.as_const();
- Const &wireinit = lhs_c.wire->attributes["\\init"];
+ Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx);
else
{
// create compare cell
- RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq");
+ RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
apply_attrs(eq_cell, sw, cs);
- eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
+ eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
- eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
- eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size());
- eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
+ eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
+ eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
eq_cell->setPort(ID::A, sig);
eq_cell->setPort(ID::B, comp);
ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
// reduce cmp vector to one logic signal
- RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
+ RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
apply_attrs(any_cell, sw, cs);
- any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
- any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
- any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
+ any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
+ any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
any_cell->setPort(ID::A, cmp_wire);
any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
// create the multiplexer itself
- RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
+ RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
apply_attrs(mux_cell, sw, cs);
- mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
+ mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
mux_cell->setPort(ID::A, else_signal);
mux_cell->setPort(ID::B, when_signal);
mux_cell->setPort(ID::S, ctrl_sig);
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
- last_mux_cell->type = "$pmux";
+ last_mux_cell->type = ID($pmux);
RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
new_s.append(ctrl_sig);
new_b.append(when_signal);
last_mux_cell->setPort(ID::B, new_b);
- last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort(ID::S).size();
+ last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
for (auto cell : module->cells())
{
- if (cell->type.in("$mux", "$pmux"))
+ if (cell->type.in(ID($mux), ID($pmux)))
{
- int width = cell->getParam("\\WIDTH").as_int();
- int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1;
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
{
log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
- int swidth = pmux->getParam("\\S_WIDTH").as_int();
+ int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1);
SigSpec sel = pmux->getPort(ID::S);
vector<Cell*> pmux_cells;
for (auto cell : module->selected_cells())
- if (cell->type == "$pmux")
+ if (cell->type == ID($pmux))
pmux_cells.push_back(cell);
for (auto cell : pmux_cells)
pool<SigBit> del_initbits;
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type.in("$adff"))
+ if (cell->type.in(ID($adff)))
{
- // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
- bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
- Const arst_val = cell->parameters["\\ARST_VALUE"];
+ // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool();
+ Const arst_val = cell->parameters[ID::ARST_VALUE];
- // SigSpec sig_clk = cell->getPort("\\CLK");
- SigSpec sig_arst = cell->getPort("\\ARST");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ // SigSpec sig_clk = cell->getPort(ID::CLK);
+ SigSpec sig_arst = cell->getPort(ID::ARST);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (arst_pol) {
module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
}
- cell->setPort("\\D", new_d);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\ARST");
- cell->unsetParam("\\ARST_POLARITY");
- cell->unsetParam("\\ARST_VALUE");
- cell->type = "$dff";
+ cell->setPort(ID::D, new_d);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::ARST);
+ cell->unsetParam(ID::ARST_POLARITY);
+ cell->unsetParam(ID::ARST_VALUE);
+ cell->type = ID($dff);
continue;
}
- if (cell->type.in("$dffsr"))
+ if (cell->type.in(ID($dffsr)))
{
- // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
- bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool();
- bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool();
+ // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool();
+ bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool();
- // SigSpec sig_clk = cell->getPort("\\CLK");
- SigSpec sig_set = cell->getPort("\\SET");
- SigSpec sig_clr = cell->getPort("\\CLR");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ // SigSpec sig_clk = cell->getPort(ID::CLK);
+ SigSpec sig_set = cell->getPort(ID::SET);
+ SigSpec sig_clr = cell->getPort(ID::CLR);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (!set_pol)
sig_set = module->Not(NEW_ID, sig_set);
tmp = module->Or(NEW_ID, new_q, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
- cell->setPort("\\D", new_d);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\SET");
- cell->unsetPort("\\CLR");
- cell->unsetParam("\\SET_POLARITY");
- cell->unsetParam("\\CLR_POLARITY");
- cell->type = "$dff";
+ cell->setPort(ID::D, new_d);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
+ cell->type = ID($dff);
continue;
}
- if (cell->type.in("$dlatch"))
+ if (cell->type.in(ID($dlatch)))
{
- bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
+ bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool();
- SigSpec sig_en = cell->getPort("\\EN");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_en = cell->getPort(ID::EN);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
}
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
- new_q->attributes["\\init"] = init_val;
+ new_q->attributes[ID::init] = init_val;
if (en_pol) {
module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
}
- cell->setPort("\\D", sig_q);
- cell->setPort("\\Q", new_q);
- cell->unsetPort("\\EN");
- cell->unsetParam("\\EN_POLARITY");
- cell->type = "$ff";
+ cell->setPort(ID::D, sig_q);
+ cell->setPort(ID::Q, new_q);
+ cell->unsetPort(ID::EN);
+ cell->unsetParam(ID::EN_POLARITY);
+ cell->type = ID($ff);
continue;
}
}
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
delete_initattr = false;
if (delete_initattr)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at("\\init") = initval;
+ wire->attributes.at(ID::init) = initval;
}
}
}
pool<SigBit> del_initbits;
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
for (auto cell : vector<Cell*>(module->selected_cells()))
{
- if (cell->type.in("$mem"))
+ if (cell->type.in(ID($mem)))
{
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
- int rd_ports = cell->getParam("\\RD_PORTS").as_int();
- int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
+ int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
for (int i = 0; i < rd_ports; i++) {
- if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
}
- Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE");
- Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY");
+ Const wr_clk_en_param = cell->getParam(ID::WR_CLK_ENABLE);
+ Const wr_clk_pol_param = cell->getParam(ID::WR_CLK_POLARITY);
- SigSpec wr_clk_port = cell->getPort("\\WR_CLK");
- SigSpec wr_en_port = cell->getPort("\\WR_EN");
- SigSpec wr_addr_port = cell->getPort("\\WR_ADDR");
- SigSpec wr_data_port = cell->getPort("\\WR_DATA");
+ SigSpec wr_clk_port = cell->getPort(ID::WR_CLK);
+ SigSpec wr_en_port = cell->getPort(ID::WR_EN);
+ SigSpec wr_addr_port = cell->getPort(ID::WR_ADDR);
+ SigSpec wr_data_port = cell->getPort(ID::WR_DATA);
for (int wport = 0; wport < wr_ports; wport++)
{
log_signal(addr), log_signal(data));
Wire *past_clk = module->addWire(NEW_ID);
- past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+ past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
module->addFf(NEW_ID, clk, past_clk);
SigSpec clock_edge_pattern;
wr_clk_pol_param[wport] = State::S0;
}
- cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param);
- cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param);
+ cell->setParam(ID::WR_CLK_ENABLE, wr_clk_en_param);
+ cell->setParam(ID::WR_CLK_POLARITY, wr_clk_pol_param);
- cell->setPort("\\WR_CLK", wr_clk_port);
- cell->setPort("\\WR_EN", wr_en_port);
- cell->setPort("\\WR_ADDR", wr_addr_port);
- cell->setPort("\\WR_DATA", wr_data_port);
+ cell->setPort(ID::WR_CLK, wr_clk_port);
+ cell->setPort(ID::WR_EN, wr_en_port);
+ cell->setPort(ID::WR_ADDR, wr_addr_port);
+ cell->setPort(ID::WR_DATA, wr_data_port);
}
- if (cell->type.in("$dlatch", "$dlatchsr"))
+ if (cell->type.in(ID($dlatch), ID($dlatchsr)))
{
- bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
+ bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
- SigSpec sig_en = cell->getPort("\\EN");
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_en = cell->getPort(ID::EN);
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_q, past_q);
- if (cell->type == "$dlatch")
+ if (cell->type == ID($dlatch))
{
if (enpol)
module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
else
t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
- SigSpec s = cell->getPort("\\SET");
- if (!cell->parameters["\\SET_POLARITY"].as_bool())
+ SigSpec s = cell->getPort(ID::SET);
+ if (!cell->parameters[ID::SET_POLARITY].as_bool())
s = module->Not(NEW_ID, s);
t = module->Or(NEW_ID, t, s);
- SigSpec c = cell->getPort("\\CLR");
- if (cell->parameters["\\CLR_POLARITY"].as_bool())
+ SigSpec c = cell->getPort(ID::CLR);
+ if (cell->parameters[ID::CLR_POLARITY].as_bool())
c = module->Not(NEW_ID, c);
module->addAnd(NEW_ID, t, c, sig_q);
}
}
if (assign_initval)
- past_q->attributes["\\init"] = initval;
+ past_q->attributes[ID::init] = initval;
module->remove(cell);
continue;
}
- bool word_dff = cell->type.in("$dff", "$adff", "$dffsr");
+ bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr));
if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
bool clkpol;
SigSpec clk;
if (word_dff) {
- clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
- clk = cell->getPort("\\CLK");
+ clkpol = cell->parameters[ID::CLK_POLARITY].as_bool();
+ clk = cell->getPort(ID::CLK);
}
else {
if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
clkpol = cell->type[8] == 'P';
else log_abort();
- clk = cell->getPort("\\C");
+ clk = cell->getPort(ID::C);
}
Wire *past_clk = module->addWire(NEW_ID);
- past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
+ past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
if (word_dff)
module->addFf(NEW_ID, clk, past_clk);
else
module->addFfGate(NEW_ID, clk, past_clk);
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
module->addFfGate(NEW_ID, sig_q, past_q);
}
- if (cell->type == "$adff")
+ if (cell->type == ID($adff))
{
- SigSpec arst = cell->getPort("\\ARST");
+ SigSpec arst = cell->getPort(ID::ARST);
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
- Const rstval = cell->parameters["\\ARST_VALUE"];
+ Const rstval = cell->parameters[ID::ARST_VALUE];
Wire *past_arst = module->addWire(NEW_ID);
module->addFf(NEW_ID, arst, past_arst);
- if (cell->parameters["\\ARST_POLARITY"].as_bool())
+ if (cell->parameters[ID::ARST_POLARITY].as_bool())
arst = module->LogicOr(NEW_ID, arst, past_arst);
else
arst = module->LogicAnd(NEW_ID, arst, past_arst);
- if (cell->parameters["\\ARST_POLARITY"].as_bool())
+ if (cell->parameters[ID::ARST_POLARITY].as_bool())
module->addMux(NEW_ID, qval, rstval, arst, sig_q);
else
module->addMux(NEW_ID, rstval, qval, arst, sig_q);
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
{
- SigSpec arst = cell->getPort("\\R");
+ SigSpec arst = cell->getPort(ID::R);
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigBit rstval = (cell->type[8] == '1');
module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
}
else
- if (cell->type == "$dffsr")
+ if (cell->type == ID($dffsr))
{
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
- SigSpec setval = cell->getPort("\\SET");
- SigSpec clrval = cell->getPort("\\CLR");
+ SigSpec setval = cell->getPort(ID::SET);
+ SigSpec clrval = cell->getPort(ID::CLR);
- if (!cell->parameters["\\SET_POLARITY"].as_bool())
+ if (!cell->parameters[ID::SET_POLARITY].as_bool())
setval = module->Not(NEW_ID, setval);
- if (cell->parameters["\\CLR_POLARITY"].as_bool())
+ if (cell->parameters[ID::CLR_POLARITY].as_bool())
clrval = module->Not(NEW_ID, clrval);
qval = module->Or(NEW_ID, qval, setval);
{
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigSpec setval = cell->getPort(ID::S);
- SigSpec clrval = cell->getPort("\\R");
+ SigSpec clrval = cell->getPort(ID::R);
if (cell->type[9] != 'P')
setval = module->Not(NEW_ID, setval);
qval = module->OrGate(NEW_ID, qval, setval);
module->addAndGate(NEW_ID, qval, clrval, sig_q);
}
- else if (cell->type == "$dff")
+ else if (cell->type == ID($dff))
{
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
}
}
if (assign_initval) {
- past_d->attributes["\\init"] = initval;
- past_q->attributes["\\init"] = initval;
+ past_d->attributes[ID::init] = initval;
+ past_q->attributes[ID::init] = initval;
}
module->remove(cell);
}
for (auto wire : module->wires())
- if (wire->attributes.count("\\init") > 0)
+ if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
delete_initattr = false;
if (delete_initattr)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
else
- wire->attributes.at("\\init") = initval;
+ wire->attributes.at(ID::init) = initval;
}
}
pool<SigBit> cutpoint_bits;
for (auto cell : module->selected_cells()) {
- if (cell->type == "$anyseq")
+ if (cell->type == ID($anyseq))
continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) {
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
- std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y"));
+ std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y)));
std::vector<bool> y_values;
if (model_undef) {
- std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y"));
+ std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y)));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
}
}
}
- if (module->wire("\\y") == nullptr)
+ if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", log_id(module->name));
- RTLIL::SigSpec sig(module->wire("\\y"));
+ RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) {
SigPool dffsignals;
for (auto cell : module->cells()) {
- if (ct.cell_known(cell->type) && cell->hasPort("\\Q"))
- dffsignals.add(sigmap(cell->getPort("\\Q")));
+ if (ct.cell_known(cell->type) && cell->hasPort(ID::Q))
+ dffsignals.add(sigmap(cell->getPort(ID::Q)));
}
for (auto w : module->wires()) {
info.arst_value = RTLIL::State::Sm;
info.cell = cell;
- if (info.cell->type == "$dff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
- info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
- std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
+ if (info.cell->type == ID($dff)) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+ info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
bit_info[sig_q.at(i)] = info;
continue;
}
- if (info.cell->type == "$adff") {
- info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
- info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
- info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
- info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
- std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
- std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
+ if (info.cell->type == ID($adff)) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit();
+ info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
+ info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
+ std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
+ std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).bits;
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
info.arst_value = arst_value.at(i);
continue;
}
- if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
- info.clk_polarity = info.cell->type == "$_DFF_P_";
- info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
- bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+ if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+ info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+ info.clk_polarity = info.cell->type == ID($_DFF_P_);
+ info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+ bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
continue;
}
if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) {
- info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
- info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
+ info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
+ info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit();
info.clk_polarity = info.cell->type[6] == 'P';
info.arst_polarity = info.cell->type[7] == 'P';
info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
- info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
- bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
+ info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
+ bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
continue;
}
}
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cell(cell_name);
- std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
- cell->setPort("\\Q", cell_q_bits);
+ cell->setPort(ID::Q, cell_q_bits);
}
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
- RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
- c->parameters["\\A_SIGNED"] = 0;
- c->parameters["\\A_WIDTH"] = 1;
- c->parameters["\\Y_WIDTH"] = 1;
+ RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+ c->parameters[ID::A_SIGNED] = 0;
+ c->parameters[ID::A_WIDTH] = 1;
+ c->parameters[ID::Y_WIDTH] = 1;
c->setPort(ID::A, info.sig_clk);
c->setPort(ID::Y, wire_c);
}
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
- RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
- c->parameters["\\A_SIGNED"] = 0;
- c->parameters["\\A_WIDTH"] = 1;
- c->parameters["\\Y_WIDTH"] = 1;
+ RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
+ c->parameters[ID::A_SIGNED] = 0;
+ c->parameters[ID::A_WIDTH] = 1;
+ c->parameters[ID::Y_WIDTH] = 1;
c->setPort(ID::A, info.sig_arst);
c->setPort(ID::Y, wire_r);
}
FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
opts(opts), design(design), original(design->module(orig_type)),
- orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
+ orig_type(orig_type), combined_type(stringf("$fmcombine%s", orig_type.c_str()))
{
}
for (auto cell : original->cells()) {
if (design->module(cell->type) == nullptr) {
- if (opts.anyeq && cell->type.in("$anyseq", "$anyconst")) {
+ if (opts.anyeq && cell->type.in(ID($anyseq), ID($anyconst))) {
Cell *gold = import_prim_cell(cell, "_gold");
for (auto &conn : cell->connections())
module->connect(import_sig(conn.second, "_gate"), gold->getPort(conn.first));
Cell *gold = import_prim_cell(cell, "_gold");
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
- if (cell->type.in("$ff", "$dff", "$dffe",
- "$dffsr", "$adff", "$dlatch", "$dlatchsr")) {
- SigSpec gold_q = gold->getPort("\\Q");
- SigSpec gate_q = gate->getPort("\\Q");
+ if (cell->type.in(ID($ff), ID($dff), ID($dffe),
+ ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) {
+ SigSpec gold_q = gold->getPort(ID::Q);
+ SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);
SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
module->addAssume(NEW_ID, eq, en);
SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
Wire *outwire = module->addWire(NEW_ID);
- outwire->attributes[ID(init)] = i > 0 ? State::S0 : State::S1;
+ outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1;
if (clksig.empty())
module->addFf(NEW_ID, insig, outwire);
if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
{
Wire *ffwire = module->addWire(NEW_ID);
- ffwire->attributes[ID(init)] = State::S0;
+ ffwire->attributes[ID::init] = State::S0;
SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);
if (clksig.empty())
{
inv_sig = module->addWire(NEW_ID);
- RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_NOT_");
+ RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
inv_cell->setPort(ID::A, grp[0].bit);
inv_cell->setPort(ID::Y, inv_sig);
}
miter_module->name = miter_name;
design->add(miter_module);
- RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
- RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
+ RTLIL::Cell *gold_cell = miter_module->addCell(ID(gold), gold_name);
+ RTLIL::Cell *gate_cell = miter_module->addCell(ID(gate), gate_name);
RTLIL::SigSpec all_conditions;
{
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
for (int i = 0; i < w_gold->width; i++) {
- RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
- eqx_cell->parameters["\\A_WIDTH"] = 1;
- eqx_cell->parameters["\\B_WIDTH"] = 1;
- eqx_cell->parameters["\\Y_WIDTH"] = 1;
- eqx_cell->parameters["\\A_SIGNED"] = 0;
- eqx_cell->parameters["\\B_SIGNED"] = 0;
+ RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eqx_cell->parameters[ID::A_WIDTH] = 1;
+ eqx_cell->parameters[ID::B_WIDTH] = 1;
+ eqx_cell->parameters[ID::Y_WIDTH] = 1;
+ eqx_cell->parameters[ID::A_SIGNED] = 0;
+ eqx_cell->parameters[ID::B_SIGNED] = 0;
eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
eqx_cell->setPort(ID::B, RTLIL::State::Sx);
eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
- RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
- or_gold_cell->parameters["\\A_WIDTH"] = w_gold->width;
- or_gold_cell->parameters["\\B_WIDTH"] = w_gold->width;
- or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
- or_gold_cell->parameters["\\A_SIGNED"] = 0;
- or_gold_cell->parameters["\\B_SIGNED"] = 0;
+ RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or));
+ or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width;
+ or_gold_cell->parameters[ID::A_SIGNED] = 0;
+ or_gold_cell->parameters[ID::B_SIGNED] = 0;
or_gold_cell->setPort(ID::A, w_gold);
or_gold_cell->setPort(ID::B, gold_x);
or_gold_cell->setPort(ID::Y, gold_masked);
- RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
- or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
- or_gate_cell->parameters["\\B_WIDTH"] = w_gate->width;
- or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
- or_gate_cell->parameters["\\A_SIGNED"] = 0;
- or_gate_cell->parameters["\\B_SIGNED"] = 0;
+ RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or));
+ or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width;
+ or_gate_cell->parameters[ID::A_SIGNED] = 0;
+ or_gate_cell->parameters[ID::B_SIGNED] = 0;
or_gate_cell->setPort(ID::A, w_gate);
or_gate_cell->setPort(ID::B, gold_x);
or_gate_cell->setPort(ID::Y, gate_masked);
- RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
- eq_cell->parameters["\\Y_WIDTH"] = 1;
- eq_cell->parameters["\\A_SIGNED"] = 0;
- eq_cell->parameters["\\B_SIGNED"] = 0;
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ eq_cell->parameters[ID::Y_WIDTH] = 1;
+ eq_cell->parameters[ID::A_SIGNED] = 0;
+ eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, gold_masked);
eq_cell->setPort(ID::B, gate_masked);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
}
else
{
- RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
- eq_cell->parameters["\\Y_WIDTH"] = 1;
- eq_cell->parameters["\\A_SIGNED"] = 0;
- eq_cell->parameters["\\B_SIGNED"] = 0;
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
+ eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
+ eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
+ eq_cell->parameters[ID::Y_WIDTH] = 1;
+ eq_cell->parameters[ID::A_SIGNED] = 0;
+ eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, w_gold);
eq_cell->setPort(ID::B, w_gate);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
}
if (all_conditions.size() != 1) {
- RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
- reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- reduce_cell->parameters["\\Y_WIDTH"] = 1;
- reduce_cell->parameters["\\A_SIGNED"] = 0;
+ RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and));
+ reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ reduce_cell->parameters[ID::Y_WIDTH] = 1;
+ reduce_cell->parameters[ID::A_SIGNED] = 0;
reduce_cell->setPort(ID::A, all_conditions);
reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
all_conditions = reduce_cell->getPort(ID::Y);
}
if (flag_make_assert) {
- RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
+ RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert));
assert_cell->setPort(ID::A, all_conditions);
- assert_cell->setPort("\\EN", State::S1);
+ assert_cell->setPort(ID::EN, State::S1);
}
- RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
+ RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger));
w_trigger->port_output = true;
- RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
- not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
- not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
- not_cell->parameters["\\A_SIGNED"] = 0;
+ RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not));
+ not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
+ not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
+ not_cell->parameters[ID::A_SIGNED] = 0;
not_cell->setPort(ID::A, all_conditions);
not_cell->setPort(ID::Y, w_trigger);
for (auto wire : module->wires())
wire->port_output = false;
- Wire *trigger = module->addWire("\\trigger");
+ Wire *trigger = module->addWire(ID(trigger));
trigger->port_output = true;
module->fixup_ports();
vector<Cell*> cell_list = module->cells();
for (auto cell : cell_list)
{
- if (!cell->type.in("$assert", "$assume"))
+ if (!cell->type.in(ID($assert), ID($assume)))
continue;
SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
- SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
+ SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1);
- if (cell->type == "$assert") {
+ if (cell->type == ID($assert)) {
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
} else {
assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
else
{
Wire *assume_q = module->addWire(NEW_ID);
- assume_q->attributes["\\init"] = State::S0;
+ assume_q->attributes[ID::init] = State::S0;
assume_signals.append(assume_q);
SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
for (auto &it : module->wires_)
{
- if (it.second->attributes.count("\\init") == 0)
+ if (it.second->attributes.count(ID::init) == 0)
continue;
RTLIL::SigSpec lhs = sigmap(it.second);
- RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
+ RTLIL::SigSpec rhs = it.second->attributes.at(ID::init);
log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits;
} else {
for (auto &d : drivers)
for (auto &p : d->connections()) {
- if (d->type == "$dff" && p.first == "\\CLK")
+ if (d->type == ID($dff) && p.first == ID::CLK)
continue;
- if (d->type.begins_with("$_DFF_") && p.first == "\\C")
+ if (d->type.begins_with("$_DFF_") && p.first == ID::C)
continue;
queued_signals.add(handled_signals.remove(sigmap(p.second)));
}
if (show_regs) {
pool<Wire*> reg_wires;
for (auto cell : module->cells()) {
- if (cell->type == "$dff" || cell->type.begins_with("$_DFF_"))
- for (auto bit : cell->getPort("\\Q"))
+ if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
+ for (auto bit : cell->getPort(ID::Q))
if (bit.wire)
reg_wires.insert(bit.wire);
}
}
}
- if (wire->attributes.count("\\init")) {
- Const initval = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) {
state_nets[sig[i]] = initval[i];
upd_cells[bit].insert(cell);
}
- if (cell->type.in("$dff")) {
+ if (cell->type.in(ID($dff))) {
ff_state_t ff;
ff.past_clock = State::Sx;
- ff.past_d = Const(State::Sx, cell->getParam("\\WIDTH").as_int());
+ ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
ff_database[cell] = ff;
}
- if (cell->type == "$mem")
+ if (cell->type == ID($mem))
{
mem_state_t mem;
- mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort("\\WR_CLK")));
- mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort("\\WR_EN")));
- mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort("\\WR_ADDR")));
- mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort("\\WR_DATA")));
+ mem.past_wr_clk = Const(State::Sx, GetSize(cell->getPort(ID::WR_CLK)));
+ mem.past_wr_en = Const(State::Sx, GetSize(cell->getPort(ID::WR_EN)));
+ mem.past_wr_addr = Const(State::Sx, GetSize(cell->getPort(ID::WR_ADDR)));
+ mem.past_wr_data = Const(State::Sx, GetSize(cell->getPort(ID::WR_DATA)));
- mem.data = cell->getParam("\\INIT");
- int sz = cell->getParam("\\SIZE").as_int() * cell->getParam("\\WIDTH").as_int();
+ mem.data = cell->getParam(ID::INIT);
+ int sz = cell->getParam(ID::SIZE).as_int() * cell->getParam(ID::WIDTH).as_int();
if (GetSize(mem.data) > sz)
mem.data.bits.resize(sz);
mem_database[cell] = mem;
}
- if (cell->type.in("$assert", "$cover", "$assume")) {
+ if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
formal_database.insert(cell);
}
}
ff_state_t &ff = it.second;
zinit(ff.past_d);
- SigSpec qsig = cell->getPort("\\Q");
+ SigSpec qsig = cell->getPort(ID::Q);
Const qdata = get_state(qsig);
zinit(qdata);
set_state(qsig, qdata);
{
mem_state_t &mem = mem_database.at(cell);
- int num_rd_ports = cell->getParam("\\RD_PORTS").as_int();
+ int num_rd_ports = cell->getParam(ID::RD_PORTS).as_int();
- int size = cell->getParam("\\SIZE").as_int();
- int offset = cell->getParam("\\OFFSET").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int size = cell->getParam(ID::SIZE).as_int();
+ int offset = cell->getParam(ID::OFFSET).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- if (cell->getParam("\\RD_CLK_ENABLE").as_bool())
+ if (cell->getParam(ID::RD_CLK_ENABLE).as_bool())
log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(cell));
- SigSpec rd_addr_sig = cell->getPort("\\RD_ADDR");
- SigSpec rd_data_sig = cell->getPort("\\RD_DATA");
+ SigSpec rd_addr_sig = cell->getPort(ID::RD_ADDR);
+ SigSpec rd_data_sig = cell->getPort(ID::RD_DATA);
for (int port_idx = 0; port_idx < num_rd_ports; port_idx++)
{
has_a = cell->hasPort(ID::A);
has_b = cell->hasPort(ID::B);
- has_c = cell->hasPort("\\C");
- has_d = cell->hasPort("\\D");
+ has_c = cell->hasPort(ID::C);
+ has_d = cell->hasPort(ID::D);
has_s = cell->hasPort(ID::S);
has_y = cell->hasPort(ID::Y);
if (has_a) sig_a = cell->getPort(ID::A);
if (has_b) sig_b = cell->getPort(ID::B);
- if (has_c) sig_c = cell->getPort("\\C");
- if (has_d) sig_d = cell->getPort("\\D");
+ if (has_c) sig_c = cell->getPort(ID::C);
+ if (has_d) sig_d = cell->getPort(ID::D);
if (has_s) sig_s = cell->getPort(ID::S);
if (has_y) sig_y = cell->getPort(ID::Y);
Cell *cell = it.first;
ff_state_t &ff = it.second;
- if (cell->type.in("$dff"))
+ if (cell->type.in(ID($dff)))
{
- bool clkpol = cell->getParam("\\CLK_POLARITY").as_bool();
- State current_clock = get_state(cell->getPort("\\CLK"))[0];
+ bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
+ State current_clock = get_state(cell->getPort(ID::CLK))[0];
if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
(ff.past_clock == State::S0 || current_clock != State::S0))
continue;
- if (set_state(cell->getPort("\\Q"), ff.past_d))
+ if (set_state(cell->getPort(ID::Q), ff.past_d))
did_something = true;
}
}
Cell *cell = it.first;
mem_state_t &mem = it.second;
- int num_wr_ports = cell->getParam("\\WR_PORTS").as_int();
+ int num_wr_ports = cell->getParam(ID::WR_PORTS).as_int();
- int size = cell->getParam("\\SIZE").as_int();
- int offset = cell->getParam("\\OFFSET").as_int();
- int abits = cell->getParam("\\ABITS").as_int();
- int width = cell->getParam("\\WIDTH").as_int();
+ int size = cell->getParam(ID::SIZE).as_int();
+ int offset = cell->getParam(ID::OFFSET).as_int();
+ int abits = cell->getParam(ID::ABITS).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
- Const wr_clk_enable = cell->getParam("\\WR_CLK_ENABLE");
- Const wr_clk_polarity = cell->getParam("\\WR_CLK_POLARITY");
- Const current_wr_clk = get_state(cell->getPort("\\WR_CLK"));
+ Const wr_clk_enable = cell->getParam(ID::WR_CLK_ENABLE);
+ Const wr_clk_polarity = cell->getParam(ID::WR_CLK_POLARITY);
+ Const current_wr_clk = get_state(cell->getPort(ID::WR_CLK));
for (int port_idx = 0; port_idx < num_wr_ports; port_idx++)
{
if (wr_clk_enable[port_idx] == State::S0)
{
- addr = get_state(cell->getPort("\\WR_ADDR").extract(port_idx*abits, abits));
- data = get_state(cell->getPort("\\WR_DATA").extract(port_idx*width, width));
- enable = get_state(cell->getPort("\\WR_EN").extract(port_idx*width, width));
+ addr = get_state(cell->getPort(ID::WR_ADDR).extract(port_idx*abits, abits));
+ data = get_state(cell->getPort(ID::WR_DATA).extract(port_idx*width, width));
+ enable = get_state(cell->getPort(ID::WR_EN).extract(port_idx*width, width));
}
else
{
Cell *cell = it.first;
ff_state_t &ff = it.second;
- if (cell->type.in("$dff")) {
- ff.past_clock = get_state(cell->getPort("\\CLK"))[0];
- ff.past_d = get_state(cell->getPort("\\D"));
+ if (cell->type.in(ID($dff))) {
+ ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
+ ff.past_d = get_state(cell->getPort(ID::D));
}
}
Cell *cell = it.first;
mem_state_t &mem = it.second;
- mem.past_wr_clk = get_state(cell->getPort("\\WR_CLK"));
- mem.past_wr_en = get_state(cell->getPort("\\WR_EN"));
- mem.past_wr_addr = get_state(cell->getPort("\\WR_ADDR"));
- mem.past_wr_data = get_state(cell->getPort("\\WR_DATA"));
+ mem.past_wr_clk = get_state(cell->getPort(ID::WR_CLK));
+ mem.past_wr_en = get_state(cell->getPort(ID::WR_EN));
+ mem.past_wr_addr = get_state(cell->getPort(ID::WR_ADDR));
+ mem.past_wr_data = get_state(cell->getPort(ID::WR_DATA));
}
for (auto cell : formal_database)
label = cell->attributes.at(ID::src).decode_string();
State a = get_state(cell->getPort(ID::A))[0];
- State en = get_state(cell->getPort("\\EN"))[0];
+ State en = get_state(cell->getPort(ID::EN))[0];
- if (cell->type == "$cover" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($cover) && en == State::S1 && a != State::S1)
log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
- if (cell->type == "$assume" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
- if (cell->type == "$assert" && en == State::S1 && a != State::S1)
+ if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
}
wbmods.insert(module);
for (auto wire : module->wires())
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
for (auto &it : ff_database)
{
Cell *cell = it.first;
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_q = cell->getPort(ID::Q);
Const initval = get_state(sig_q);
for (int i = 0; i < GetSize(sig_q); i++)
{
Wire *w = sig_q[i].wire;
- if (w->attributes.count("\\init") == 0)
- w->attributes["\\init"] = Const(State::Sx, GetSize(w));
+ if (w->attributes.count(ID::init) == 0)
+ w->attributes[ID::init] = Const(State::Sx, GetSize(w));
- w->attributes["\\init"][sig_q[i].offset] = initval[i];
+ w->attributes[ID::init][sig_q[i].offset] = initval[i];
}
}
initval.bits.pop_back();
}
- cell->setParam("\\INIT", initval);
+ cell->setParam(ID::INIT, initval);
}
for (auto it : children)
{
if (clk_polarity != (cell->type == ID($_DFF_P_)))
return;
- if (clk_sig != assign_map(cell->getPort(ID(C))))
+ if (clk_sig != assign_map(cell->getPort(ID::C)))
return;
if (GetSize(en_sig) != 0)
return;
return;
if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
return;
- if (clk_sig != assign_map(cell->getPort(ID(C))))
+ if (clk_sig != assign_map(cell->getPort(ID::C)))
return;
- if (en_sig != assign_map(cell->getPort(ID(E))))
+ if (en_sig != assign_map(cell->getPort(ID::E)))
return;
goto matching_dff;
}
if (0) {
matching_dff:
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
if (keepff)
for (auto &c : sig_q.chunks())
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
- RTLIL::SigSpec sig_s = cell->getPort(ID(S));
+ RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
- RTLIL::SigSpec sig_c = cell->getPort(ID(C));
+ RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
- RTLIL::SigSpec sig_c = cell->getPort(ID(C));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
+ RTLIL::SigSpec sig_c = cell->getPort(ID::C);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
RTLIL::Wire *w = it.second;
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
- if (orig_wire != nullptr && orig_wire->attributes.count(ID(src)))
- wire->attributes[ID(src)] = orig_wire->attributes[ID(src)];
- if (markgroups) wire->attributes[ID(abcgroup)] = map_autoidx;
+ if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
+ wire->attributes[ID::src] = orig_wire->attributes[ID::src];
+ if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
design->select(module, wire);
}
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
+ cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
- cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
+ cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
+ cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
+ cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
- cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
- cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
- cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
- cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
- cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
- cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
+ cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
+ cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)]));
+ cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)]));
+ cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)]));
+ cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)]));
+ cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
+ cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
+ cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
- cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
- cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
- cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
- cell->setPort(ID(I), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(I)).as_wire()->name)]));
- cell->setPort(ID(J), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(J)).as_wire()->name)]));
- cell->setPort(ID(K), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(K)).as_wire()->name)]));
- cell->setPort(ID(L), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(L)).as_wire()->name)]));
- cell->setPort(ID(M), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(M)).as_wire()->name)]));
- cell->setPort(ID(N), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(N)).as_wire()->name)]));
- cell->setPort(ID(O), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(O)).as_wire()->name)]));
- cell->setPort(ID(P), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(P)).as_wire()->name)]));
- cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
- cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
- cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
- cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)]));
+ cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
+ cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)]));
+ cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)]));
+ cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)]));
+ cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)]));
+ cell->setPort(ID::I, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::I).as_wire()->name)]));
+ cell->setPort(ID::J, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::J).as_wire()->name)]));
+ cell->setPort(ID::K, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::K).as_wire()->name)]));
+ cell->setPort(ID::L, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::L).as_wire()->name)]));
+ cell->setPort(ID::M, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::M).as_wire()->name)]));
+ cell->setPort(ID::N, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::N).as_wire()->name)]));
+ cell->setPort(ID::O, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::O).as_wire()->name)]));
+ cell->setPort(ID::P, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::P).as_wire()->name)]));
+ cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
+ cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
+ cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)]));
+ cell->setPort(ID::V, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::V).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
+ cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
- cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
+ cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), en_sig);
+ cell->setPort(ID::E, en_sig);
}
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
- cell->setPort(ID(C), clk_sig);
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
+ cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)]));
+ cell->setPort(ID::C, clk_sig);
design->select(module, cell);
continue;
}
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), en_sig);
+ cell->setPort(ID::E, en_sig);
}
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
- cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
- cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
- cell->setPort(ID(C), clk_sig);
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
+ cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
+ cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)]));
+ cell->setPort(ID::C, clk_sig);
design->select(module, cell);
continue;
}
- if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
+ if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)];
SigSpec my_y = module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)];
module->connect(my_y, my_a);
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
- if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
+ if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->parameters = c->parameters;
for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;
if (recover_init)
for (auto wire : mapped_mod->wires()) {
- if (wire->attributes.count(ID(init))) {
+ if (wire->attributes.count(ID::init)) {
Wire *w = module->wires_[remap_name(wire->name)];
- log_assert(w->attributes.count(ID(init)) == 0);
- w->attributes[ID(init)] = wire->attributes.at(ID(init));
+ log_assert(w->attributes.count(ID::init) == 0);
+ w->attributes[ID::init] = wire->attributes.at(ID::init);
}
}
signal_init.clear();
for (Wire *wire : mod->wires())
- if (wire->attributes.count(ID(init))) {
+ if (wire->attributes.count(ID::init)) {
SigSpec initsig = assign_map(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
switch (initval[i]) {
case State::S0:
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
- key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
+ key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID::C)), true, RTLIL::SigSpec());
}
else
if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
- key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
+ key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID::C)), this_en_pol, assign_map(cell->getPort(ID::E)));
}
else
continue;
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
}
- log_assert(!mod->attributes.count(ID(abc9_box_id)));
+ log_assert(!mod->attributes.count(ID::abc9_box_id));
log_push();
active_design->selection().select(mod);
if (m->name.begins_with("$paramod"))
continue;
- auto flop = m->get_bool_attribute(ID(abc9_flop));
- auto it = m->attributes.find(ID(abc9_box_id));
+ auto flop = m->get_bool_attribute(ID::abc9_flop);
+ auto it = m->attributes.find(ID::abc9_box_id);
if (!flop) {
if (it == m->attributes.end())
continue;
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) {
if (carry_in != IdString())
log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
// write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
- auto it = cell->attributes.find(ID(abc9_scc_id));
+ auto it = cell->attributes.find(ID::abc9_scc_id);
if (it == cell->attributes.end())
continue;
auto id = it->second;
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
- w->set_bool_attribute(ID(abc9_scc));
+ w->set_bool_attribute(ID::abc9_scc);
module->connect(w, c.second);
c.second = w;
}
dict<clkdomain_t, int> clk_to_mergeability;
for (auto cell : module->cells()) {
- if (cell->type != "$__ABC9_FF_")
+ if (cell->type != ID($__ABC9_FF_))
continue;
Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
clkdomain_t key(abc9_clock);
auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
- auto r2 = cell->attributes.insert(ID(abc9_mergeability));;
+ auto r2 = cell->attributes.insert(ID::abc9_mergeability);
log_assert(r2.second);
r2.first->second = r.first->second;
}
dict<SigSpec, SigSpec> replace;
for (auto cell : holes_module->cells().to_vector()) {
- if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
+ if (!cell->type.in(ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1), ID($_DFF_PP0_), ID($_DFF_PP1_)))
continue;
- SigBit D = cell->getPort("\\D");
- SigBit Q = cell->getPort("\\Q");
+ SigBit D = cell->getPort(ID::D);
+ SigBit Q = cell->getPort(ID::Q);
// Emulate async control embedded inside $_DFF_* cell with mux in front of D
- if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
- D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
- else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
- D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
- else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
- D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
- else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
- D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
+ if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_PN0_)))
+ D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort(ID::R));
+ else if (cell->type.in(ID($_DFF_NN1_), ID($_DFF_PN1_)))
+ D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort(ID::R));
+ else if (cell->type.in(ID($_DFF_NP0_), ID($_DFF_PP0_)))
+ D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort(ID::R));
+ else if (cell->type.in(ID($_DFF_NP1_), ID($_DFF_PP1_)))
+ D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort(ID::R));
// Remove the $_DFF_* cell from what needs to be a combinatorial box
holes_module->remove(cell);
Wire *port;
dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
- if (cell->type == "$__ABC9_FF_")
+ if (cell->type == ID($__ABC9_FF_))
continue;
if (cell->has_keep_attr())
continue;
auto inst_module = module->design->module(cell->type);
- bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+ bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
- if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
+ if ((inst_module && inst_module->get_bool_attribute(ID::abc9_box)) || abc9_flop) {
auto r = box_ports.insert(cell->type);
if (r.second) {
// Make carry in the last PI, and carry out the last PO
for (const auto &port_name : inst_module->ports) {
auto w = inst_module->wire(port_name);
log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
- holes_module->set_bool_attribute("\\abc9_holes");
+ holes_module->set_bool_attribute(ID::abc9_holes);
dict<IdString, Cell*> cell_cache;
TimingInfo timing;
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
- if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
+ if (!box_module || (!box_module->get_bool_attribute(ID::abc9_box) && !box_module->get_bool_attribute(ID::abc9_flop)))
continue;
- cell->attributes["\\abc9_box_seq"] = box_count++;
+ cell->attributes[ID::abc9_box_seq] = box_count++;
IdString derived_type = box_module->derive(design, cell->parameters);
box_module = design->module(derived_type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
- if (box_module->get_bool_attribute("\\whitebox")) {
+ if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(cell->name, derived_type);
if (box_module->has_processes())
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute("\\abc9_flop")) {
+ if (box_module->get_bool_attribute(ID::abc9_flop)) {
box_inputs++;
Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
if (!holes_wire) {
continue;
if (!inst_module->get_blackbox_attribute())
continue;
- if (inst_module->attributes.count(ID(abc9_box)))
+ if (inst_module->attributes.count(ID::abc9_box))
continue;
IdString derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
- if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
+ if (dff_mode && inst_module->get_bool_attribute(ID::abc9_flop)) {
flops.insert(inst_module);
continue; // do not add $__ABC9_DELAY boxes to flops
// as delays will be captured in the flop box
}
#endif
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
- box->setPort(ID(I), conn.second[i]);
- box->setPort(ID(O), O[i]);
- box->setParam(ID(DELAY), d);
+ box->setPort(ID::I, conn.second[i]);
+ box->setPort(ID::O, O[i]);
+ box->setParam(ID::DELAY, d);
conn.second[i] = O[i];
}
}
std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
for (auto module : design->modules()) {
- auto it = module->attributes.find(ID(abc9_lut));
+ auto it = module->attributes.find(ID::abc9_lut);
if (it == module->attributes.end())
continue;
std::stringstream ss;
int abc9_box_id = 1;
for (auto module : design->modules()) {
- auto it = module->attributes.find(ID(abc9_box_id));
+ auto it = module->attributes.find(ID::abc9_box_id);
if (it == module->attributes.end())
continue;
abc9_box_id = std::max(abc9_box_id, it->second.as_int());
dict<IdString,std::vector<IdString>> box_ports;
for (auto module : design->modules()) {
- auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
+ auto abc9_flop = module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop) {
- auto r = module->attributes.insert(ID(abc9_box_id));
+ auto r = module->attributes.insert(ID::abc9_box_id);
if (!r.second)
continue;
r.first->second = abc9_box_id++;
}
}
else {
- if (!module->attributes.erase(ID(abc9_box)))
+ if (!module->attributes.erase(ID::abc9_box))
continue;
- auto r = module->attributes.insert(ID(abc9_box_id));
+ auto r = module->attributes.insert(ID::abc9_box_id);
if (!r.second)
continue;
r.first->second = abc9_box_id++;
for (const auto &port_name : module->ports) {
auto w = module->wire(port_name);
log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
outputs.emplace_back(wire, i);
}
- ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
+ ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
dict<IdString,std::vector<IdString>> box_ports;
for (auto m : design->modules()) {
- if (!m->attributes.count(ID(abc9_box_id)))
+ if (!m->attributes.count(ID::abc9_box_id))
continue;
auto r = box_ports.insert(m->name);
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
- if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
continue;
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
module->remove(cell);
- else if (cell->attributes.erase("\\abc9_box_seq"))
+ else if (cell->attributes.erase(ID::abc9_box_seq))
boxes.emplace_back(cell);
}
IdString derived_type = box_module->derive(design, existing_cell->parameters);
RTLIL::Module* derived_module = design->module(derived_type);
log_assert(derived_module);
- log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
+ log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->attributes = existing_cell->attributes;
module->swap_names(cell, existing_cell);
- auto jt = mapped_cell->connections_.find("\\i");
+ auto jt = mapped_cell->connections_.find(ID(i));
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
- jt = mapped_cell->connections_.find("\\o");
+ jt = mapped_cell->connections_.find(ID(o));
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
- auto abc9_flop = box_module->attributes.count("\\abc9_flop");
+ auto abc9_flop = box_module->attributes.count(ID::abc9_flop);
if (!abc9_flop) {
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
- wire->attributes.erase(ID(abc9_scc));
+ wire->attributes.erase(ID::abc9_scc);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID::A);
- RTLIL::Const mask = sink_cell->getParam(ID(LUT));
+ RTLIL::Const mask = sink_cell->getParam(ID::LUT);
int index = 0;
for (; index < GetSize(A); index++)
if (A[index] == a_bit)
}
A[index] = y_bit;
sink_cell->setPort(ID::A, A);
- sink_cell->setParam(ID(LUT), mask);
+ sink_cell->setParam(ID::LUT, mask);
}
// Since we have rewritten all sinks (which we know
// that the original driving LUT will become dangling
// and get cleaned away
clone_lut:
- driver_mask = driver_lut->getParam(ID(LUT));
+ driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
prep_box(design, dff_mode);
for (auto mod : design->selected_modules()) {
- if (mod->get_bool_attribute("\\abc9_holes"))
+ if (mod->get_bool_attribute(ID::abc9_holes))
continue;
if (mod->processes.size() > 0) {
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
- cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID(X)), false, alu_cell->get_src_attribute());
+ cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
return cached_eq;
}
RTLIL::SigSpec get_cf() {
if (GetSize(cached_cf) == 0) {
- cached_cf = alu_cell->getPort(ID(CO));
+ cached_cf = alu_cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
}
RTLIL::SigSpec get_of() {
if (GetSize(cached_of) == 0) {
- cached_of = {alu_cell->getPort(ID(CO)), alu_cell->getPort(ID(CI))};
+ cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
if (cell->type.in(ID($pos), ID($neg)))
{
new_port.in_a = sigmap(cell->getPort(ID::A));
- new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = cell->type == ID($neg);
n->macc.ports.push_back(new_port);
}
if (cell->type.in(ID($add), ID($sub)))
{
new_port.in_a = sigmap(cell->getPort(ID::A));
- new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
new_port.in_a = sigmap(cell->getPort(ID::B));
- new_port.is_signed = cell->getParam(ID(B_SIGNED)).as_bool();
+ new_port.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
new_port.do_subtract = cell->type == ID($sub);
n->macc.ports.push_back(new_port);
}
{
new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.in_b = sigmap(cell->getPort(ID::B));
- new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
}
bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = cell->type.in(ID($le), ID($ge));
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
for (auto cell : eq_cells)
{
bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
- bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);
- n->alu_cell->setPort(ID(CI), GetSize(n->c) ? n->c : State::S0);
- n->alu_cell->setPort(ID(BI), n->invert_b ? State::S1 : State::S0);
+ n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
+ n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
- n->alu_cell->setPort(ID(X), module->addWire(NEW_ID, GetSize(n->y)));
- n->alu_cell->setPort(ID(CO), module->addWire(NEW_ID, GetSize(n->y)));
+ n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
+ n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
- IdString clkbuf_inhibit("\\clkbuf_inhibit");
-
// Process submodules before module using them.
std::vector<Module *> modules_sorted;
pool<Module *> modules_processed;
if (module->get_blackbox_attribute()) {
for (auto port : module->ports) {
auto wire = module->wire(port);
- if (wire->get_bool_attribute("\\clkbuf_driver"))
+ if (wire->get_bool_attribute(ID::clkbuf_driver))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
- if (wire->get_bool_attribute("\\clkbuf_sink"))
+ if (wire->get_bool_attribute(ID::clkbuf_sink))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
- auto it = wire->attributes.find("\\clkbuf_inv");
+ auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
for (int i = 0; i < GetSize(wire); i++) {
if (wire->port_input && wire->port_output)
continue;
bool process_wire = module->selected(wire);
- if (!select && wire->get_bool_attribute(clkbuf_inhibit))
+ if (!select && wire->get_bool_attribute(ID::clkbuf_inhibit))
process_wire = false;
if (!process_wire) {
// This wire is supposed to be bypassed, so make sure we don't buffer it in
cell_int_t mux_cell_int = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B));
- RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(S)));
+ RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID::S));
int width = GetSize(sig_a), index = mux_cell_int.second;
for (int i = 0; i < GetSize(sig_s); i++)
void handle_dff_cell(RTLIL::Cell *dff_cell)
{
- RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID(D)));
- RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID(Q)));
+ RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID::D));
+ RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID::Q));
std::map<patterns_t, std::set<int>> grouped_patterns;
std::set<int> remaining_indices;
}
if (!direct_dict.empty()) {
log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q));
- dff_cell->setPort(ID(E), make_patterns_logic(it.first, true));
+ dff_cell->setPort(ID::E, make_patterns_logic(it.first, true));
dff_cell->type = direct_dict.at(dff_cell->type);
} else
if (dff_cell->type == ID($dff)) {
- RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID(CLK)), make_patterns_logic(it.first, false),
- new_sig_d, new_sig_q, dff_cell->getParam(ID(CLK_POLARITY)).as_bool(), true);
+ RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID::CLK), make_patterns_logic(it.first, false),
+ new_sig_d, new_sig_q, dff_cell->getParam(ID::CLK_POLARITY).as_bool(), true);
log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
} else {
- RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID(C)), make_patterns_logic(it.first, true),
+ RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID::C), make_patterns_logic(it.first, true),
new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true);
log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
}
new_sig_d.append(sig_d[i]);
new_sig_q.append(sig_q[i]);
}
- dff_cell->setPort(ID(D), new_sig_d);
- dff_cell->setPort(ID(Q), new_sig_q);
- dff_cell->setParam(ID(WIDTH), GetSize(remaining_indices));
+ dff_cell->setPort(ID::D, new_sig_d);
+ dff_cell->setPort(ID::Q, new_sig_q);
+ dff_cell->setParam(ID::WIDTH, GetSize(remaining_indices));
}
}
for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type)
continue;
- if (sigmap(cell->getPort(ID(EN))) == sigmap(cell_other->getPort(ID(EN))))
+ if (sigmap(cell->getPort(ID::EN)) == sigmap(cell_other->getPort(ID::EN)))
ce_use++;
}
if (ce_use >= min_ce_use)
continue;
}
- RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID(D))));
- mod->addDff(NEW_ID, cell->getPort(ID(CLK)), tmp, cell->getPort(ID(Q)), cell->getParam(ID(CLK_POLARITY)).as_bool());
- if (cell->getParam(ID(EN_POLARITY)).as_bool())
- mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(EN)), tmp);
+ RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID::D)));
+ mod->addDff(NEW_ID, cell->getPort(ID::CLK), tmp, cell->getPort(ID::Q), cell->getParam(ID::CLK_POLARITY).as_bool());
+ if (cell->getParam(ID::EN_POLARITY).as_bool())
+ mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::EN), tmp);
else
- mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(EN)), tmp);
+ mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::EN), tmp);
mod->remove(cell);
continue;
}
for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type)
continue;
- if (sigmap(cell->getPort(ID(E))) == sigmap(cell_other->getPort(ID(E))))
+ if (sigmap(cell->getPort(ID::E)) == sigmap(cell_other->getPort(ID::E)))
ce_use++;
}
if (ce_use >= min_ce_use)
bool clk_pol = cell->type.compare(7, 1, "P") == 0;
bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
- mod->addDff(NEW_ID, cell->getPort(ID(C)), tmp, cell->getPort(ID(Q)), clk_pol);
+ mod->addDff(NEW_ID, cell->getPort(ID::C), tmp, cell->getPort(ID::Q), clk_pol);
if (en_pol)
- mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(E)), tmp);
+ mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::E), tmp);
else
- mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(E)), tmp);
+ mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::E), tmp);
mod->remove(cell);
continue;
}
for (auto cell : ff_cells)
{
- SigSpec sig_d = cell->getPort(ID(D));
+ SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
Cell *mux_cell = sr_muxes.at(bit_d);
SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
- SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
+ SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
SigBit sr_val, sr_sig;
bool invert_sr;
}
if (match_init) {
- SigBit bit_q = cell->getPort(ID(Q));
+ SigBit bit_q = cell->getPort(ID::Q);
if (bit_q.wire) {
- auto it = bit_q.wire->attributes.find(ID(init));
+ auto it = bit_q.wire->attributes.find(ID::init);
if (it != bit_q.wire->attributes.end()) {
auto init_val = it->second[bit_q.offset];
if (init_val == State::S1 && sr_val != State::S1)
else cell->type = ID($__DFFS_PP0_);
}
}
- cell->setPort(ID(R), sr_sig);
- cell->setPort(ID(D), bit_d);
+ cell->setPort(ID::R, sr_sig);
+ cell->setPort(ID::D, bit_d);
}
}
}
pool<SigBit> used_bits;
for (auto wire : module->selected_wires()) {
- if (wire->attributes.count(ID(init))) {
- Const value = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init)) {
+ Const value = wire->attributes.at(ID::init);
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
for (auto wire : module->selected_wires())
- if (wire->attributes.count(ID(init))) {
- Const &value = wire->attributes.at(ID(init));
+ if (wire->attributes.count(ID::init)) {
+ Const &value = wire->attributes.at(ID::init);
bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
}
}
}
{
if (cell->type == ID($dffsr))
{
- int width = cell->getParam(ID(WIDTH)).as_int();
- bool setpol = cell->getParam(ID(SET_POLARITY)).as_bool();
- bool clrpol = cell->getParam(ID(CLR_POLARITY)).as_bool();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ bool setpol = cell->getParam(ID::SET_POLARITY).as_bool();
+ bool clrpol = cell->getParam(ID::CLR_POLARITY).as_bool();
SigBit setunused = setpol ? State::S0 : State::S1;
SigBit clrunused = clrpol ? State::S0 : State::S1;
- SigSpec setsig = sigmap(cell->getPort(ID(SET)));
- SigSpec clrsig = sigmap(cell->getPort(ID(CLR)));
+ SigSpec setsig = sigmap(cell->getPort(ID::SET));
+ SigSpec clrsig = sigmap(cell->getPort(ID::CLR));
Const reset_val;
SigSpec setctrl, clrctrl;
log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
if (GetSize(setctrl) == 1) {
- cell->setPort(ID(ARST), setctrl);
- cell->setParam(ID(ARST_POLARITY), setpol);
+ cell->setPort(ID::ARST, setctrl);
+ cell->setParam(ID::ARST_POLARITY, setpol);
} else {
- cell->setPort(ID(ARST), clrctrl);
- cell->setParam(ID(ARST_POLARITY), clrpol);
+ cell->setPort(ID::ARST, clrctrl);
+ cell->setParam(ID::ARST_POLARITY, clrpol);
}
cell->type = ID($adff);
- cell->unsetPort(ID(SET));
- cell->unsetPort(ID(CLR));
- cell->setParam(ID(ARST_VALUE), reset_val);
- cell->unsetParam(ID(SET_POLARITY));
- cell->unsetParam(ID(CLR_POLARITY));
+ cell->unsetPort(ID::SET);
+ cell->unsetPort(ID::CLR);
+ cell->setParam(ID::ARST_VALUE, reset_val);
+ cell->unsetParam(ID::SET_POLARITY);
+ cell->unsetParam(ID::CLR_POLARITY);
return;
}
char setpol = cell->type.c_str()[9];
char clrpol = cell->type.c_str()[10];
- SigBit setbit = sigmap(cell->getPort(ID(S)));
- SigBit clrbit = sigmap(cell->getPort(ID(R)));
+ SigBit setbit = sigmap(cell->getPort(ID::S));
+ SigBit clrbit = sigmap(cell->getPort(ID::R));
SigBit setunused = setpol == 'P' ? State::S0 : State::S1;
SigBit clrunused = clrpol == 'P' ? State::S0 : State::S1;
if (setbit == setunused) {
cell->type = stringf("$_DFF_%c%c0_", clkpol, clrpol);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
goto converted_gate;
}
if (clrbit == clrunused) {
cell->type = stringf("$_DFF_%c%c1_", clkpol, setpol);
- cell->setPort(ID(R), cell->getPort(ID(S)));
- cell->unsetPort(ID(S));
+ cell->setPort(ID::R, cell->getPort(ID::S));
+ cell->unsetPort(ID::S);
goto converted_gate;
}
{
if (cell->type == ID($adff))
{
- bool rstpol = cell->getParam(ID(ARST_POLARITY)).as_bool();
+ bool rstpol = cell->getParam(ID::ARST_POLARITY).as_bool();
SigBit rstunused = rstpol ? State::S0 : State::S1;
- SigSpec rstsig = sigmap(cell->getPort(ID(ARST)));
+ SigSpec rstsig = sigmap(cell->getPort(ID::ARST));
if (rstsig != rstunused)
return;
log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell));
cell->type = ID($dff);
- cell->unsetPort(ID(ARST));
- cell->unsetParam(ID(ARST_VALUE));
- cell->unsetParam(ID(ARST_POLARITY));
+ cell->unsetPort(ID::ARST);
+ cell->unsetParam(ID::ARST_VALUE);
+ cell->unsetParam(ID::ARST_POLARITY);
return;
}
char clkpol = cell->type.c_str()[6];
char rstpol = cell->type.c_str()[7];
- SigBit rstbit = sigmap(cell->getPort(ID(R)));
+ SigBit rstbit = sigmap(cell->getPort(ID::R));
SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1;
if (rstbit != rstunused)
log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype));
cell->type = newtype;
- cell->unsetPort(ID(R));
+ cell->unsetPort(ID::R);
return;
}
return value;
#define param_bool(_n) if (param == _n) return value.as_bool();
- param_bool(ID(ARST_POLARITY));
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- param_bool(ID(CLK_ENABLE));
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(CLR_POLARITY));
- param_bool(ID(EN_POLARITY));
- param_bool(ID(SET_POLARITY));
- param_bool(ID(TRANSPARENT));
+ param_bool(ID::ARST_POLARITY);
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ param_bool(ID::CLK_ENABLE);
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::TRANSPARENT);
#undef param_bool
#define param_int(_n) if (param == _n) return value.as_int();
- param_int(ID(ABITS))
- param_int(ID(A_WIDTH))
- param_int(ID(B_WIDTH))
- param_int(ID(CTRL_IN_WIDTH))
- param_int(ID(CTRL_OUT_WIDTH))
- param_int(ID(OFFSET))
- param_int(ID(PRIORITY))
- param_int(ID(RD_PORTS))
- param_int(ID(SIZE))
- param_int(ID(STATE_BITS))
- param_int(ID(STATE_NUM))
- param_int(ID(STATE_NUM_LOG2))
- param_int(ID(STATE_RST))
- param_int(ID(S_WIDTH))
- param_int(ID(TRANS_NUM))
- param_int(ID(WIDTH))
- param_int(ID(WR_PORTS))
- param_int(ID(Y_WIDTH))
+ param_int(ID::ABITS)
+ param_int(ID::A_WIDTH)
+ param_int(ID::B_WIDTH)
+ param_int(ID::CTRL_IN_WIDTH)
+ param_int(ID::CTRL_OUT_WIDTH)
+ param_int(ID::OFFSET)
+ param_int(ID::PRIORITY)
+ param_int(ID::RD_PORTS)
+ param_int(ID::SIZE)
+ param_int(ID::STATE_BITS)
+ param_int(ID::STATE_NUM)
+ param_int(ID::STATE_NUM_LOG2)
+ param_int(ID::STATE_RST)
+ param_int(ID::S_WIDTH)
+ param_int(ID::TRANS_NUM)
+ param_int(ID::WIDTH)
+ param_int(ID::WR_PORTS)
+ param_int(ID::Y_WIDTH)
#undef param_int
return value;
bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
{
int left_idx = 0, right_idx = 0;
- if (left->attributes.count(ID(extract_order)) > 0)
- left_idx = left->attributes.at(ID(extract_order)).as_int();
- if (right->attributes.count(ID(extract_order)) > 0)
- right_idx = right->attributes.at(ID(extract_order)).as_int();
+ if (left->attributes.count(ID::extract_order) > 0)
+ left_idx = left->attributes.at(ID::extract_order).as_int();
+ if (right->attributes.count(ID::extract_order) > 0)
+ right_idx = right->attributes.at(ID::extract_order).as_int();
if (left_idx != right_idx)
return left_idx < right_idx;
return left->name < right->name;
SigMap& sigmap = index.sigmap;
//Both inputs must be unsigned, so don't extract anything with a signed input
- bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool();
- bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool();
+ bool a_sign = cell->getParam(ID::A_SIGNED).as_bool();
+ bool b_sign = cell->getParam(ID::B_SIGNED).as_bool();
if(a_sign || b_sign)
return 3;
//CO and X must be unconnected (exactly one connection to each port)
- if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index))
+ if(!is_unconnected(sigmap(cell->getPort(ID::CO)), index))
return 7;
- if(!is_unconnected(sigmap(cell->getPort(ID(X))), index))
+ if(!is_unconnected(sigmap(cell->getPort(ID::X)), index))
return 8;
//true if $alu is performing A - B, else A + B
bool alu_is_subtract;
//BI and CI must be both constant 0 or both constant 1 as well
- const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
- const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
+ const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID::BI));
+ const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID::CI));
if(bi_port.is_fully_const() && bi_port.as_int() == 1 &&
ci_port.is_fully_const() && ci_port.as_int() == 1)
{
if(alu_is_subtract)
{
- const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ const int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
// down, cnt <= cnt - 1
}
else
{
- const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
- const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
+ const int a_width = cell->getParam(ID::A_WIDTH).as_int();
+ const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A));
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
//Check if counter is an appropriate size
int count_width;
if (alu_port_use_a)
- count_width = cell->getParam(ID(A_WIDTH)).as_int();
+ count_width = cell->getParam(ID::A_WIDTH).as_int();
else
- count_width = cell->getParam(ID(B_WIDTH)).as_int();
+ count_width = cell->getParam(ID::B_WIDTH).as_int();
extract.width = count_width;
if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) )
return 1;
//S connection of the mux must come from an inverter if down, eq if up
//(need not be the only load)
- const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S)));
+ const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID::S));
extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
Cell* overflow_cell = NULL;
continue;
if(!extract.count_is_up && c->type != ID($logic_not))
continue;
- if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true))
+ if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true))
continue;
overflow_cell = c;
return 24;
count_reg = *cey_loads.begin();
- if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D))))
+ if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID::D)))
return 24;
//Mux should have A driven by count Q, and B by muxy
//if A and B are swapped, CE polarity is inverted
if(sigmap(cemux->getPort(ID::B)) == muxy &&
- sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID(Q))))
+ sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = false;
}
else if(sigmap(cemux->getPort(ID::A)) == muxy &&
- sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID(Q))))
+ sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = true;
}
//Select of the mux is our clock enable
extract.has_ce = true;
- extract.ce = sigmap(cemux->getPort(ID(S)));
+ extract.ce = sigmap(cemux->getPort(ID::S));
}
else
extract.has_ce = false;
extract.has_reset = true;
//Check polarity of reset - we may have to add an inverter later on!
- extract.rst_inverted = (count_reg->getParam(ID(ARST_POLARITY)).as_int() != 1);
+ extract.rst_inverted = (count_reg->getParam(ID::ARST_POLARITY).as_int() != 1);
//Verify ARST_VALUE is zero or full scale
- int rst_value = count_reg->getParam(ID(ARST_VALUE)).as_int();
+ int rst_value = count_reg->getParam(ID::ARST_VALUE).as_int();
if(rst_value == 0)
extract.rst_to_max = false;
else if(rst_value == extract.count_value)
return 23;
//Save the reset
- extract.rst = sigmap(count_reg->getPort(ID(ARST)));
+ extract.rst = sigmap(count_reg->getPort(ID::ARST));
}
//TODO: support synchronous reset
else
return 16;
if(extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::A))
return 16;
- if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D)))
+ if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID::D))
return 16;
}
- else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID(D)))
+ else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID::D))
return 16;
//TODO: Verify count_reg CLK_POLARITY is 1
//Register output must have exactly two loads, the inverter and ALU
//(unless we have a parallel output!)
//If we have a clock enable, 3 is OK
- const RTLIL::SigSpec qport = count_reg->getPort(ID(Q));
+ const RTLIL::SigSpec qport = count_reg->getPort(ID::Q);
extract.poutsig = qport;
extract.has_pout = false;
const RTLIL::SigSpec cnout = sigmap(qport);
}
if(!extract.count_is_up)
{
- if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
+ if(!is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true))
return 18;
}
else
{
- if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
+ if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true))
{
// B must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B));
return 12;
extract.count_value = overflow.as_int();
}
- else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true))
+ else if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::B, true))
{
// A must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A));
return 18;
}
}
- if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
+ if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::A, true))
return 19;
- if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true))
+ if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::B, true))
return 19;
//Look up the clock from the register
- extract.clk = sigmap(count_reg->getPort(ID(CLK)));
+ extract.clk = sigmap(count_reg->getPort(ID::CLK));
if(!extract.count_is_up)
{
//Register output net must have an INIT attribute equal to the count value
extract.rwire = cnout.as_wire();
- if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
+ if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end())
return 20;
- int rinit = extract.rwire->attributes[ID(init)].as_int();
+ int rinit = extract.rwire->attributes[ID::init].as_int();
if(rinit != extract.count_value)
return 21;
}
{
//Register output net must not have an INIT attribute or it must be zero
extract.rwire = cnout.as_wire();
- if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
+ if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end())
return 0;
- int rinit = extract.rwire->attributes[ID(init)].as_int();
+ int rinit = extract.rwire->attributes[ID::init].as_int();
if(rinit != 0)
return 21;
}
RTLIL::Wire* port_wire = port.as_wire();
bool force_extract = false;
bool never_extract = false;
- string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str();
+ string count_reg_src = port_wire->attributes[ID::src].decode_string().c_str();
if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
{
pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
//Wipe all of the old connections to the ALU
cell->unsetPort(ID::A);
cell->unsetPort(ID::B);
- cell->unsetPort(ID(BI));
- cell->unsetPort(ID(CI));
- cell->unsetPort(ID(CO));
- cell->unsetPort(ID(X));
+ cell->unsetPort(ID::BI);
+ cell->unsetPort(ID::CI);
+ cell->unsetPort(ID::CO);
+ cell->unsetPort(ID::X);
cell->unsetPort(ID::Y);
- cell->unsetParam(ID(A_SIGNED));
- cell->unsetParam(ID(A_WIDTH));
- cell->unsetParam(ID(B_SIGNED));
- cell->unsetParam(ID(B_WIDTH));
- cell->unsetParam(ID(Y_WIDTH));
+ cell->unsetParam(ID::A_SIGNED);
+ cell->unsetParam(ID::A_WIDTH);
+ cell->unsetParam(ID::B_SIGNED);
+ cell->unsetParam(ID::B_WIDTH);
+ cell->unsetParam(ID::Y_WIDTH);
//Change the cell type
cell->type = ID($__COUNT_);
//Hook up other stuff
//cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1));
cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value));
- cell->setParam(ID(WIDTH), RTLIL::Const(extract.width));
- cell->setPort(ID(CLK), extract.clk);
+ cell->setParam(ID::WIDTH, RTLIL::Const(extract.width));
+ cell->setPort(ID::CLK, extract.clk);
cell->setPort(ID(OUT), extract.outsig);
//Hook up clock enable
int newbits = ceil(log2(extract.count_value));
if(extract.width != newbits)
{
- cell->setParam(ID(WIDTH), RTLIL::Const(newbits));
+ cell->setParam(ID::WIDTH, RTLIL::Const(newbits));
log(" Optimizing out %d unused high-order bits (new width is %d)\n",
extract.width - newbits,
newbits);
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
- for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
+ for (auto port : {ID::A, ID::B, ID::C, ID::D}) {
if (!cell->hasPort(port))
continue;
auto bit = sigmap(SigBit(cell->getPort(port)));
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
- cell->setParam(ID(WIDTH), 1);
+ cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
- cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
+ cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
- cell->setPort(ID(X), X);
+ cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
- cell->setParam(ID(WIDTH), 1);
+ cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
- cell->setPort(ID(C), State::S0);
+ cell->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
- cell->setPort(ID(X), X);
+ cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
}
gt == GateType::And ? ID($reduce_and) :
gt == GateType::Or ? ID($reduce_or) :
gt == GateType::Xor ? ID($reduce_xor) : "");
- new_reduce_cell->setParam(ID(A_SIGNED), 0);
- new_reduce_cell->setParam(ID(A_WIDTH), input.size());
- new_reduce_cell->setParam(ID(Y_WIDTH), 1);
+ new_reduce_cell->setParam(ID::A_SIGNED, 0);
+ new_reduce_cell->setParam(ID::A_WIDTH, input.size());
+ new_reduce_cell->setParam(ID::Y_WIDTH, 1);
new_reduce_cell->setPort(ID::A, input);
new_reduce_cell->setPort(ID::Y, output);
auto cell_wire = cell_module->wire(port.first);
if (!cell_wire)
continue;
- auto it = cell_wire->attributes.find("\\invertible_pin");
+ auto it = cell_wire->attributes.find(ID::invertible_pin);
if (it == cell_wire->attributes.end())
continue;
IdString param_name = RTLIL::escape_id(it->second.decode_string());
for (auto gate_node : lut_gates[node])
{
auto gate_origin = node_origins[gate_node];
- lut->add_strpool_attribute(ID(src), gate_origin.cell->get_strpool_attribute(ID(src)));
+ lut->add_strpool_attribute(ID::src, gate_origin.cell->get_strpool_attribute(ID::src));
packed_count++;
}
lut_count++;
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
- IdString celltype = "$_BUF_", in_portname = ID::A, out_portname = ID::Y;
+ IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
// Collect explicitly-marked already-buffered SigBits.
for (auto wire : module->wires())
- if (wire->get_bool_attribute("\\iopad_external_pin") || ignore.count(make_pair(module->name, wire->name)))
+ if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(module->name, wire->name)))
for (int i = 0; i < GetSize(wire); i++)
buf_bits.insert(sigmap(SigBit(wire, i)));
if (tbuf_cell != nullptr) {
// Found a tristate buffer — use it.
- en_sig = tbuf_cell->getPort(ID(E)).as_bit();
+ en_sig = tbuf_cell->getPort(ID::E).as_bit();
data_sig = tbuf_cell->getPort(ID::A).as_bit();
} else if (is_driven) {
// No tristate buffer, but an always-on driver is present.
}
if (wire->port_output) {
- auto jt = new_wire->attributes.find(ID(init));
+ auto jt = new_wire->attributes.find(ID::init);
// For output ports, move \init attributes from old wire to new wire
if (jt != new_wire->attributes.end()) {
- wire->attributes[ID(init)] = std::move(jt->second);
+ wire->attributes[ID::init] = std::move(jt->second);
new_wire->attributes.erase(jt);
}
}
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
- Const lut = cell->getParam(ID(LUT));
+ Const lut = cell->getParam(ID::LUT);
int count = 1;
if (GetSize(sig_a) == 1)
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
- cell->setPort(ID(C), in3);
+ cell->setPort(ID::C, in3);
cell->setPort(ID::Y, w1);
- cell->setPort(ID(X), w2);
+ cell->setPort(ID::X, w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb};
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
- c->setPort(ID(CI), State::S0);
- c->setPort(ID(BI), State::S0);
+ c->setPort(ID::CI, State::S0);
+ c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
- c->setPort(ID(X), module->addWire(NEW_ID, width));
- c->setPort(ID(CO), module->addWire(NEW_ID, width));
+ c->setPort(ID::X, module->addWire(NEW_ID, width));
+ c->setPort(ID::CO, module->addWire(NEW_ID, width));
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
- c->setPort(ID(CI), tree_sum_bits.back());
+ c->setPort(ID::CI, tree_sum_bits.back());
tree_sum_bits.pop_back();
}
log_assert(tree_sum_bits.empty());
if (!cell->input(conn.first))
continue;
for (auto bit : sigmap(conn.second)) {
- if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(S))
+ if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID::S)
roots.insert(bit);
used_once.insert(bit);
}
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
- cell->setPort(ID(S), mux.selects[0]);
+ cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::Y, bit);
return;
}
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
- cell->setPort(ID(C), mux.inputs[2]);
- cell->setPort(ID(D), mux.inputs[3]);
- cell->setPort(ID(S), mux.selects[0]);
- cell->setPort(ID(T), mux.selects[1]);
+ cell->setPort(ID::C, mux.inputs[2]);
+ cell->setPort(ID::D, mux.inputs[3]);
+ cell->setPort(ID::S, mux.selects[0]);
+ cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::Y, bit);
return;
}
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
- cell->setPort(ID(C), mux.inputs[2]);
- cell->setPort(ID(D), mux.inputs[3]);
- cell->setPort(ID(E), mux.inputs[4]);
- cell->setPort(ID(F), mux.inputs[5]);
- cell->setPort(ID(G), mux.inputs[6]);
- cell->setPort(ID(H), mux.inputs[7]);
- cell->setPort(ID(S), mux.selects[0]);
- cell->setPort(ID(T), mux.selects[1]);
- cell->setPort(ID(U), mux.selects[2]);
+ cell->setPort(ID::C, mux.inputs[2]);
+ cell->setPort(ID::D, mux.inputs[3]);
+ cell->setPort(ID::E, mux.inputs[4]);
+ cell->setPort(ID::F, mux.inputs[5]);
+ cell->setPort(ID::G, mux.inputs[6]);
+ cell->setPort(ID::H, mux.inputs[7]);
+ cell->setPort(ID::S, mux.selects[0]);
+ cell->setPort(ID::T, mux.selects[1]);
+ cell->setPort(ID::U, mux.selects[2]);
cell->setPort(ID::Y, bit);
return;
}
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
- cell->setPort(ID(C), mux.inputs[2]);
- cell->setPort(ID(D), mux.inputs[3]);
- cell->setPort(ID(E), mux.inputs[4]);
- cell->setPort(ID(F), mux.inputs[5]);
- cell->setPort(ID(G), mux.inputs[6]);
- cell->setPort(ID(H), mux.inputs[7]);
- cell->setPort(ID(I), mux.inputs[8]);
- cell->setPort(ID(J), mux.inputs[9]);
- cell->setPort(ID(K), mux.inputs[10]);
- cell->setPort(ID(L), mux.inputs[11]);
- cell->setPort(ID(M), mux.inputs[12]);
- cell->setPort(ID(N), mux.inputs[13]);
- cell->setPort(ID(O), mux.inputs[14]);
- cell->setPort(ID(P), mux.inputs[15]);
- cell->setPort(ID(S), mux.selects[0]);
- cell->setPort(ID(T), mux.selects[1]);
- cell->setPort(ID(U), mux.selects[2]);
- cell->setPort(ID(V), mux.selects[3]);
+ cell->setPort(ID::C, mux.inputs[2]);
+ cell->setPort(ID::D, mux.inputs[3]);
+ cell->setPort(ID::E, mux.inputs[4]);
+ cell->setPort(ID::F, mux.inputs[5]);
+ cell->setPort(ID::G, mux.inputs[6]);
+ cell->setPort(ID::H, mux.inputs[7]);
+ cell->setPort(ID::I, mux.inputs[8]);
+ cell->setPort(ID::J, mux.inputs[9]);
+ cell->setPort(ID::K, mux.inputs[10]);
+ cell->setPort(ID::L, mux.inputs[11]);
+ cell->setPort(ID::M, mux.inputs[12]);
+ cell->setPort(ID::N, mux.inputs[13]);
+ cell->setPort(ID::O, mux.inputs[14]);
+ cell->setPort(ID::P, mux.inputs[15]);
+ cell->setPort(ID::S, mux.selects[0]);
+ cell->setPort(ID::T, mux.selects[1]);
+ cell->setPort(ID::U, mux.selects[2]);
+ cell->setPort(ID::V, mux.selects[3]);
cell->setPort(ID::Y, bit);
return;
}
continue;
SigSpec sig_data = cell->getPort(ID::B);
- SigSpec sig_sel = cell->getPort(ID(S));
+ SigSpec sig_sel = cell->getPort(ID::S);
if (!cell->getPort(ID::A).is_fully_undef()) {
sig_data.append(cell->getPort(ID::A));
bool fixup(Cell *cell, dict<int, SigBit> &taps)
{
- auto D = cell->getPort(ID(D));
- auto C = cell->getPort(ID(C));
+ auto D = cell->getPort(ID::D);
+ auto C = cell->getPort(ID::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
- newcell->setPort(ID(CLK), C);
+ newcell->setPort(ID::CLK, C);
newcell->setPort(ID(IN), D);
int i = 0;
sigbit_with_non_chain_users.insert(bit);
}
- if (wire->attributes.count(ID(init))) {
+ if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire);
- Const initval = wire->attributes.at(ID(init));
+ Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 && !opts.zinit)
sigbit_init[initsig[i]] = false;
initval.push_back(State::S0);
remove_init.insert(bit);
}
- first_cell->setParam(ID(INIT), initval);
+ first_cell->setParam(ID::INIT, initval);
}
if (opts.zinit)
first_cell->type = shreg_cell_type_str;
first_cell->setPort(q_port, last_cell->getPort(q_port));
- first_cell->setParam(ID(DEPTH), depth);
+ first_cell->setParam(ID::DEPTH, depth);
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
remove_cells.insert(first_cell);
for (auto wire : module->wires())
{
- if (wire->attributes.count(ID(init)) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec initsig = sigmap(wire);
- Const &initval = wire->attributes.at(ID(init));
+ Const &initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (remove_init.count(initsig[i]))
initval[i] = State::Sx;
if (SigSpec(initval).is_fully_undef())
- wire->attributes.erase(ID(init));
+ wire->attributes.erase(ID::init);
}
remove_cells.clear();
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
- opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_none)
- opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_pos)
- opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_neg)
- opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_pos)
- opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_neg)
- opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
+ opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (en_pos || en_neg)
opts.ffe = true;
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
}
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
- sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID(B_SIGNED)).as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
+ sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
if (cell->type == ID($xnor))
{
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_t[i]);
gate->setPort(ID::Y, sig_y[i]);
}
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::Y, sig_y[i]);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
last_output_cell = gate;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
}
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
gate->setPort(ID::Y, sig_y);
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
- bool is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
+ bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
- xor_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
- reduce_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
- not_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_lognot(module, not_cell);
module->remove(not_cell);
}
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
- gate->setPort(ID(S), cell->getPort(ID(S)));
+ gate->setPort(ID::S, cell->getPort(ID::S));
gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
- RTLIL::SigSpec sig_e = cell->getPort(ID(EN));
+ RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
- gate->setPort(ID(E), sig_e);
+ gate->setPort(ID::E, sig_e);
gate->setPort(ID::Y, sig_y[i]);
}
}
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec lut_ctrl = cell->getPort(ID::A);
- SigSpec lut_data = cell->getParam(ID(LUT));
- lut_data.extend_u0(1 << cell->getParam(ID(WIDTH)).as_int());
+ SigSpec lut_data = cell->getParam(ID::LUT);
+ lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec sig_s = lut_ctrl[idx];
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
- gate->setPort(ID(S), lut_ctrl[idx]);
+ gate->setPort(ID::S, lut_ctrl[idx]);
gate->setPort(ID::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec ctrl = cell->getPort(ID::A);
- SigSpec table = cell->getParam(ID(TABLE));
+ SigSpec table = cell->getParam(ID::TABLE);
- int width = cell->getParam(ID(WIDTH)).as_int();
- int depth = cell->getParam(ID(DEPTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int depth = cell->getParam(ID::DEPTH).as_int();
table.extend_u0(2 * width * depth);
SigSpec products;
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int offset = cell->parameters.at(ID(OFFSET)).as_int();
+ int offset = cell->parameters.at(ID::OFFSET).as_int();
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
- char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+ char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
- RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
- RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+ RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(S), sig_s[i]);
- gate->setPort(ID(R), sig_r[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::S, sig_s[i]);
+ gate->setPort(ID::R, sig_r[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
+ int width = cell->parameters.at(ID::WIDTH).as_int();
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = ID($_FF_);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
- RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(C), sig_clk);
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
- char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
- RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
- RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(C), sig_clk);
- gate->setPort(ID(E), sig_en);
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::E, sig_en);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
- char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
- char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+ char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+ char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
- RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
- RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
- RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+ RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(C), sig_clk);
- gate->setPort(ID(S), sig_s[i]);
- gate->setPort(ID(R), sig_r[i]);
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::S, sig_s[i]);
+ gate->setPort(ID::R, sig_r[i]);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
- char rst_pol = cell->parameters.at(ID(ARST_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+ char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
- std::vector<RTLIL::State> rst_val = cell->parameters.at(ID(ARST_VALUE)).bits;
+ std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
while (int(rst_val.size()) < width)
rst_val.push_back(RTLIL::State::S0);
- RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
- RTLIL::SigSpec sig_rst = cell->getPort(ID(ARST));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(C), sig_clk);
- gate->setPort(ID(R), sig_rst);
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::R, sig_rst);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
{
- int width = cell->parameters.at(ID(WIDTH)).as_int();
- char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
- RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
- RTLIL::SigSpec sig_d = cell->getPort(ID(D));
- RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
- gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
- gate->setPort(ID(E), sig_en);
- gate->setPort(ID(D), sig_d[i]);
- gate->setPort(ID(Q), sig_q[i]);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::E, sig_en);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
}
}
record.value = it.second;
result[p].push_back(record);
it.second->attributes[ID::keep] = RTLIL::Const(1);
- it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
+ it.second->attributes[ID::_techmap_special_] = RTLIL::Const(1);
}
}
}
std::string orig_cell_name;
- pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
+ pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
orig_cell_name = cell->name.str();
if (!flatten_mode) {
for (auto &it : tpl->cells_)
- if (it.first == ID(_TECHMAP_REPLACE_)) {
+ if (it.first == ID::_TECHMAP_REPLACE_) {
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
- if (m->attributes.count(ID(src)))
- m->add_strpool_attribute(ID(src), extra_src_attrs);
+ if (m->attributes.count(ID::src))
+ m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
IdString posportname = stringf("$%d", it.second->port_id);
positional_ports[posportname] = it.first;
- if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
+ if (!flatten_mode && it.second->get_bool_attribute(ID::techmap_autopurge) &&
(!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
{
apply_prefix(cell->name, w_name);
RTLIL::Wire *w = module->wire(w_name);
if (w != nullptr) {
- if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
+ if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
temp_renamed_wires[w] = w->name;
module->rename(w, NEW_ID);
w = nullptr;
} else {
- w->attributes.erase(ID(hierconn));
+ w->attributes.erase(ID::hierconn);
if (GetSize(w) < GetSize(it.second)) {
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
w->port_output = false;
w->port_id = 0;
if (!flatten_mode)
- w->attributes.erase(ID(techmap_autopurge));
- if (it.second->get_bool_attribute(ID(_techmap_special_)))
+ w->attributes.erase(ID::techmap_autopurge);
+ if (it.second->get_bool_attribute(ID::_techmap_special_))
w->attributes.clear();
- if (w->attributes.count(ID(src)))
- w->add_strpool_attribute(ID(src), extra_src_attrs);
+ if (w->attributes.count(ID::src))
+ w->add_strpool_attribute(ID::src, extra_src_attrs);
}
design->select(module, w);
}
for (auto &attr : w->attributes) {
- if (attr.first == ID(src))
+ if (attr.first == ID::src)
continue;
auto lhs = GetSize(extra_connect.first);
auto rhs = GetSize(extra_connect.second);
for (auto &it : tpl->cells_)
{
IdString c_name = it.second->name.str();
- bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
+ bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
if (techmap_replace_cell)
c_name = orig_cell_name;
c->unsetPort(it2);
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
- IdString memid = c->getParam(ID(MEMID)).decode_string();
+ IdString memid = c->getParam(ID::MEMID).decode_string();
log_assert(memory_renames.count(memid) != 0);
- c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
+ c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
}
if (c->type == ID($mem)) {
- IdString memid = c->getParam(ID(MEMID)).decode_string();
+ IdString memid = c->getParam(ID::MEMID).decode_string();
apply_prefix(cell->name, memid);
- c->setParam(ID(MEMID), Const(memid.c_str()));
+ c->setParam(ID::MEMID, Const(memid.c_str()));
}
- if (c->attributes.count(ID(src)))
- c->add_strpool_attribute(ID(src), extra_src_attrs);
+ if (c->attributes.count(ID::src))
+ c->add_strpool_attribute(ID::src, extra_src_attrs);
if (techmap_replace_cell)
for (auto attr : cell->attributes)
pool<SigBit> remove_init_bits;
for (auto wire : module->wires()) {
- if (wire->attributes.count("\\init")) {
- Const value = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const value = wire->attributes.at(ID::init);
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i];
}
if (flatten_mode) {
- bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
+ bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
for (auto &tpl_name : celltypeMap.at(cell_type))
- if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
+ if (map->modules_[tpl_name]->get_bool_attribute(ID::keep_hierarchy))
keepit = true;
if (keepit) {
if (!flatten_keep_list[cell]) {
{
std::string extmapper_name;
- if (tpl->get_bool_attribute(ID(techmap_simplemap)))
+ if (tpl->get_bool_attribute(ID::techmap_simplemap))
extmapper_name = "simplemap";
- if (tpl->get_bool_attribute(ID(techmap_maccmap)))
+ if (tpl->get_bool_attribute(ID::techmap_maccmap))
extmapper_name = "maccmap";
- if (tpl->attributes.count(ID(techmap_wrap)))
+ if (tpl->attributes.count(ID::techmap_wrap))
extmapper_name = "wrap";
if (!extmapper_name.empty())
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
- m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
+ m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
- if (w->name.in(ID::Y, ID(Q)))
+ if (w->name.in(ID::Y, ID::Q))
w->port_output = true;
else
w->port_input = true;
}
if (extmapper_name == "wrap") {
- std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
+ std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
continue;
}
- if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
- parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
+ if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
+ parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type);
for (auto conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
bits = i;
// Increment index by one to get number of bits
bits++;
- if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
- parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
+ if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
+ parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
for (auto conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
if (!remove_init_bits.empty()) {
for (auto wire : module->wires())
- if (wire->attributes.count("\\init")) {
- Const &value = wire->attributes.at("\\init");
+ if (wire->attributes.count(ID::init)) {
+ Const &value = wire->attributes.at(ID::init);
bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
}
}
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) {
- if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
- char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
+ if (it.second->attributes.count(ID::techmap_celltype) && !it.second->attributes.at(ID::techmap_celltype).bits.empty()) {
+ char *p = strdup(it.second->attributes.at(ID::techmap_celltype).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p);
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
for (auto mod : design->modules())
- if (mod->get_bool_attribute(ID(top)))
+ if (mod->get_bool_attribute(ID::top))
top_mod = mod;
std::set<RTLIL::Cell*> handled_cells;
if (cell->type.in(ID($mux), ID($_MUX_)))
{
- IdString en_port = cell->type == ID($mux) ? ID(EN) : ID(E);
+ IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) {
if (is_all_z(cell->getPort(ID::A))) {
cell->setPort(ID::A, cell->getPort(ID::B));
- cell->setPort(en_port, cell->getPort(ID(S)));
+ cell->setPort(en_port, cell->getPort(ID::S));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
}
if (is_all_z(cell->getPort(ID::B))) {
- cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID(S))));
+ cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
- cell->unsetPort(ID(S));
+ cell->unsetPort(ID::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
SigSpec pmux_b, pmux_s;
for (auto cell : it.second) {
if (cell->type == ID($tribuf))
- pmux_s.append(cell->getPort(ID(EN)));
+ pmux_s.append(cell->getPort(ID::EN));
else
- pmux_s.append(cell->getPort(ID(E)));
+ pmux_s.append(cell->getPort(ID::E));
pmux_b.append(cell->getPort(ID::A));
module->remove(cell);
}
for (auto wire : module->selected_wires())
{
- if (wire->attributes.count(ID(init)) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const initval = wire->attributes.at(ID(init));
- wire->attributes.erase(ID(init));
+ Const initval = wire->attributes.at(ID::init);
+ wire->attributes.erase(ID::init);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
{
if (!dff_types.count(cell->type))
continue;
- SigSpec sig_d = sigmap(cell->getPort(ID(D)));
- SigSpec sig_q = sigmap(cell->getPort(ID(Q)));
+ SigSpec sig_d = sigmap(cell->getPort(ID::D));
+ SigSpec sig_q = sigmap(cell->getPort(ID::Q));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
}
Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
- initwire->attributes[ID(init)] = initval;
+ initwire->attributes[ID::init] = initval;
for (int i = 0; i < GetSize(initwire); i++)
if (initval.bits.at(i) == State::S1)
{
sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
- initwire->attributes[ID(init)].bits.at(i) = State::S0;
+ initwire->attributes[ID::init].bits.at(i) = State::S0;
}
else
{
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log_signal(sig_q), log_signal(initval));
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), initwire);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, initwire);
}
for (auto &it : initbits)
while (1)
{
- module = design->addModule("\\uut");
+ module = design->addModule(ID(UUT));
create_cycles++;
in_sig = {};
RTLIL::Module *mod = it->second;
- if (mod->get_bool_attribute("\\gentb_skip"))
+ if (mod->get_bool_attribute(ID::gentb_skip))
continue;
int count_ports = 0;
f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
} else if (wire->port_input) {
count_ports++;
- bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
+ bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock);
for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3)
for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) {
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
if (c.wire == wire)
is_clksignal = true;
}
- if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
+ if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) {
signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
} else {
signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
- if (wire->attributes.count("\\gentb_constant") != 0)
- signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
+ if (wire->attributes.count(ID::gentb_constant) != 0)
+ signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string();
}
f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
}
f << stringf("\t// $dumpvars(0, testbench);\n");
f << stringf("\tfile = $fopen(`outfile);\n");
for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it)
- if (!it->second->get_bool_attribute("\\gentb_skip"))
+ if (!it->second->get_bool_attribute(ID::gentb_skip))
f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str());
f << stringf("\t$fclose(file);\n");
f << stringf("\t$finish;\n");
static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, std::string cell_type_flags, bool constmode, bool muxdiv)
{
- RTLIL::Module *module = design->addModule("\\gold");
- RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
+ RTLIL::Module *module = design->addModule(ID(gold));
+ RTLIL::Cell *cell = module->addCell(ID(UUT), cell_type);
RTLIL::Wire *wire;
- if (cell_type.in("$mux", "$pmux"))
+ if (cell_type.in(ID($mux), ID($pmux)))
{
int width = 1 + xorshift32(8);
- int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
+ int swidth = cell_type == ID($mux) ? 1 : 1 + xorshift32(8);
wire = module->addWire(ID::A);
wire->width = width;
cell->setPort(ID::Y, wire);
}
- if (cell_type == "$fa")
+ if (cell_type == ID($fa))
{
int width = 1 + xorshift32(8);
wire->port_input = true;
cell->setPort(ID::B, wire);
- wire = module->addWire("\\C");
+ wire = module->addWire(ID::C);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\C", wire);
+ cell->setPort(ID::C, wire);
- wire = module->addWire("\\X");
+ wire = module->addWire(ID::X);
wire->width = width;
wire->port_output = true;
- cell->setPort("\\X", wire);
+ cell->setPort(ID::X, wire);
wire = module->addWire(ID::Y);
wire->width = width;
cell->setPort(ID::Y, wire);
}
- if (cell_type == "$lcu")
+ if (cell_type == ID($lcu))
{
int width = 1 + xorshift32(8);
- wire = module->addWire("\\P");
+ wire = module->addWire(ID::P);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\P", wire);
+ cell->setPort(ID::P, wire);
- wire = module->addWire("\\G");
+ wire = module->addWire(ID::G);
wire->width = width;
wire->port_input = true;
- cell->setPort("\\G", wire);
+ cell->setPort(ID::G, wire);
- wire = module->addWire("\\CI");
+ wire = module->addWire(ID::CI);
wire->port_input = true;
- cell->setPort("\\CI", wire);
+ cell->setPort(ID::CI, wire);
- wire = module->addWire("\\CO");
+ wire = module->addWire(ID::CO);
wire->width = width;
wire->port_output = true;
- cell->setPort("\\CO", wire);
+ cell->setPort(ID::CO, wire);
}
- if (cell_type == "$macc")
+ if (cell_type == ID($macc))
{
Macc macc;
int width = 1 + xorshift32(8);
macc.to_cell(cell);
}
- if (cell_type == "$lut")
+ if (cell_type == ID($lut))
{
int width = 1 + xorshift32(6);
for (int i = 0; i < (1 << width); i++)
config.append(xorshift32(2) ? State::S1 : State::S0);
- cell->setParam("\\LUT", config.as_const());
+ cell->setParam(ID::LUT, config.as_const());
}
- if (cell_type == "$sop")
+ if (cell_type == ID($sop))
{
int width = 1 + xorshift32(8);
int depth = 1 + xorshift32(8);
break;
}
- cell->setParam("\\DEPTH", depth);
- cell->setParam("\\TABLE", config.as_const());
+ cell->setParam(ID::DEPTH, depth);
+ cell->setParam(ID::TABLE, config.as_const());
}
if (cell_type_flags.find('A') != std::string::npos) {
if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
if (cell_type_flags.find('A') != std::string::npos)
- cell->parameters["\\A_SIGNED"] = true;
+ cell->parameters[ID::A_SIGNED] = true;
if (cell_type_flags.find('B') != std::string::npos)
- cell->parameters["\\B_SIGNED"] = true;
+ cell->parameters[ID::B_SIGNED] = true;
}
if (cell_type_flags.find('s') != std::string::npos) {
if (cell_type_flags.find('A') != std::string::npos && xorshift32(2))
- cell->parameters["\\A_SIGNED"] = true;
+ cell->parameters[ID::A_SIGNED] = true;
if (cell_type_flags.find('B') != std::string::npos && xorshift32(2))
- cell->parameters["\\B_SIGNED"] = true;
+ cell->parameters[ID::B_SIGNED] = true;
}
if (cell_type_flags.find('Y') != std::string::npos) {
cell->setPort(ID::Y, wire);
}
- if (muxdiv && cell_type.in("$div", "$mod")) {
+ if (muxdiv && cell_type.in(ID($div), ID($mod))) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
cell->setPort(ID::Y, div_out);
}
- if (cell_type == "$alu")
+ if (cell_type == ID($alu))
{
- wire = module->addWire("\\CI");
+ wire = module->addWire(ID::CI);
wire->port_input = true;
- cell->setPort("\\CI", wire);
+ cell->setPort(ID::CI, wire);
- wire = module->addWire("\\BI");
+ wire = module->addWire(ID::BI);
wire->port_input = true;
- cell->setPort("\\BI", wire);
+ cell->setPort(ID::BI, wire);
- wire = module->addWire("\\X");
+ wire = module->addWire(ID::X);
wire->width = GetSize(cell->getPort(ID::Y));
wire->port_output = true;
- cell->setPort("\\X", wire);
+ cell->setPort(ID::X, wire);
- wire = module->addWire("\\CO");
+ wire = module->addWire(ID::CO);
wire->width = GetSize(cell->getPort(ID::Y));
wire->port_output = true;
- cell->setPort("\\CO", wire);
+ cell->setPort(ID::CO, wire);
}
if (constmode)
{
log("Eval testing:%c", verbose ? '\n' : ' ');
- RTLIL::Module *gold_mod = design->module("\\gold");
- RTLIL::Module *gate_mod = design->module("\\gate");
+ RTLIL::Module *gold_mod = design->module(ID(gold));
+ RTLIL::Module *gate_mod = design->module(ID(gate));
ConstEval gold_ce(gold_mod), gate_ce(gate_mod);
ezSatPtr ez1, ez2;
log("Rng seed value: %d\n", int(xorshift32_state));
}
- std::map<std::string, std::string> cell_types;
- std::vector<std::string> selected_cell_types;
-
- cell_types["$not"] = "ASY";
- cell_types["$pos"] = "ASY";
- cell_types["$neg"] = "ASY";
-
- cell_types["$and"] = "ABSY";
- cell_types["$or"] = "ABSY";
- cell_types["$xor"] = "ABSY";
- cell_types["$xnor"] = "ABSY";
-
- cell_types["$reduce_and"] = "ASY";
- cell_types["$reduce_or"] = "ASY";
- cell_types["$reduce_xor"] = "ASY";
- cell_types["$reduce_xnor"] = "ASY";
- cell_types["$reduce_bool"] = "ASY";
-
- cell_types["$shl"] = "ABshY";
- cell_types["$shr"] = "ABshY";
- cell_types["$sshl"] = "ABshY";
- cell_types["$sshr"] = "ABshY";
- cell_types["$shift"] = "ABshY";
- cell_types["$shiftx"] = "ABshY";
-
- cell_types["$lt"] = "ABSY";
- cell_types["$le"] = "ABSY";
- cell_types["$eq"] = "ABSY";
- cell_types["$ne"] = "ABSY";
- // cell_types["$eqx"] = "ABSY";
- // cell_types["$nex"] = "ABSY";
- cell_types["$ge"] = "ABSY";
- cell_types["$gt"] = "ABSY";
-
- cell_types["$add"] = "ABSY";
- cell_types["$sub"] = "ABSY";
- cell_types["$mul"] = "ABSY";
- cell_types["$div"] = "ABSY";
- cell_types["$mod"] = "ABSY";
- // cell_types["$pow"] = "ABsY";
-
- cell_types["$logic_not"] = "ASY";
- cell_types["$logic_and"] = "ABSY";
- cell_types["$logic_or"] = "ABSY";
+ std::map<IdString, std::string> cell_types;
+ std::vector<IdString> selected_cell_types;
+
+ cell_types[ID($not)] = "ASY";
+ cell_types[ID($pos)] = "ASY";
+ cell_types[ID($neg)] = "ASY";
+
+ cell_types[ID($and)] = "ABSY";
+ cell_types[ID($or)] = "ABSY";
+ cell_types[ID($xor)] = "ABSY";
+ cell_types[ID($xnor)] = "ABSY";
+
+ cell_types[ID($reduce_and)] = "ASY";
+ cell_types[ID($reduce_or)] = "ASY";
+ cell_types[ID($reduce_xor)] = "ASY";
+ cell_types[ID($reduce_xnor)] = "ASY";
+ cell_types[ID($reduce_bool)] = "ASY";
+
+ cell_types[ID($shl)] = "ABshY";
+ cell_types[ID($shr)] = "ABshY";
+ cell_types[ID($sshl)] = "ABshY";
+ cell_types[ID($sshr)] = "ABshY";
+ cell_types[ID($shift)] = "ABshY";
+ cell_types[ID($shiftx)] = "ABshY";
+
+ cell_types[ID($lt)] = "ABSY";
+ cell_types[ID($le)] = "ABSY";
+ cell_types[ID($eq)] = "ABSY";
+ cell_types[ID($ne)] = "ABSY";
+ // cell_types[ID($eqx)] = "ABSY";
+ // cell_types[ID($nex)] = "ABSY";
+ cell_types[ID($ge)] = "ABSY";
+ cell_types[ID($gt)] = "ABSY";
+
+ cell_types[ID($add)] = "ABSY";
+ cell_types[ID($sub)] = "ABSY";
+ cell_types[ID($mul)] = "ABSY";
+ cell_types[ID($div)] = "ABSY";
+ cell_types[ID($mod)] = "ABSY";
+ // cell_types[ID($pow)] = "ABsY";
+
+ cell_types[ID($logic_not)] = "ASY";
+ cell_types[ID($logic_and)] = "ABSY";
+ cell_types[ID($logic_or)] = "ABSY";
if (edges) {
- cell_types["$mux"] = "*";
- cell_types["$pmux"] = "*";
+ cell_types[ID($mux)] = "*";
+ cell_types[ID($pmux)] = "*";
}
- // cell_types["$slice"] = "A";
- // cell_types["$concat"] = "A";
+ // cell_types[ID($slice)] = "A";
+ // cell_types[ID($concat)] = "A";
- cell_types["$lut"] = "*";
- cell_types["$sop"] = "*";
- cell_types["$alu"] = "ABSY";
- cell_types["$lcu"] = "*";
- cell_types["$macc"] = "*";
- cell_types["$fa"] = "*";
+ cell_types[ID($lut)] = "*";
+ cell_types[ID($sop)] = "*";
+ cell_types[ID($alu)] = "ABSY";
+ cell_types[ID($lcu)] = "*";
+ cell_types[ID($macc)] = "*";
+ cell_types[ID($fa)] = "*";
for (; argidx < GetSize(args); argidx++)
{
}
if (args[argidx].compare(0, 1, "/") == 0) {
- std::vector<std::string> new_selected_cell_types;
+ std::vector<IdString> new_selected_cell_types;
for (auto it : selected_cell_types)
if (it != args[argidx].substr(1))
new_selected_cell_types.push_back(it);
int charcount = 100;
for (auto &it : cell_types) {
if (charcount > 60) {
- cell_type_list += "\n" + it.first;
+ cell_type_list += stringf("\n%s", + log_id(it.first));
charcount = 0;
} else
- cell_type_list += " " + it.first;
+ cell_type_list += stringf(" %s", log_id(it.first));
charcount += GetSize(it.first);
}
log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
{
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\AL_MAP_LUT1")
+ if (cell->type == ID(AL_MAP_LUT1))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),1));
cnt++;
}
- if (cell->type == "\\AL_MAP_LUT2")
+ if (cell->type == ID(AL_MAP_LUT2))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),2));
cnt++;
}
- if (cell->type == "\\AL_MAP_LUT3")
+ if (cell->type == ID(AL_MAP_LUT3))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),3));
cnt++;
}
- if (cell->type == "\\AL_MAP_LUT4")
+ if (cell->type == ID(AL_MAP_LUT4))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),4));
cnt++;
}
- if (cell->type == "\\AL_MAP_LUT5")
+ if (cell->type == ID(AL_MAP_LUT5))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),5));
cnt++;
}
- if (cell->type == "\\AL_MAP_LUT6")
+ if (cell->type == ID(AL_MAP_LUT6))
{
- cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6));
+ cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),6));
cnt++;
}
}
for (auto cell : module->cells())
{
- if (cell->type == "\\AL_MAP_ADDER") {
- if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
- SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
- SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
+ if (cell->type == ID(AL_MAP_ADDER)) {
+ if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
- SigSpec o = cell->getPort("\\o");
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
+ SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
- if (cell->type == "\\AL_MAP_ADDER") {
- if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
- SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
- SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
+ if (cell->type == ID(AL_MAP_ADDER)) {
+ if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
for (auto cell : adders_to_fix_cells)
{
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
- Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
+ Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);
SigSpec bits;
bits.append(dummy_bit);
bits.append(new_bit);
- c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
- c->setPort("\\a", bit);
- c->setPort("\\b", State::S0);
- c->setPort("\\c", State::S0);
- c->setPort("\\o", bits);
+ c->setParam(ID(ALUTYPE), Const("ADD_CARRY"));
+ c->setPort(ID(a), bit);
+ c->setPort(ID(b), State::S0);
+ c->setPort(ID(c), State::S0);
+ c->setPort(ID(o), bits);
- cell->setPort("\\c", new_bit);
+ cell->setPort(ID(c), new_bit);
}
}
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", true);
- xor_cell->setPort("\\OUT", outwire);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), true);
+ xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(false))
{
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", false);
- xor_cell->setPort("\\OUT", outwire);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), false);
+ xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(RTLIL::State::Sx))
{
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", false);
- xor_cell->setPort("\\OUT", outwire);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), false);
+ xor_cell->setPort(ID(OUT), outwire);
}
else
{
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
- "\\ANDTERM");
- and_cell->setParam("\\TRUE_INP", 1);
- and_cell->setParam("\\COMP_INP", 0);
- and_cell->setPort("\\OUT", and_to_xor_wire);
- and_cell->setPort("\\IN", inwire);
- and_cell->setPort("\\IN_B", SigSpec());
+ ID(ANDTERM));
+ and_cell->setParam(ID(TRUE_INP), 1);
+ and_cell->setParam(ID(COMP_INP), 0);
+ and_cell->setPort(ID(OUT), and_to_xor_wire);
+ and_cell->setPort(ID(IN), inwire);
+ and_cell->setPort(ID(IN_B), SigSpec());
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", false);
- xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
- xor_cell->setPort("\\OUT", outwire);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), false);
+ xor_cell->setPort(ID(IN_PTC), and_to_xor_wire);
+ xor_cell->setPort(ID(OUT), outwire);
}
return outwire;
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
- "\\ANDTERM");
- and_cell->setParam("\\TRUE_INP", 1);
- and_cell->setParam("\\COMP_INP", 0);
- and_cell->setPort("\\OUT", outwire);
- and_cell->setPort("\\IN", inwire);
- and_cell->setPort("\\IN_B", SigSpec());
+ ID(ANDTERM));
+ and_cell->setParam(ID(TRUE_INP), 1);
+ and_cell->setParam(ID(COMP_INP), 0);
+ and_cell->setPort(ID(OUT), outwire);
+ and_cell->setPort(ID(IN), inwire);
+ and_cell->setPort(ID(IN_B), SigSpec());
return outwire;
}
pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells())
{
- if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
- "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
+ ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
- auto output = sigmap(cell->getPort("\\Q")[0]);
+ auto output = sigmap(cell->getPort(ID::Q)[0]);
sig_fed_by_ff.insert(output);
}
}
pool<SigBit> sig_fed_by_xor;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\MACROCELL_XOR")
+ if (cell->type == ID(MACROCELL_XOR))
{
- auto output = sigmap(cell->getPort("\\OUT")[0]);
+ auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_xor.insert(output);
}
}
pool<SigBit> sig_fed_by_io;
for (auto cell : module->selected_cells())
{
- if (cell->type.in("\\IBUF", "\\IOBUFE"))
+ if (cell->type.in(ID(IBUF), ID(IOBUFE)))
{
- if (cell->hasPort("\\O")) {
- auto output = sigmap(cell->getPort("\\O")[0]);
+ if (cell->hasPort(ID::O)) {
+ auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_io.insert(output);
}
}
pool<SigBit> sig_fed_by_pterm;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\ANDTERM")
+ if (cell->type == ID(ANDTERM))
{
- auto output = sigmap(cell->getPort("\\OUT")[0]);
+ auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_pterm.insert(output);
}
}
pool<SigBit> sig_fed_by_bufg;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\BUFG")
+ if (cell->type == ID(BUFG))
{
- auto output = sigmap(cell->getPort("\\O")[0]);
+ auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufg.insert(output);
}
}
pool<SigBit> sig_fed_by_bufgsr;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\BUFGSR")
+ if (cell->type == ID(BUFGSR))
{
- auto output = sigmap(cell->getPort("\\O")[0]);
+ auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgsr.insert(output);
}
}
pool<SigBit> sig_fed_by_bufgts;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\BUFGTS")
+ if (cell->type == ID(BUFGTS))
{
- auto output = sigmap(cell->getPort("\\O")[0]);
+ auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgts.insert(output);
}
}
pool<SigBit> sig_fed_by_ibuf;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\IBUF")
+ if (cell->type == ID(IBUF))
{
- auto output = sigmap(cell->getPort("\\O")[0]);
+ auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_ibuf.insert(output);
}
}
// the pad-to-zia path has to be used up and the register
// can't be packed with the ibuf.
if (fanout_count == 1 && maybe_ff_cell->type.in(
- "\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
- "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
+ ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit input;
- if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
- input = sigmap(maybe_ff_cell->getPort("\\T")[0]);
+ if (maybe_ff_cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
+ input = sigmap(maybe_ff_cell->getPort(ID::T)[0]);
else
- input = sigmap(maybe_ff_cell->getPort("\\D")[0]);
- SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]);
+ input = sigmap(maybe_ff_cell->getPort(ID::D)[0]);
+ SigBit output = sigmap(maybe_ff_cell->getPort(ID::Q)[0]);
if (input == ibuf_out_wire)
{
for (auto cell : module->selected_cells())
{
- if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
- "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
+ ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
// Buffering FF inputs. FF inputs can only come from either
// an IO pin or from an XOR. Otherwise AND/XOR cells need
// to be inserted.
SigBit input;
- if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
- input = sigmap(cell->getPort("\\T")[0]);
+ if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
+ input = sigmap(cell->getPort(ID::T)[0]);
else
- input = sigmap(cell->getPort("\\D")[0]);
+ input = sigmap(cell->getPort(ID::D)[0]);
// If the input wasn't an XOR nor an IO, then a buffer
// definitely needs to be added.
auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
- if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
- cell->setPort("\\T", xor_to_ff_wire);
+ if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
+ cell->setPort(ID::T, xor_to_ff_wire);
else
- cell->setPort("\\D", xor_to_ff_wire);
+ cell->setPort(ID::D, xor_to_ff_wire);
}
// Buffering FF clocks. FF clocks can only come from either
// in coolrunner2_sop (e.g. if clock is generated from
// AND-ing two signals) but not in all cases.
SigBit clock;
- if (cell->type.in("\\LDCP", "\\LDCP_N"))
- clock = sigmap(cell->getPort("\\G")[0]);
+ if (cell->type.in(ID(LDCP), ID(LDCP_N)))
+ clock = sigmap(cell->getPort(ID::G)[0]);
else
- clock = sigmap(cell->getPort("\\C")[0]);
+ clock = sigmap(cell->getPort(ID::C)[0]);
if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
{
auto pterm_to_ff_wire = makeptermbuffer(module, clock);
- if (cell->type.in("\\LDCP", "\\LDCP_N"))
- cell->setPort("\\G", pterm_to_ff_wire);
+ if (cell->type.in(ID(LDCP), ID(LDCP_N)))
+ cell->setPort(ID::G, pterm_to_ff_wire);
else
- cell->setPort("\\C", pterm_to_ff_wire);
+ cell->setPort(ID::C, pterm_to_ff_wire);
}
// Buffering FF set/reset. This can only come from either
// a pterm or a bufgsr.
SigBit set;
- set = sigmap(cell->getPort("\\PRE")[0]);
+ set = sigmap(cell->getPort(ID(PRE))[0]);
if (set != SigBit(false))
{
if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
auto pterm_to_ff_wire = makeptermbuffer(module, set);
- cell->setPort("\\PRE", pterm_to_ff_wire);
+ cell->setPort(ID(PRE), pterm_to_ff_wire);
}
}
SigBit reset;
- reset = sigmap(cell->getPort("\\CLR")[0]);
+ reset = sigmap(cell->getPort(ID::CLR)[0]);
if (reset != SigBit(false))
{
if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
auto pterm_to_ff_wire = makeptermbuffer(module, reset);
- cell->setPort("\\CLR", pterm_to_ff_wire);
+ cell->setPort(ID::CLR, pterm_to_ff_wire);
}
}
// Buffering FF clock enable
// FIXME: This doesn't fully fix PTC conflicts
// FIXME: Need to ensure constant enables are optimized out
- if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
+ if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit ce;
- ce = sigmap(cell->getPort("\\CE")[0]);
+ ce = sigmap(cell->getPort(ID(CE))[0]);
if (!sig_fed_by_pterm[ce])
{
log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, ce);
- cell->setPort("\\CE", pterm_to_ff_wire);
+ cell->setPort(ID(CE), pterm_to_ff_wire);
}
}
}
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\IOBUFE")
+ if (cell->type == ID(IOBUFE))
{
// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
- SigBit input = sigmap(cell->getPort("\\I")[0]);
+ SigBit input = sigmap(cell->getPort(ID::I)[0]);
if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
packed_reg_out[input])
auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
- cell->setPort("\\I", xor_to_io_wire);
+ cell->setPort(ID::I, xor_to_io_wire);
}
// Buffer IOBUFE enables. This can only be fed from a pterm
// or a bufgts.
- if (cell->hasPort("\\E"))
+ if (cell->hasPort(ID::E))
{
SigBit oe;
- oe = sigmap(cell->getPort("\\E")[0]);
+ oe = sigmap(cell->getPort(ID::E)[0]);
if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
{
log("Buffering output enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_oe_wire = makeptermbuffer(module, oe);
- cell->setPort("\\E", pterm_to_oe_wire);
+ cell->setPort(ID::E, pterm_to_oe_wire);
}
}
}
dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\MACROCELL_XOR")
+ if (cell->type == ID(MACROCELL_XOR))
{
- auto output = sigmap(cell->getPort("\\OUT")[0]);
+ auto output = sigmap(cell->getPort(ID(OUT))[0]);
xor_out_to_xor_cell[output] = cell;
}
}
pool<SigBit> xor_fanout_once;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\ANDTERM")
+ if (cell->type == ID(ANDTERM))
continue;
for (auto &conn : cell->connections())
module->uniquify(xor_cell->name), xor_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
- new_xor_cell->setPort("\\OUT", new_wire);
+ new_xor_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
xor_fanout_once.insert(wire_in);
dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\ORTERM")
+ if (cell->type == ID(ORTERM))
{
- auto output = sigmap(cell->getPort("\\OUT")[0]);
+ auto output = sigmap(cell->getPort(ID(OUT))[0]);
or_out_to_or_cell[output] = cell;
}
}
module->uniquify(or_cell->name), or_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
- new_or_cell->setPort("\\OUT", new_wire);
+ new_or_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
or_fanout_once.insert(wire_in);
dict<SigBit, tuple<SigBit, Cell*>> not_cells;
for (auto cell : module->selected_cells())
{
- if (cell->type == "$_NOT_")
+ if (cell->type == ID($_NOT_))
{
auto not_input = sigmap(cell->getPort(ID::A)[0]);
auto not_output = sigmap(cell->getPort(ID::Y)[0]);
}
// Find wires that need to become special product terms
- dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
- dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
+ dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv;
+ dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv;
for (auto cell : module->selected_cells())
{
- if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
- "\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
+ if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
+ ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
{
- if (cell->hasPort("\\PRE"))
- special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
- tuple<Cell*, const char *>(cell, "\\PRE"));
- if (cell->hasPort("\\CLR"))
- special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
- tuple<Cell*, const char *>(cell, "\\CLR"));
- if (cell->hasPort("\\CE"))
- special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
- tuple<Cell*, const char *>(cell, "\\CE"));
-
- if (cell->hasPort("\\C"))
- special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
- tuple<Cell*, const char *>(cell, "\\C"));
- if (cell->hasPort("\\G"))
- special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
- tuple<Cell*, const char *>(cell, "\\G"));
+ if (cell->hasPort(ID(PRE)))
+ special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
+ make_tuple(cell, ID(PRE)));
+ if (cell->hasPort(ID::CLR))
+ special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert(
+ make_tuple(cell, ID::CLR));
+ if (cell->hasPort(ID(CE)))
+ special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
+ make_tuple(cell, ID(CE)));
+
+ if (cell->hasPort(ID::C))
+ special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert(
+ make_tuple(cell, ID::C));
+ if (cell->hasPort(ID::G))
+ special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert(
+ make_tuple(cell, ID::G));
}
}
// Process $sop cells
for (auto cell : module->selected_cells())
{
- if (cell->type == "$sop")
+ if (cell->type == ID($sop))
{
// Read the inputs/outputs/parameters of the $sop cell
auto sop_inputs = sigmap(cell->getPort(ID::A));
auto sop_output = sigmap(cell->getPort(ID::Y))[0];
- auto sop_depth = cell->getParam("\\DEPTH").as_int();
- auto sop_width = cell->getParam("\\WIDTH").as_int();
- auto sop_table = cell->getParam("\\TABLE");
+ auto sop_depth = cell->getParam(ID::DEPTH).as_int();
+ auto sop_width = cell->getParam(ID::WIDTH).as_int();
+ auto sop_table = cell->getParam(ID::TABLE);
auto sop_output_wire_name = sop_output.wire->name.c_str();
// Construct the cell
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
- "\\ANDTERM");
- and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
- and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
- and_cell->setPort("\\OUT", and_out);
- and_cell->setPort("\\IN", and_in_true);
- and_cell->setPort("\\IN_B", and_in_comp);
+ ID(ANDTERM));
+ and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
+ and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
+ and_cell->setPort(ID(OUT), and_out);
+ and_cell->setPort(ID(IN), and_in_true);
+ and_cell->setPort(ID(IN_B), and_in_comp);
}
if (sop_depth == 1)
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", has_invert);
- xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
- xor_cell->setPort("\\OUT", sop_output);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), has_invert);
+ xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
+ xor_cell->setPort(ID(OUT), sop_output);
// Special P-term handling
if (is_special_pterm)
{
// Can always connect the P-term directly if it's going
// into something invert-capable
- for (auto x : special_pterms_inv[sop_output])
+ for (const auto &x : special_pterms_inv[sop_output])
{
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
if (has_invert)
{
auto cell = std::get<0>(x);
- if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
- else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
- else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
- else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
- else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
- else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
- else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
- else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
+ if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
+ else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
+ else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
+ else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
+ else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
+ else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
+ else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
+ else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
else log_assert(!"Internal error! Bad cell type!");
}
}
// Construct the OR cell
auto or_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
- "\\ORTERM");
- or_cell->setParam("\\WIDTH", sop_depth);
- or_cell->setPort("\\IN", intermed_wires);
- or_cell->setPort("\\OUT", or_to_xor_wire);
+ ID(ORTERM));
+ or_cell->setParam(ID::WIDTH, sop_depth);
+ or_cell->setPort(ID(IN), intermed_wires);
+ or_cell->setPort(ID(OUT), or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
- "\\MACROCELL_XOR");
- xor_cell->setParam("\\INVERT_OUT", has_invert);
- xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
- xor_cell->setPort("\\OUT", sop_output);
+ ID(MACROCELL_XOR));
+ xor_cell->setParam(ID(INVERT_OUT), has_invert);
+ xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
+ xor_cell->setPort(ID(OUT), sop_output);
}
// Finally, remove the $sop cell
for (auto wire : module->selected_wires())
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
}
for (auto cell : module->selected_cells())
{
- if (cell->type != "\\TRELLIS_FF")
+ if (cell->type != ID(TRELLIS_FF))
continue;
- SigSpec sig_d = cell->getPort("\\DI");
- SigSpec sig_q = cell->getPort("\\Q");
- SigSpec sig_lsr = cell->getPort("\\LSR");
+ SigSpec sig_d = cell->getPort(ID(DI));
+ SigSpec sig_q = cell->getPort(ID::Q);
+ SigSpec sig_lsr = cell->getPort(ID(LSR));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
SigBit bit_q = sigmap(sig_q[0]);
std::string regset = "RESET";
- if (cell->hasParam("\\REGSET"))
- regset = cell->getParam("\\REGSET").decode_string();
+ if (cell->hasParam(ID(REGSET)))
+ regset = cell->getParam(ID(REGSET)).decode_string();
State resetState;
if (regset == "SET")
resetState = State::S1;
if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
std::string srmode = "LSR_OVER_CE";
- if (cell->hasParam("\\SRMODE"))
- srmode = cell->getParam("\\SRMODE").decode_string();
+ if (cell->hasParam(ID(SRMODE)))
+ srmode = cell->getParam(ID(SRMODE)).decode_string();
if (srmode == "ASYNC") {
log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
}
- cell->setPort("\\DI", new_bit_d);
- cell->setPort("\\LSR", State::S0);
+ cell->setPort(ID(DI), new_bit_d);
+ cell->setPort(ID(LSR), State::S0);
- if(cell->hasPort("\\CE")) {
+ if(cell->hasPort(ID(CE))) {
std::string cemux = "CE";
- if (cell->hasParam("\\CEMUX"))
- cemux = cell->getParam("\\CEMUX").decode_string();
- SigSpec sig_ce = cell->getPort("\\CE");
+ if (cell->hasParam(ID(CEMUX)))
+ cemux = cell->getParam(ID(CEMUX)).decode_string();
+ SigSpec sig_ce = cell->getPort(ID(CE));
if (GetSize(sig_ce) >= 1) {
SigBit bit_ce = sigmap(sig_ce[0]);
Wire *new_bit_ce = module->addWire(NEW_ID);
module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
else
module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
- cell->setPort("\\CE", new_bit_ce);
+ cell->setPort(ID(CE), new_bit_ce);
}
}
- cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
} else {
- cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+ cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
handled_initbits.insert(bit_q);
}
}
for (auto wire : init_wires)
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const &initval = wire->attributes.at("\\init");
+ Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
}
if (remove_attribute)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
}
}
continue;
bool gsren = found_gsr;
- if (cell->get_bool_attribute("\\nogsr"))
+ if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
{
if (cell->type != ID($_NOT_))
continue;
- SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
+ SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y);
if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
continue;
SigBit a = sigmap(sig_a[0]);
for (auto cell : module->cells())
{
- if (cell->type == "\\EFX_ADD") {
- SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
- SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
+ if (cell->type == ID(EFX_ADD)) {
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
- SigBit bit_o = sigmap(cell->getPort("\\O"));
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
+ SigBit bit_o = sigmap(cell->getPort(ID::O));
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
- if (cell->type == "\\EFX_ADD") {
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
- SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\I0"));
- SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\I1"));
+ if (cell->type == ID(EFX_ADD)) {
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
+ SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(I0)));
+ SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
for (auto cell : adders_to_fix_cells)
{
- SigBit bit_ci = get_bit_or_zero(cell->getPort("\\CI"));
+ SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
- Cell *c = module->addCell(NEW_ID, "\\EFX_ADD");
+ Cell *c = module->addCell(NEW_ID, ID(EFX_ADD));
SigBit new_bit = module->addWire(NEW_ID);
- c->setParam("\\I0_POLARITY", State::S1);
- c->setParam("\\I1_POLARITY", State::S1);
- c->setPort("\\I0", bit);
- c->setPort("\\I1", State::S1);
- c->setPort("\\CI", State::S0);
- c->setPort("\\CO", new_bit);
+ c->setParam(ID(I0_POLARITY), State::S1);
+ c->setParam(ID(I1_POLARITY), State::S1);
+ c->setPort(ID(I0), bit);
+ c->setPort(ID(I1), State::S1);
+ c->setPort(ID::CI, State::S0);
+ c->setPort(ID::CO, new_bit);
- cell->setPort("\\CI", new_bit);
+ cell->setPort(ID::CI, new_bit);
}
}
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- log_header(design, "Executing efinix_fixcarry pass (fix invalid carry chain).\n");
+ log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
for (auto cell : module->cells())
{
- if (cell->type == "\\EFX_FF") {
- for (auto bit : sigmap(cell->getPort("\\CLK")))
+ if (cell->type == ID(EFX_FF)) {
+ for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
- if (cell->type == "\\EFX_RAM_5K") {
- for (auto bit : sigmap(cell->getPort("\\RCLK")))
+ if (cell->type == ID(EFX_RAM_5K)) {
+ for (auto bit : sigmap(cell->getPort(ID(RCLK))))
clk_bits.insert(bit);
- for (auto bit : sigmap(cell->getPort("\\WCLK")))
+ for (auto bit : sigmap(cell->getPort(ID(WCLK))))
clk_bits.insert(bit);
}
}
if (!clk_bits.count(canonical_bit))
continue;
- Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
+ Cell *c = module->addCell(NEW_ID, ID(EFX_GBUFCE));
SigBit new_bit = module->addWire(NEW_ID);
- c->setParam("\\CE_POLARITY", State::S1);
- c->setPort("\\O", new_bit);
- c->setPort("\\CE", State::S1);
+ c->setParam(ID(CE_POLARITY), State::S1);
+ c->setPort(ID::O, new_bit);
+ c->setPort(ID(CE), State::S1);
pad_bits.push_back(make_pair(c, bit));
rewrite_bits[canonical_bit] = new_bit;
module->rewrite_sigspecs(rewrite_function);
for (auto &it : pad_bits)
- it.first->setPort("\\I", it.second);
+ it.first->setPort(ID::I, it.second);
}
struct EfinixGbufPass : public Pass {
{
for (auto cell : module->selected_cells())
{
- if (cell->type == "\\RAM16S4")
+ if (cell->type == ID(RAM16S4))
{
- cell->setParam("\\INIT_0", determine_init(cell->getParam("\\INIT_0")));
- cell->setParam("\\INIT_1", determine_init(cell->getParam("\\INIT_1")));
- cell->setParam("\\INIT_2", determine_init(cell->getParam("\\INIT_2")));
- cell->setParam("\\INIT_3", determine_init(cell->getParam("\\INIT_3")));
+ cell->setParam(ID(INIT_0), determine_init(cell->getParam(ID(INIT_0))));
+ cell->setParam(ID(INIT_1), determine_init(cell->getParam(ID(INIT_1))));
+ cell->setParam(ID(INIT_2), determine_init(cell->getParam(ID(INIT_2))));
+ cell->setParam(ID(INIT_3), determine_init(cell->getParam(ID(INIT_3))));
cnt++;
}
}
if (!invert_input)
{
- Const initval = cell->getParam("\\INIT");
+ Const initval = cell->getParam(ID::INIT);
if (GetSize(initval) >= 1) {
if (initval.bits[0] == State::S0)
initval.bits[0] = State::S1;
else if (initval.bits[0] == State::S1)
initval.bits[0] = State::S0;
- cell->setParam("\\INIT", initval);
+ cell->setParam(ID::INIT, initval);
}
if (cell_type_r && cell_type_s)
{
- Const srmode = cell->getParam("\\SRMODE");
+ Const srmode = cell->getParam(ID(SRMODE));
if (GetSize(srmode) >= 1) {
if (srmode.bits[0] == State::S0)
srmode.bits[0] = State::S1;
else if (srmode.bits[0] == State::S1)
srmode.bits[0] = State::S0;
- cell->setParam("\\SRMODE", srmode);
+ cell->setParam(ID(SRMODE), srmode);
}
}
else
{
if (cell_type_r) {
- cell->setPort("\\nSET", cell->getPort("\\nRST"));
- cell->unsetPort("\\nRST");
+ cell->setPort(ID(nSET), cell->getPort(ID(nRST)));
+ cell->unsetPort(ID(nRST));
cell_type_r = false;
cell_type_s = true;
} else
if (cell_type_s) {
- cell->setPort("\\nRST", cell->getPort("\\nSET"));
- cell->unsetPort("\\nSET");
+ cell->setPort(ID(nRST), cell->getPort(ID(nSET)));
+ cell->unsetPort(ID(nSET));
cell_type_r = true;
cell_type_s = false;
}
}
if (cell_type_i) {
- cell->setPort("\\Q", cell->getPort("\\nQ"));
- cell->unsetPort("\\nQ");
+ cell->setPort(ID::Q, cell->getPort(ID(nQ)));
+ cell->unsetPort(ID(nQ));
cell_type_i = false;
} else {
- cell->setPort("\\nQ", cell->getPort("\\Q"));
- cell->unsetPort("\\Q");
+ cell->setPort(ID(nQ), cell->getPort(ID::Q));
+ cell->unsetPort(ID::Q);
cell_type_i = true;
}
extra_args(args, argidx, design);
pool<IdString> gp_dff_types;
- gp_dff_types.insert("\\GP_DFF");
- gp_dff_types.insert("\\GP_DFFI");
- gp_dff_types.insert("\\GP_DFFR");
- gp_dff_types.insert("\\GP_DFFRI");
- gp_dff_types.insert("\\GP_DFFS");
- gp_dff_types.insert("\\GP_DFFSI");
- gp_dff_types.insert("\\GP_DFFSR");
- gp_dff_types.insert("\\GP_DFFSRI");
-
- gp_dff_types.insert("\\GP_DLATCH");
- gp_dff_types.insert("\\GP_DLATCHI");
- gp_dff_types.insert("\\GP_DLATCHR");
- gp_dff_types.insert("\\GP_DLATCHRI");
- gp_dff_types.insert("\\GP_DLATCHS");
- gp_dff_types.insert("\\GP_DLATCHSI");
- gp_dff_types.insert("\\GP_DLATCHSR");
- gp_dff_types.insert("\\GP_DLATCHSRI");
+ gp_dff_types.insert(ID(GP_DFF));
+ gp_dff_types.insert(ID(GP_DFFI));
+ gp_dff_types.insert(ID(GP_DFFR));
+ gp_dff_types.insert(ID(GP_DFFRI));
+ gp_dff_types.insert(ID(GP_DFFS));
+ gp_dff_types.insert(ID(GP_DFFSI));
+ gp_dff_types.insert(ID(GP_DFFSR));
+ gp_dff_types.insert(ID(GP_DFFSRI));
+
+ gp_dff_types.insert(ID(GP_DLATCH));
+ gp_dff_types.insert(ID(GP_DLATCHI));
+ gp_dff_types.insert(ID(GP_DLATCHR));
+ gp_dff_types.insert(ID(GP_DLATCHRI));
+ gp_dff_types.insert(ID(GP_DLATCHS));
+ gp_dff_types.insert(ID(GP_DLATCHSI));
+ gp_dff_types.insert(ID(GP_DLATCHSR));
+ gp_dff_types.insert(ID(GP_DLATCHSRI));
for (auto module : design->selected_modules())
{
continue;
}
- if (cell->type == "\\GP_INV") {
- SigBit in_bit = sigmap(cell->getPort("\\IN"));
- SigBit out_bit = sigmap(cell->getPort("\\OUT"));
+ if (cell->type == ID(GP_INV)) {
+ SigBit in_bit = sigmap(cell->getPort(ID(IN)));
+ SigBit out_bit = sigmap(cell->getPort(ID(OUT)));
inv_in2out[in_bit] = out_bit;
inv_out2in[out_bit] = in_bit;
inv_in2cell[in_bit] = cell;
for (auto cell : dff_cells)
{
- SigBit d_bit = sigmap(cell->getPort("\\D"));
- SigBit q_bit = sigmap(cell->hasPort("\\Q") ? cell->getPort("\\Q") : cell->getPort("\\nQ"));
+ SigBit d_bit = sigmap(cell->getPort(ID::D));
+ SigBit q_bit = sigmap(cell->hasPort(ID::Q) ? cell->getPort(ID::Q) : cell->getPort(ID(nQ)));
while (inv_out2in.count(d_bit))
{
sig_use_cnt[d_bit]--;
invert_gp_dff(cell, true);
d_bit = inv_out2in.at(d_bit);
- cell->setPort("\\D", d_bit);
+ cell->setPort(ID::D, d_bit);
sig_use_cnt[d_bit]++;
}
inv_in2cell.erase(q_bit);
invert_gp_dff(cell, false);
- if (cell->hasPort("\\Q"))
- cell->setPort("\\Q", new_q_bit);
+ if (cell->hasPort(ID::Q))
+ cell->setPort(ID::Q, new_q_bit);
else
- cell->setPort("\\nQ", new_q_bit);
+ cell->setPort(ID(nQ), new_q_bit);
}
}
}
uint16_t mem[256];
/* Only consider cells we're interested in */
- if (cell->type != "\\SB_RAM40_4K" &&
- cell->type != "\\SB_RAM40_4KNR" &&
- cell->type != "\\SB_RAM40_4KNW" &&
- cell->type != "\\SB_RAM40_4KNRNW")
+ if (cell->type != ID(SB_RAM40_4K) &&
+ cell->type != ID(SB_RAM40_4KNR) &&
+ cell->type != ID(SB_RAM40_4KNW) &&
+ cell->type != ID(SB_RAM40_4KNRNW))
continue;
- if (!cell->hasParam("\\INIT_FILE"))
+ if (!cell->hasParam(ID(INIT_FILE)))
continue;
- std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
- cell->unsetParam("\\INIT_FILE");
+ std::string init_file = cell->getParam(ID(INIT_FILE)).decode_string();
+ cell->unsetParam(ID(INIT_FILE));
if (init_file == "")
continue;
for (auto wire : module->selected_wires())
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
+ Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
}
pool<IdString> sb_dff_types = {
- "\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR",
- "\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR",
- "\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
+ ID(SB_DFF), ID(SB_DFFE), ID(SB_DFFSR), ID(SB_DFFR), ID(SB_DFFSS), ID(SB_DFFS), ID(SB_DFFESR),
+ ID(SB_DFFER), ID(SB_DFFESS), ID(SB_DFFES), ID(SB_DFFN), ID(SB_DFFNE), ID(SB_DFFNSR), ID(SB_DFFNR),
+ ID(SB_DFFNSS), ID(SB_DFFNS), ID(SB_DFFNESR), ID(SB_DFFNER), ID(SB_DFFNESS), ID(SB_DFFNES)
};
for (auto cell : module->selected_cells())
if (!sb_dff_types.count(cell->type))
continue;
- SigSpec sig_d = cell->getPort("\\D");
- SigSpec sig_q = cell->getPort("\\Q");
+ SigSpec sig_d = cell->getPort(ID::D);
+ SigSpec sig_q = cell->getPort(ID::Q);
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
- cell->setPort("\\R", cell->getPort(ID::S));
+ cell->setPort(ID::R, cell->getPort(ID::S));
cell->unsetPort(ID::S);
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
- cell->setPort(ID::S, cell->getPort("\\R"));
- cell->unsetPort("\\R");
+ cell->setPort(ID::S, cell->getPort(ID::R));
+ cell->unsetPort(ID::R);
}
Wire *new_bit_d = module->addWire(NEW_ID);
module->addNotGate(NEW_ID, bit_d, new_bit_d);
module->addNotGate(NEW_ID, new_bit_q, bit_q);
- cell->setPort("\\D", new_bit_d);
- cell->setPort("\\Q", new_bit_q);
+ cell->setPort(ID::D, new_bit_d);
+ cell->setPort(ID::Q, new_bit_q);
}
for (auto wire : init_wires)
{
- if (wire->attributes.count("\\init") == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
- Const &initval = wire->attributes.at("\\init");
+ Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
}
if (remove_attribute)
- wire->attributes.erase("\\init");
+ wire->attributes.erase(ID::init);
}
}
}
extra_args(args, argidx, design);
pool<IdString> sb_dff_types;
- sb_dff_types.insert("\\SB_DFF");
- sb_dff_types.insert("\\SB_DFFE");
- sb_dff_types.insert("\\SB_DFFN");
- sb_dff_types.insert("\\SB_DFFNE");
+ sb_dff_types.insert(ID(SB_DFF));
+ sb_dff_types.insert(ID(SB_DFFE));
+ sb_dff_types.insert(ID(SB_DFFN));
+ sb_dff_types.insert(ID(SB_DFFNE));
for (auto module : design->selected_modules())
{
continue;
}
- if (cell->type != "$_MUX_")
+ if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort(ID::A));
for (auto cell : ff_cells)
{
- if (cell->get_bool_attribute("\\dont_touch"))
+ if (cell->get_bool_attribute(ID(dont_touch)))
continue;
- SigSpec sig_d = cell->getPort("\\D");
+ SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
cell->setPort(ID::S, sr_sig);
- cell->setPort("\\D", bit_d);
+ cell->setPort(ID::D, bit_d);
} else {
cell->type = cell->type.str() + "SR";
- cell->setPort("\\R", sr_sig);
- cell->setPort("\\D", bit_d);
+ cell->setPort(ID::R, sr_sig);
+ cell->setPort(ID::D, bit_d);
}
}
}
for (auto cell : module->selected_cells())
{
- if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER"))
+ if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
continue;
if (cell->has_keep_attr())
continue;
- if (cell->type == "\\SB_LUT4")
+ if (cell->type == ID(SB_LUT4))
{
sb_lut_cells.push_back(cell);
continue;
}
- if (cell->type == "\\SB_CARRY")
+ if (cell->type == ID(SB_CARRY))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
- get_bit_or_zero(cell->getPort("\\I0")),
- get_bit_or_zero(cell->getPort("\\I1")),
- get_bit_or_zero(cell->getPort("\\CI"))
+ get_bit_or_zero(cell->getPort(ID(I0))),
+ get_bit_or_zero(cell->getPort(ID(I1))),
+ get_bit_or_zero(cell->getPort(ID::CI))
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
- optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
- module->connect(cell->getPort("\\CO")[0], replacement_output);
+ optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
+ module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
continue;
}
- if (cell->type == "$__ICE40_CARRY_WRAPPER")
+ if (cell->type == ID($__ICE40_CARRY_WRAPPER))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
cell->getPort(ID::A),
cell->getPort(ID::B),
- cell->getPort("\\CI")
+ cell->getPort(ID::CI)
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
- optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
+ optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
auto it = cell->attributes.find(ID(SB_LUT4.name));
if (it != cell->attributes.end()) {
module->rename(cell, it->second.decode_string());
for (const auto &a : cell->attributes)
if (a.first.begins_with("\\SB_LUT4.\\"))
new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
- else if (a.first == ID(src))
+ else if (a.first == ID::src)
new_attr.insert(std::make_pair(a.first, a.second));
- else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
+ else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
continue;
else if (a.first.begins_with("\\SB_CARRY.\\"))
continue;
log_abort();
cell->attributes = std::move(new_attr);
}
- module->connect(cell->getPort("\\CO")[0], replacement_output);
+ module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
- cell->type = "$lut";
- auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
- cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
- cell->setPort(ID::Y, cell->getPort("\\O"));
+ cell->type = ID($lut);
+ auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
+ cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
+ cell->setPort(ID::Y, cell->getPort(ID::O));
cell->unsetPort(ID::B);
- cell->unsetPort("\\CI");
- cell->unsetPort("\\I0");
- cell->unsetPort("\\I3");
- cell->unsetPort("\\CO");
- cell->unsetPort("\\O");
- cell->setParam("\\WIDTH", 4);
- cell->unsetParam("\\I3_IS_CI");
+ cell->unsetPort(ID::CI);
+ cell->unsetPort(ID(I0));
+ cell->unsetPort(ID(I3));
+ cell->unsetPort(ID::CO);
+ cell->unsetPort(ID::O);
+ cell->setParam(ID::WIDTH, 4);
+ cell->unsetParam(ID(I3_IS_CI));
}
continue;
}
{
SigSpec inbits;
- inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
- inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
- inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
- inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+ inbits.append(get_bit_or_zero(cell->getPort(ID(I0))));
+ inbits.append(get_bit_or_zero(cell->getPort(ID(I1))));
+ inbits.append(get_bit_or_zero(cell->getPort(ID(I2))));
+ inbits.append(get_bit_or_zero(cell->getPort(ID(I3))));
sigmap.apply(inbits);
if (optimized_co.count(inbits[0])) goto remap_lut;
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
- cell->type ="$lut";
- cell->setParam("\\WIDTH", 4);
- cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
- cell->unsetParam("\\LUT_INIT");
+ cell->type = ID($lut);
+ cell->setParam(ID::WIDTH, 4);
+ cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
+ cell->unsetParam(ID(LUT_INIT));
cell->setPort(ID::A, SigSpec({
- get_bit_or_zero(cell->getPort("\\I3")),
- get_bit_or_zero(cell->getPort("\\I2")),
- get_bit_or_zero(cell->getPort("\\I1")),
- get_bit_or_zero(cell->getPort("\\I0"))
+ get_bit_or_zero(cell->getPort(ID(I3))),
+ get_bit_or_zero(cell->getPort(ID(I2))),
+ get_bit_or_zero(cell->getPort(ID(I1))),
+ get_bit_or_zero(cell->getPort(ID(I0)))
}));
- cell->setPort(ID::Y, cell->getPort("\\O")[0]);
- cell->unsetPort("\\I0");
- cell->unsetPort("\\I1");
- cell->unsetPort("\\I2");
- cell->unsetPort("\\I3");
- cell->unsetPort("\\O");
+ cell->setPort(ID::Y, cell->getPort(ID::O)[0]);
+ cell->unsetPort(ID(I0));
+ cell->unsetPort(ID(I1));
+ cell->unsetPort(ID(I2));
+ cell->unsetPort(ID(I3));
+ cell->unsetPort(ID::O);
cell->check();
simplemap_lut(module, cell);
for (auto cell : module->cells())
{
- if (clkbuf_mode && cell->type == "\\SLE") {
- for (auto bit : sigmap(cell->getPort("\\CLK")))
+ if (clkbuf_mode && cell->type == ID(SLE)) {
+ for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
- if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
- "\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF",
- "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
- for (auto bit : sigmap(cell->getPort("\\PAD")))
+ if (cell->type.in(ID(INBUF), ID(OUTBUF), ID(TRIBUFF), ID(BIBUF), ID(CLKBUF), ID(CLKBIBUF),
+ ID(INBUF_DIFF), ID(OUTBUF_DIFF), ID(BIBUFF_DIFF), ID(TRIBUFF_DIFF), ID(CLKBUF_DIFF),
+ ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF))) {
+ for (auto bit : sigmap(cell->getPort(ID(PAD))))
handled_io_bits.insert(bit);
}
}
IdString buf_type, buf_port;
if (wire->port_output) {
- buf_type = "\\OUTBUF";
- buf_port = "\\D";
+ buf_type = ID(OUTBUF);
+ buf_port = ID::D;
} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
- buf_type = "\\CLKBUF";
+ buf_type = ID(CLKBUF);
buf_port = ID::Y;
} else {
- buf_type = "\\INBUF";
+ buf_type = ID(INBUF);
buf_port = ID::Y;
}
module->rewrite_sigspecs(rewrite_function);
for (auto &it : pad_bits)
- it.first->setPort("\\PAD", it.second);
+ it.first->setPort(ID(PAD), it.second);
}
static void handle_clkint(Module *module)
for (auto cell : module->cells())
{
- if (cell->type == "\\SLE") {
- for (auto bit : sigmap(cell->getPort("\\CLK")))
+ if (cell->type == ID(SLE)) {
+ for (auto bit : sigmap(cell->getPort(ID::CLK)))
clk_bits.insert(bit);
}
- if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
- "\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
+ if (cell->type.in(ID(CLKBUF), ID(CLKBIBUF), ID(CLKBUF_DIFF), ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF),
+ ID(CLKINT), ID(CLKINT_PRESERVE), ID(GCLKINT), ID(RCLKINT), ID(RGCLKINT))) {
for (auto bit : sigmap(cell->getPort(ID::Y)))
handled_clk_bits.push_back(bit);
}
for (auto &bit : sig) {
SigBit canonical_bit = sigmap(bit);
if (clk_bits.count(canonical_bit)) {
- Cell *c = module->addCell(NEW_ID, "\\CLKINT");
+ Cell *c = module->addCell(NEW_ID, ID(CLKINT));
SigBit new_bit = module->addWire(NEW_ID);
c->setPort(ID::A, new_bit);
c->setPort(ID::Y, bit);
if (cell->get_bool_attribute(ID::keep))
continue;
if (cell->type == ID(INV)) {
- SigBit sigout = sigmap(cell->getPort(ID(O)));
- SigBit sigin = sigmap(cell->getPort(ID(I)));
+ SigBit sigout = sigmap(cell->getPort(ID::O));
+ SigBit sigin = sigmap(cell->getPort(ID::I));
bit_to_lut[sigout] = make_pair(LutData(Const(1, 2), {sigin}), cell);
} else if (cell->type.in(ID(LUT1), ID(LUT2), ID(LUT3), ID(LUT4), ID(LUT5), ID(LUT6))) {
- SigBit sigout = sigmap(cell->getPort(ID(O)));
- const Const &init = cell->getParam(ID(INIT));
+ SigBit sigout = sigmap(cell->getPort(ID::O));
+ const Const &init = cell->getParam(ID::INIT);
std::vector<SigBit> sigin;
sigin.push_back(sigmap(cell->getPort(ID(I0))));
if (cell->type == ID(LUT1))
continue;
// Don't bother if D has more than one use.
- SigBit sig_D = sigmap(cell->getPort(ID(D)));
+ SigBit sig_D = sigmap(cell->getPort(ID::D));
if (bit_uses[sig_D] > 2)
continue;
bool worthy_post_r = false;
// First, unmap CE.
- SigBit sig_Q = sigmap(cell->getPort(ID(Q)));
+ SigBit sig_Q = sigmap(cell->getPort(ID::Q));
SigBit sig_CE = sigmap(cell->getPort(ID(CE)));
LutData lut_ce = LutData(Const(2, 2), {sig_CE});
auto it_CE = bit_to_lut.find(sig_CE);
// Second, unmap S, if any.
lut_d_post_s = lut_d_post_ce;
if (has_s) {
- SigBit sig_S = sigmap(cell->getPort(ID(S)));
+ SigBit sig_S = sigmap(cell->getPort(ID::S));
LutData lut_s = LutData(Const(2, 2), {sig_S});
bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool();
auto it_S = bit_to_lut.find(sig_S);
// Third, unmap R, if any.
lut_d_post_r = lut_d_post_s;
if (has_r) {
- SigBit sig_R = sigmap(cell->getPort(ID(R)));
+ SigBit sig_R = sigmap(cell->getPort(ID::R));
LutData lut_r = LutData(Const(2, 2), {sig_R});
bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool();
auto it_R = bit_to_lut.find(sig_R);
// Okay, we're doing it. Unmap ports.
if (worthy_post_r) {
cell->unsetParam(ID(IS_R_INVERTED));
- cell->setPort(ID(R), Const(0, 1));
+ cell->setPort(ID::R, Const(0, 1));
}
if (has_s && (worthy_post_r || worthy_post_s)) {
cell->unsetParam(ID(IS_S_INVERTED));
- cell->setPort(ID(S), Const(0, 1));
+ cell->setPort(ID::S, Const(0, 1));
}
cell->setPort(ID(CE), Const(1, 1));
cell->unsetParam(ID(IS_D_INVERTED));
}
lut_cell->attributes = cell_d->attributes;
Wire *lut_out = module->addWire(NEW_ID);
- lut_cell->setParam(ID(INIT), final_lut.first);
- cell->setPort(ID(D), lut_out);
- lut_cell->setPort(ID(O), lut_out);
+ lut_cell->setParam(ID::INIT, final_lut.first);
+ cell->setPort(ID::D, lut_out);
+ lut_cell->setPort(ID::O, lut_out);
lut_cell->setPort(ID(I0), final_lut.second[0]);
if (GetSize(final_lut.second) >= 2)
lut_cell->setPort(ID(I1), final_lut.second[1]);
projects / yosys.git / commitdiff