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diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 5f9007cf3a2cdf143a581de04f81951b364428da..958c63f6fa4dbcb87c39f36e08013432295ba064 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -80,16 +80,17 @@ BM2-Form
 
 Pseudo-code:
 
+```
     if _RB = 0 then mask <- [1] * XLEN
-    else mask <- (RB)
+    else            mask <- (RB)
     ra <- (RA) & mask
     a1 <- ra
-    if bm[4] = 0 then a1 <- ¬ra
+    if bm[4] = 0 then a1 <- ¬ra
     mode2 <- bm[2:3]
-    if mode2 = 0 then a2 <- (¬ra)+1
+    if mode2 = 0 then a2 <- (¬ra)+1
     if mode2 = 1 then a2 <- ra-1
     if mode2 = 2 then a2 <- ra+1
-    if mode2 = 3 then a2 <- ¬(ra+1)
+    if mode2 = 3 then a2 <- ¬(ra+1)
     a1 <- a1 & mask
     a2 <- a2 & mask
     # select operator
@@ -98,11 +99,13 @@ Pseudo-code:
     if mode3 = 1 then result <- a1 & a2
     if mode3 = 2 then result <- a1 ^ a2
     if mode3 = 3 then result <- undefined([0]*XLEN)
+    # mask output
     result <- result & mask
     # optionally restore masked-out bits
     if L = 1 then
-        result <- result | (RA & ¬mask)
+        result <- result | (RA & ¬mask)
     RT <- result
+```
 
 Special Registers Altered: