i386.md (*bmi2_umul<mode><dwi>3_1): Merge from *bmi2_umulsidi3_1 and *bmi2_umulditi3_...

	* config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Merge from
	*bmi2_umulsidi3_1 and *bmi2_umulditi3_1 using DWIH mode iterator.

From-SVN: r222052

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 641bdffcc8b2dee75f939ac1e9fc05caab2a2ac4..e846816e09d1165b80213855a0195046dd9c5819 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-13  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (*bmi2_umul<mode><dwi>3_1): Merge from
+       *bmi2_umulsidi3_1 and *bmi2_umulditi3_1 using DWIH mode iterator.
+
 2015-04-13  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/65204

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index e1c82fefc0d6b44feb02f038c389cd5034b9f043..729db75584e7ca946809d23348a4ce77481ee499 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6818,41 +6818,23 @@
              (clobber (reg:CC FLAGS_REG))])]
   "TARGET_QIMODE_MATH")
 
-(define_insn "*bmi2_umulditi3_1"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-       (mult:DI
-         (match_operand:DI 2 "nonimmediate_operand" "%d")
-         (match_operand:DI 3 "nonimmediate_operand" "rm")))
-   (set (match_operand:DI 1 "register_operand" "=r")
-       (truncate:DI
-         (lshiftrt:TI
-           (mult:TI (zero_extend:TI (match_dup 2))
-                    (zero_extend:TI (match_dup 3)))
-           (const_int 64))))]
-  "TARGET_64BIT && TARGET_BMI2
-   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "mulx\t{%3, %0, %1|%1, %0, %3}"
-  [(set_attr "type" "imulx")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "DI")])
-
-(define_insn "*bmi2_umulsidi3_1"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (mult:SI
-         (match_operand:SI 2 "nonimmediate_operand" "%d")
-         (match_operand:SI 3 "nonimmediate_operand" "rm")))
-   (set (match_operand:SI 1 "register_operand" "=r")
-       (truncate:SI
-         (lshiftrt:DI
-           (mult:DI (zero_extend:DI (match_dup 2))
-                    (zero_extend:DI (match_dup 3)))
-           (const_int 32))))]
-  "!TARGET_64BIT && TARGET_BMI2
+(define_insn "*bmi2_umul<mode><dwi>3_1"
+  [(set (match_operand:DWIH 0 "register_operand" "=r")
+       (mult:DWIH
+         (match_operand:DWIH 2 "nonimmediate_operand" "%d")
+         (match_operand:DWIH 3 "nonimmediate_operand" "rm")))
+   (set (match_operand:DWIH 1 "register_operand" "=r")
+       (truncate:DWIH
+         (lshiftrt:<DWI>
+           (mult:<DWI> (zero_extend:<DWI> (match_dup 2))
+                       (zero_extend:<DWI> (match_dup 3)))
+           (match_operand:QI 4 "const_int_operand" "n"))))]
+  "TARGET_BMI2 && INTVAL (operands[4]) == <MODE_SIZE> * BITS_PER_UNIT
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "mulx\t{%3, %0, %1|%1, %0, %3}"
   [(set_attr "type" "imulx")
    (set_attr "prefix" "vex")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "*umul<mode><dwi>3_1"
   [(set (match_operand:<DWI> 0 "register_operand" "=r,A")
@@ -6902,7 +6884,7 @@
 {
   split_double_mode (<DWI>mode, &operands[0], 1, &operands[3], &operands[4]);
 
-  operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
+  operands[5] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT);
 })
 
 (define_insn "*mul<mode><dwi>3_1"