make all vector-size related integer params in $mem sim model signed

this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index abd2af521f622588683358f5c23fa558e3e6ba83..f3a12717016acfe927e16aaba78995e6a81fcfb1 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1556,18 +1556,18 @@ endmodule
 module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
 
 parameter MEMID = "";
-parameter SIZE = 4;
-parameter OFFSET = 0;
-parameter ABITS = 2;
-parameter WIDTH = 8;
+parameter signed SIZE = 4;
+parameter signed OFFSET = 0;
+parameter signed ABITS = 2;
+parameter signed WIDTH = 8;
 parameter signed INIT = 1'bx;
 
-parameter RD_PORTS = 1;
+parameter signed RD_PORTS = 1;
 parameter RD_CLK_ENABLE = 1'b1;
 parameter RD_CLK_POLARITY = 1'b1;
 parameter RD_TRANSPARENT = 1'b1;
 
-parameter WR_PORTS = 1;
+parameter signed WR_PORTS = 1;
 parameter WR_CLK_ENABLE = 1'b1;
 parameter WR_CLK_POLARITY = 1'b1;