class Platform(XilinxPlatform):
default_clk_name = "clk100"
- default_clk_period = 10.0
+ default_clk_period = 1e9/100e6
def __init__(self, variant="a7-35"):
device = {
class Platform(MicrosemiPlatform):
default_clk_name = "clk50"
- default_clk_period = 20.0
+ default_clk_period = 1e9/50e6
def __init__(self):
MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
class Platform(AlteraPlatform):
default_clk_name = "clk50"
- default_clk_period = 20
+ default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
class Platform(XilinxPlatform):
default_clk_name = "clk200"
- default_clk_period = 5
+ default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
class Platform(XilinxPlatform):
default_clk_name = "clk156"
- default_clk_period = 6.4
+ default_clk_period = 1e9/156.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
class Platform(XilinxPlatform):
default_clk_name = "clk125"
- default_clk_period = 8.0
+ default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
class Platform(LatticePlatform):
default_clk_name = "clk12"
- default_clk_period = 83
+ default_clk_period = 1e9/12e6
def __init__(self):
LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)
class Platform(XilinxPlatform):
default_clk_name = "clk32"
- default_clk_period = 31.25
+ default_clk_period = 1e9/32e6
def __init__(self, device="xc6slx25"):
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
class Platform(XilinxPlatform):
default_clk_name = "clk50"
- default_clk_period = 20.0
+ default_clk_period = 1e9/50e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
class Platform(XilinxPlatform):
default_clk_name = "clk100"
- default_clk_period = 10.0
+ default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
class Platform(XilinxPlatform):
default_clk_name = "clk100"
- default_clk_period = 10.0
+ default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")
class Platform(LatticePlatform):
default_clk_name = "clk16"
- default_clk_period = 62.5
+ default_clk_period = 1e9/16e6
def __init__(self):
LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm")
class Platform(LatticePlatform):
default_clk_name = "clk25"
- default_clk_period = 40
+ default_clk_period = 1e9/25e6
def __init__(self, device="LFE5U-45F", **kwargs):
LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
class Platform(LatticePlatform):
default_clk_name = "clk100"
- default_clk_period = 10
+ default_clk_period = 1e9/100e6
def __init__(self):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
class Platform(LatticePlatform):
default_clk_name = "clk100"
- default_clk_period = 10
+ default_clk_period = 1e9/100e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)