(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 732c6c9809456711cf7a21b05c963bb0392d4f35..f3802e1d9efb74cc467a6ae83b0fe55042315ee8 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -191,8 +191,11 @@ Brief description of fields:
   If VLI (Vector Length Inclusive) is clear,
   VL is truncated to *exclude* the current element, otherwise it is
   included. SVSTATE.MVL is not altered: only VL.
-* **LRu**: Link Register Update. When set, Link Register will
-  only be updated if the Branch Condition succeeds. This avoids
+* **LRu**: Link Register Update, used in conjunction with LK=1.
+  When LRu=1,LK=1, Link Register will
+  only be updated if the Branch Condition succeeds.
+  When LRu=0,LK=1, Link Register will only be updated if
+  the Branch Condition fails. This avoids
   destruction of LR during loops (particularly Vertical-First
   ones).
 * **VSb** In VLSET Mode, after testing,
@@ -541,7 +544,7 @@ lr_ok <- SVRMmode.LRu
 if ctr_ok & cond_ok then
   if AA then NIA <-iea EXTS(BD || 0b00)
   else       NIA <-iea CIA + EXTS(BD || 0b00)
-  lr_ok <- 0b1
+  lr_ok <- ¬lr_ok
 if LK & lr_ok then LR <-iea CIA + 4
 ```
 
@@ -601,7 +604,7 @@ lr_ok <- SVRMmode.LRu
 if cond_ok then
     if AA then NIA <-iea EXTS(BD || 0b00)
     else       NIA <-iea CIA + EXTS(BD || 0b00)
-    lr_ok <- 0b1
+    lr_ok <- ¬lr_ok
 if LK & lr_ok then LR <-iea CIA + 4
 ```
 
@@ -725,7 +728,7 @@ for i in 0 to VL-1:
     cond_ok <- BO[0] | ¬(CR[BI+32] ^  BO[1])
     if ctr_ok & cond_ok then
        NIA <-iea LR[0:61] || 0b00
-       lr_ok = 1
+       lr_ok = ¬lr_ok
     if LK & lr_ok then LR <-iea CIA + 4
 ```
 
@@ -753,5 +756,6 @@ for i in 0 to VL-1:
 # this completely violates the design principle of SVP64
 # and would actually need to be a separate (scalar)
 # instruction "set LR to CIA+4 but retrospectively"
+# which is clearly impossible
 if LK then LR <-iea CIA + 4
 ```