etnaviv: GC7000: flush TX descriptor and instruction cache

The etnaviv kernel driver will only ever flush write caches. As both
the TX descriptor and instruction cache are read caches they must be
flushed from the user cmdstream at an appropriate time.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c b/src/gallium/drivers/etnaviv/etnaviv_context.c
index fec4f3958e715352278816d06e236049171e1540..367f31f2e9b509db8b176d7953dd2003727be43c 100644 (file)
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -413,9 +413,16 @@ static void etna_reset_gpu_state(struct etna_context *ctx)
        * before command stream submission. It does not need flushing if the
        * referenced image data changes.
        */
+      etna_set_state(stream, VIVS_NTE_DESCRIPTOR_FLUSH, 0);
       etna_set_state(stream, VIVS_GL_FLUSH_CACHE,
             VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 |
             VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13);
+
+      /* Icache invalidate (should do this on shader change?) */
+      etna_set_state(stream, VIVS_VS_ICACHE_INVALIDATE,
+            VIVS_VS_ICACHE_INVALIDATE_UNK0 | VIVS_VS_ICACHE_INVALIDATE_UNK1 |
+            VIVS_VS_ICACHE_INVALIDATE_UNK2 | VIVS_VS_ICACHE_INVALIDATE_UNK3 |
+            VIVS_VS_ICACHE_INVALIDATE_UNK4);
    }
 
    ctx->dirty = ~0L;