Only action if there is more than one clock domain

diff --git a/passes/techmap/clkpart.cc b/passes/techmap/clkpart.cc
index d8d53536d2652901bd2703b0087df1a76b3769f9..8f671c175b15279a0cbb0d00c2f563de0f5bfc49 100644 (file)
--- a/passes/techmap/clkpart.cc
+++ b/passes/techmap/clkpart.cc
@@ -233,15 +233,16 @@ struct ClkPartPass : public Pass {
                                                std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
                                                std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
 
-                       for (auto &it : assigned_cells) {
-                               RTLIL::Selection sel(false);
-                               sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
+                       if (assigned_cells.size() > 1)
+                               for (auto &it : assigned_cells) {
+                                       RTLIL::Selection sel(false);
+                                       sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
 
-                               RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
-                               Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
+                                       RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
+                                       Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
 
-                               design->module(submod)->set_bool_attribute(ID(clkpart));
-                       }
+                                       design->module(submod)->set_bool_attribute(ID(clkpart));
+                               }
                }
        }