cpu/vexriscv: update

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index cfbd3e0871e1f85336c6a7adbc75f3702b365e1d..03f7f9d46c9c862e1ef3ebbe19b5113b882e4358 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit cfbd3e0871e1f85336c6a7adbc75f3702b365e1d
+Subproject commit 03f7f9d46c9c862e1ef3ebbe19b5113b882e4358