(no commit message)

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 48ba0cdb8805e4706ca3733046fda0f022d7d497..c45faed64b100152fa8088ca3ed1ab6ffc9d32da 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -369,7 +369,7 @@ decision-making, whereas VL=1 will only test the first.
 a need for merging (ORing) all bits into a single alternative predicate mask
 (single-bit) is the sort of thing we can probably live with.
 
-## fast traditional packed SIMD
+## reducing unnecessary setvl interchanges
 
 A major motivation for changing SVP64 with all isvec=0 to temporarily
 override VL to 1 is to allow easy interleaving of Scalar instructions