Signed-off-by: David Shah <dave@ds0.me>
endmodule
`endif
-module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
+module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
- .A({5'b0, A}),
- .B(B),
+ .A({6'b0, A}),
+ .B({1'b0, B}),
.C(48'b0),
.D(24'b0),
.P(P_48),
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
+ // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
+ // Due to current limitations of mul2dsp, we are actually mapping as a 24x17
+ // unsigned multiply with MSBs set to 1'b0
+
if (!nodsp || help_mode)
- run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+ run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
run("alumacc");
run("share");