xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
authorDavid Shah <dave@ds0.me>
Tue, 16 Jul 2019 15:46:41 +0000 (16:46 +0100)
committerDavid Shah <dave@ds0.me>
Tue, 16 Jul 2019 15:47:53 +0000 (16:47 +0100)
Signed-off-by: David Shah <dave@ds0.me>
techlibs/xilinx/cells_map.v
techlibs/xilinx/synth_xilinx.cc

index 6ebca0d544e56708cf1dd8ab0e84efaf506b2b59..8302e0b3a4db29b5d7f029d5b10bc361c1d34e5a 100644 (file)
@@ -366,7 +366,7 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
 endmodule
 `endif
 
-module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
+module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] OUT);
        wire [47:0] P_48;
        DSP48E1 #(
                // Disable all registers
@@ -388,8 +388,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT);
                .PREG(0)
        ) _TECHMAP_REPLACE_ (
                //Data path
-               .A({5'b0, A}),
-               .B(B),
+               .A({6'b0, A}),
+               .B({1'b0, B}),
                .C(48'b0),
                .D(24'b0),
                .P(P_48),
index 01e75b50eaf3af1f0578910eca48a0bfdfa06ad1..5bfbd158340e2c61a7d62842a9c97703df13bfab 100644 (file)
@@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
 
                        run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
 
+                       // The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
+                       // Due to current limitations of mul2dsp, we are actually mapping as a 24x17
+                       // unsigned multiply with MSBs set to 1'b0
+
                        if (!nodsp || help_mode)
-                               run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
+                               run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
 
                        run("alumacc");
                        run("share");