MicrOp, OutSel, SVMode,
SVP64LDSTmode, SVP64PredCR,
SVP64PredInt, SVP64PredMode,
- SVP64RMMode, SVPtype, XER_bits,
+ SVP64RMMode, SVPType, XER_bits,
insns, spr_byname, spr_dict)
from openpower.decoder.power_insn import SVP64Instruction
from openpower.decoder.power_svp64 import SVP64RM, decode_extra
pred_sz = yield self.dec2.rm_dec.pred_sz
if pmode == SVP64PredMode.INT.value:
srcmask = dstmask = get_predint(self.gpr, dstpred)
- if sv_ptype == SVPtype.P2.value:
+ if sv_ptype == SVPType.P2.value:
srcmask = get_predint(self.gpr, srcpred)
elif pmode == SVP64PredMode.CR.value:
srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
- if sv_ptype == SVPtype.P2.value:
+ if sv_ptype == SVPType.P2.value:
srcmask = get_predcr(self.crl, srcpred, vl)
# work out if the ssubsteps are completed
ssubstart = ssubstep == 0
log(" reverse", reverse_gear)
log(" out_vec", out_vec)
log(" in_vec", in_vec)
- log(" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+ log(" sv_ptype", sv_ptype, sv_ptype == SVPType.P2.value)
# check if this was an sv.bc* and if so did it succeed
if self.is_svp64_mode and insn_name.startswith("sv.bc"):
end_loop = self.namespace['end_loop']
# check if srcstep needs incrementing by one, stop PC advancing
# but for 2-pred both src/dest have to be checked.
# XXX this might not be true! it may just be LD/ST
- if sv_ptype == SVPtype.P2.value:
+ if sv_ptype == SVPType.P2.value:
svp64_is_vector = (out_vec or in_vec)
else:
svp64_is_vector = out_vec
from openpower.decoder.power_enums import (Function, Form, MicrOp,
In1Sel, In2Sel, In3Sel, OutSel,
SVEXTRA, SVMode, # Simple-V
- SVEtype, SVPtype, # Simple-V
+ SVEType, SVPType, # Simple-V
RCOE, LdstLen, LDSTMode, CryIn,
single_bit_flags, CRInSel,
CROutSel, get_signal_name,
'internal_op': MicrOp,
'form': Form,
'asmcode': asmlen,
- 'SV_Etype': SVEtype,
- 'SV_Ptype': SVPtype,
+ 'SV_Etype': SVEType,
+ 'SV_Ptype': SVPType,
'SV_mode': SVMode,
'in1_sel': In1Sel,
'in2_sel': In2Sel,
LdstLen, In1Sel, In2Sel, In3Sel,
OutSel, SPRfull, SPRreduced,
RCOE, SVP64LDSTmode, LDSTMode,
- SVEXTRA, SVEtype, SVPtype)
+ SVEXTRA, SVEType, SVPType)
from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
Decode2ToOperand)
# should continue. this doesn't include predication bit-tests
loop = self.loop_continue
with m.Switch(self.op_get("SV_Ptype")):
- with m.Case(SVPtype.P2.value):
+ with m.Case(SVPType.P2.value):
# twin-predication
# TODO: *and cache-inhibited LD/ST!*
comb += loop.eq(~(self.no_in_vec | self.no_out_vec))
- with m.Case(SVPtype.P1.value):
+ with m.Case(SVPType.P1.value):
# single-predication, test relies on dest only
comb += loop.eq(~self.no_out_vec)
with m.Default():
class Enum(_Enum):
@classmethod
- def _missing_(cls, value):
- if isinstance(value, str):
+ def _missing_(cls, desc):
+ if isinstance(desc, str):
try:
- if value == "":
- value = 0
+ if desc == "":
+ desc = 0
else:
- value = int(value, 0)
+ desc = int(desc, 0)
except ValueError:
pass
keys = {item.name:item for item in cls}
- values = {item.value:item for item in cls}
- item = keys.get(value, values.get(value))
- if item is None:
- raise ValueError(value)
- return item
+ descs = {item.value:item for item in cls}
+ return keys.get(desc, descs.get(desc))
# this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
@unique
-class SVPtype(Enum):
+class SVPType(Enum):
NONE = 0
P1 = 1
P2 = 2
@classmethod
- def _missing_(cls, value):
- return {"1P": SVPtype.P1, "2P": SVPtype.P2}[value]
+ def _missing_(cls, desc):
+ return {"1P": SVPType.P1, "2P": SVPType.P2}.get(desc)
def __repr__(self):
return {
- SVPtype.NONE: "NONE",
- SVPtype.P1: "1P",
- SVPtype.P2: "2P",
+ SVPType.NONE: "NONE",
+ SVPType.P1: "1P",
+ SVPType.P2: "2P",
}[self]
@unique
-class SVEtype(Enum):
+class SVEType(Enum):
NONE = 0
EXTRA2 = 1
EXTRA3 = 2
@unique
-class SVmask_src(Enum):
+class SVMaskSrc(Enum):
NO = 0
EN = 1
SPR = auto()
@classmethod
- def _missing_(cls, value):
+ def _missing_(cls, desc):
selectors = (
In1Sel, In2Sel, In3Sel, CRInSel, CRIn2Sel,
OutSel, CROutSel,
)
- if isinstance(value, selectors):
- return cls.__members__[value.name]
- return super()._missing_(value)
+ if isinstance(desc, selectors):
+ return cls.__members__.get(desc.name)
+
+ return super()._missing_(desc)
@unique
RC1_INV = ("~RC1", True, 0b1)
@classmethod
- def _missing_(cls, value):
- if isinstance(value, str):
+ def _missing_(cls, desc):
+ if isinstance(desc, str):
members = {}
for (name, member) in cls.__members__.items():
members[str(member)] = member.name
- member = value
+ member = desc
if "RC1" not in member:
member = member.lower()
member = members.get(member, member)
return cls[member]
- return super()._missing_(value)
+ return super()._missing_(desc)
def __str__(self):
return self.value[0]
RC1_INV = RC1
@classmethod
- def _missing_(cls, value):
- if isinstance(value, SVP64Predicate):
- return cls.__members__[value.name]
- return super()._missing_(value)
+ def _missing_(cls, desc):
+ if isinstance(desc, SVP64Predicate):
+ return cls.__members__.get(desc.name)
+
+ return super()._missing_(desc)
@unique
@unique
-class SVP64width(Enum):
+class SVP64Width(Enum):
DEFAULT = 0
EW_32 = 1
EW_16 = 2
def _missing_(cls, desc):
if isinstance(desc, str):
return {
- "32": SVP64width.EW_32,
- "16": SVP64width.EW_16,
- "8": SVP64width.EW_8,
+ "32": SVP64Width.EW_32,
+ "16": SVP64Width.EW_16,
+ "8": SVP64Width.EW_8,
}.get(desc)
return super()._missing_(desc)
-SVP64Width = SVP64width
-
@unique
-class SVP64subvl(Enum):
+class SVP64SubVL(Enum):
VEC1 = 0
VEC2 = 1
VEC3 = 2
def _missing_(cls, desc):
if isinstance(desc, str):
name = desc.upper()
- value = cls.__members__.get(name)
- if value is None:
- raise ValueError(desc)
- return value
- return super()._missing_(desc)
+ return cls.__members__.get(name)
-SVP64SubVL = SVP64subvl
+ return super()._missing_(desc)
@unique
-class SVP64sat(Enum):
+class SVP64Sat(Enum):
NONE = 0
SIGNED = 1
UNSIGNED = 2
@classmethod
def _missing_(cls, value):
if isinstance(value, SVExtraReg):
- return cls.__members__[value.name]
+ return cls.__members__.get(value.name)
+
return super()._missing_(value)
RCOE as _RCOE,
CryIn as _CryIn,
Form as _Form,
- SVEtype as _SVEtype,
- SVmask_src as _SVmask_src,
+ SVEType as _SVEType,
+ SVMaskSrc as _SVMaskSrc,
SVMode as _SVMode,
- SVPtype as _SVPtype,
+ SVPType as _SVPType,
SVExtra as _SVExtra,
RegType as _RegType,
SVP64RMMode as _SVP64RMMode,
return repr({index:self[index] for index in range(0, 4)})
name: str
- ptype: _SVPtype = _SVPtype.NONE
- etype: _SVEtype = _SVEtype.NONE
- msrc: _SVmask_src = _SVmask_src.NO # MASK_SRC is active
+ ptype: _SVPType = _SVPType.NONE
+ etype: _SVEType = _SVEType.NONE
+ msrc: _SVMaskSrc = _SVMaskSrc.NO # MASK_SRC is active
in1: _In1Sel = _In1Sel.NONE
in2: _In2Sel = _In2Sel.NONE
in3: _In3Sel = _In3Sel.NONE
if extra_idx is _SVExtra.NONE:
return (vector, value, span)
- if self.record.etype is _SVEtype.EXTRA3:
+ if self.record.etype is _SVEType.EXTRA3:
spec = insn.prefix.rm.extra3[extra_idx]
- elif self.record.etype is _SVEtype.EXTRA2:
+ elif self.record.etype is _SVEType.EXTRA2:
spec = insn.prefix.rm.extra2[extra_idx]
else:
raise ValueError(self.record.etype)
if spec != 0:
vector = bool(spec[0])
spec_span = spec.__class__
- if self.record.etype is _SVEtype.EXTRA3:
+ if self.record.etype is _SVEType.EXTRA3:
spec_span = tuple(map(str, spec_span[1, 2]))
spec = spec[1, 2]
- elif self.record.etype is _SVEtype.EXTRA2:
+ elif self.record.etype is _SVEType.EXTRA2:
spec_span = tuple(map(str, spec_span[1,]))
spec = _SelectableInt(value=spec[1].value, bits=2)
if vector:
if extra_idx is _SVExtra.NONE:
raise ValueError(self.record)
- if self.record.etype is _SVEtype.EXTRA3:
+ if self.record.etype is _SVEType.EXTRA3:
insn.prefix.rm.extra3[extra_idx] = extra
- elif self.record.etype is _SVEtype.EXTRA2:
+ elif self.record.etype is _SVEType.EXTRA2:
insn.prefix.rm.extra2[extra_idx] = extra
else:
raise ValueError(self.record.etype)
yield f"{indent}{indent}{', '.join(span)}"
if isinstance(insn, SVP64Instruction):
extra_idx = self.extra_idx
- if self.record.etype is _SVEtype.NONE:
+ if self.record.etype is _SVEType.NONE:
yield f"{indent}{indent}extra[none]"
else:
etype = repr(self.record.etype).lower()
# now sanity-check. EXTRA3 is ok, EXTRA2 has limits
# (and shrink to a single bit if ok)
- if self.record.etype is _SVEtype.EXTRA2:
+ if self.record.etype is _SVEType.EXTRA2:
if vector:
# range is r0-r127 in increments of 2 (r0 r2 ... r126)
assert (extra & 0b01) == 0, \
assert (extra >> 1) == 0, \
("scalar GPR %d cannot fit into EXTRA2" % value)
extra &= 0b01
- elif self.record.etype is _SVEtype.EXTRA3:
+ elif self.record.etype is _SVEType.EXTRA3:
if vector:
# EXTRA3 vector bit needs marking
extra |= 0b100
extra = (value >> 3)
value &= 0x7
- if self.record.etype is _SVEtype.EXTRA2:
+ if self.record.etype is _SVEType.EXTRA2:
if vector:
assert (extra & 0x7) == 0, \
"vector CR cannot fit into EXTRA2"
assert (extra >> 1) == 0, \
"scalar CR cannot fit into EXTRA2"
extra &= 0x1
- elif self.record.etype is _SVEtype.EXTRA3:
+ elif self.record.etype is _SVEType.EXTRA3:
if vector:
assert (extra & 0x3) == 0, \
"vector CR cannot fit into EXTRA3"
yield f"{indent}{indent}{', '.join(span)}"
if isinstance(insn, SVP64Instruction):
extra_idx = self.extra_idx
- if self.record.etype is _SVEtype.NONE:
+ if self.record.etype is _SVEType.NONE:
yield f"{indent}{indent}extra[none]"
else:
etype = repr(self.record.etype).lower()
CR = (int(self.mmode) == 1)
mask = int(self.mask)
sm = dm = PredicateBaseRM.predicate(CR, mask)
- if record.svp64.ptype is _SVPtype.P2:
+ if record.svp64.ptype is _SVPType.P2:
smask = int(self.smask)
sm = PredicateBaseRM.predicate(CR, smask)
if sm == dm and dm:
return super().match(desc=desc, record=record, mode="sm")
def validate(self, others):
- if self.record.svp64.ptype is _SVPtype.P1:
+ if self.record.svp64.ptype is _SVPType.P1:
raise ValueError("source-mask on non-twin predicate")
if self.pred.type is _SVP64PredicateType.CR:
return super().match(desc=desc, record=record, mode="dm")
def validate(self, others):
- if self.record.svp64.ptype is _SVPtype.P1:
+ if self.record.svp64.ptype is _SVPType.P1:
raise ValueError("dest-mask on non-twin predicate")
if self.pred.type is _SVP64PredicateType.CR:
from nmutil.util import sel
-from openpower.decoder.power_enums import (SVEXTRA, SVEtype)
+from openpower.decoder.power_enums import (SVEXTRA, SVEType)
from openpower.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field,
SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs)
"""
def __init__(self):
self.extra = Signal(9, reset_less=True)
- self.etype = Signal(SVEtype, reset_less=True) # 2 or 3 bits
+ self.etype = Signal(SVEType, reset_less=True) # 2 or 3 bits
self.idx = Signal(SVEXTRA, reset_less=True) # which part of extra
self.spec = Signal(3) # EXTRA spec for the register
# the register-extension information. extract those now
with m.Switch(self.etype):
# 2-bit index selection mode
- with m.Case(SVEtype.EXTRA2):
+ with m.Case(SVEType.EXTRA2):
with m.Switch(self.idx):
with m.Case(SVEXTRA.Idx0): # 1st 2 bits [0:1]
comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX0_VEC])
comb += spec[SPEC.VEC].eq(extra[EXTRA2.IDX3_VEC])
comb += spec[SPEC.MSB].eq(extra[EXTRA2.IDX3_MSB])
# 3-bit index selection mode
- with m.Case(SVEtype.EXTRA3):
+ with m.Case(SVEType.EXTRA3):
with m.Switch(self.idx):
with m.Case(SVEXTRA.Idx0): # 1st 3 bits [0:2]
extra3_idx0 = sel(m, extra, EXTRA3.IDX0)
"""
from nmigen import Elaboratable, Module, Signal, Const
-from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype,
+from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPType,
SVMode,
- SVP64PredMode, SVP64sat, SVP64LDSTmode,
+ SVP64PredMode, SVP64Sat, SVP64LDSTmode,
SVP64BCPredMode, SVP64BCVLSETMode,
SVP64BCGate, SVP64BCCTRMode,
- SVP64width
+ SVP64Width
)
from openpower.consts import EXTRA3, SVP64MODE
from openpower.sv.svp64 import SVP64Rec
sv_input_record_layout = [
('sv_pred_sz', 1), # predicate source zeroing
('sv_pred_dz', 1), # predicate dest zeroing
- ('sv_saturate', SVP64sat),
+ ('sv_saturate', SVP64Sat),
('sv_ldstmode', SVP64LDSTmode),
- ('SV_Ptype', SVPtype),
+ ('SV_Ptype', SVPType),
('SV_mode', SVMode),
#('sv_RC1', 1),
]
self.fn_in = Signal(Function) # LD/ST and Branch is different
self.sv_mode = Signal(SVMode) # BRANCH/LDST_IMM/CROP etc.
self.svp64_vf_in = Signal() # Vertical-First Mode
- self.ptype_in = Signal(SVPtype)
+ self.ptype_in = Signal(SVPType)
self.rc_in = Signal()
self.cr_5bit_in = Signal() # if CR field was 5-bit
self.cr_2bit_in = Signal() # bottom 2 bits of CR field
self.pred_dz = Signal(1) # predicate dest zeroing
# Modes n stuff
- self.ew_src = Signal(SVP64width) # source elwidth
- self.ew_dst = Signal(SVP64width) # dest elwidth
+ self.ew_src = Signal(SVP64Width) # source elwidth
+ self.ew_dst = Signal(SVP64Width) # dest elwidth
self.subvl= Signal(2) # subvl
- self.saturate = Signal(SVP64sat)
+ self.saturate = Signal(SVP64Sat)
self.RC1 = Signal()
self.vli = Signal()
self.cr_sel = Signal(2) # bit of CR to test (index 0-3)
with m.Switch(mode2):
with m.Case(2):
with m.If(mode[SVP64MODE.N]):
- comb += self.saturate.eq(SVP64sat.UNSIGNED)
+ comb += self.saturate.eq(SVP64Sat.UNSIGNED)
with m.Else():
- comb += self.saturate.eq(SVP64sat.SIGNED)
+ comb += self.saturate.eq(SVP64Sat.SIGNED)
with m.Default():
- comb += self.saturate.eq(SVP64sat.NONE)
+ comb += self.saturate.eq(SVP64Sat.NONE)
# do elwidth/elwidth_src extract
comb += self.ew_src.eq(self.rm_in.ewsrc)
# is in exactly the same bits
srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)
dstmask = self.rm_in.mask
- with m.If(self.ptype_in == SVPtype.P2):
+ with m.If(self.ptype_in == SVPType.P2):
comb += self.srcpred.eq(srcmask)
with m.Else():
comb += self.srcpred.eq(dstmask)
CRInSel as _CRInSel,
CRIn2Sel as _CRIn2Sel,
CROutSel as _CROutSel,
- SVPtype as _SVPtype,
- SVEtype as _SVEtype,
+ SVPType as _SVPType,
+ SVEType as _SVEType,
SVExtra as _SVExtra,
SVMode as _SVMode,
find_wiki_dir as _find_wiki_dir,
CRInSel = Enum("CRInSel", _CRInSel, c_tag="svp64_cr_in_sel")
CRIn2Sel = Enum("CRIn2Sel", _CRIn2Sel, c_tag="svp64_cr_in2_sel")
CROutSel = Enum("CROutSel", _CROutSel, c_tag="svp64_cr_out_sel")
-PType = Enum("PType", _SVPtype, c_tag="svp64_ptype")
-EType = Enum("EType", _SVEtype, c_tag="svp64_etype", exclude="NONE")
+PType = Enum("PType", _SVPType, c_tag="svp64_ptype")
+EType = Enum("EType", _SVEType, c_tag="svp64_etype", exclude="NONE")
Extra = Enum("Extra", _SVExtra, c_tag="svp64_extra", exclude="Idx_1_2")
Mode = Enum("Mode", _SVMode, c_tag="svp64_mode")
for (key, cls) in fields.items():
value = getattr(insn, key)
- if (((cls is EType) and (value is _SVEtype.NONE)) or
+ if (((cls is EType) and (value is _SVEType.NONE)) or
((cls is Extra) and (value is _SVExtra.Idx_1_2))):
desc = None
break
projects / openpower-isa.git / commitdiff