Fixed bug in synthesis of memories that are never written

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index b41d3aa2f4162162d8cd9f4fdb6b9a82419ecd74..1651751a2b2acbb5a77ca7515a19fe6d863b81f4 100644 (file)
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -121,8 +121,13 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
                        c->name = genid(cell->name, "", i);
                        c->type = "$dff";
                        c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
-                       c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
-                       c->connections["\\CLK"] = clocks.extract(0, 1);
+                       if (clocks_pol.bits.size() > 0) {
+                               c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
+                               c->connections["\\CLK"] = clocks.extract(0, 1);
+                       } else {
+                               c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
+                               c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
+                       }
                        module->cells[c->name] = c;
 
                        RTLIL::Wire *w_in = new RTLIL::Wire;