test: add attribute-before-stmt test from @nakengelhardt

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
index eb4f0fac478a1cf8850dc092533a563b8d2c0d41..4b629ba9241d1c6c0385351cd204181fc288c0d5 100644 (file)
--- a/tests/verilog/bug2037.ys
+++ b/tests/verilog/bug2037.ys
@@ -41,3 +41,18 @@ module test ();
 endmodule
 EOT
 select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+       localparam y = 1;
+       reg x = 1'b0;
+       always @(*) begin
+               if (y)
+                       (* foo *) x <= 1'b1;
+               else
+                       (* bar *) x = 1'b0;
+       end
+endmodule
+EOT