finish changing to use adde, not addeo for bigint add

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
index d14bf8e15636fc4d696e8f14eb008fe6c3ccd988..6f6f6deab31c6c96f3e81cd0b408862185181311 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
@@ -25,9 +25,9 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_bigint_add(self):
         """performs a carry-rollover-vector-add aka "big integer vector add"
-        this is remarkably simple, each sv.addeo uses and produces a CA which
-        goes into the next sv.addeo.  arbitrary size is possible (1024+) as
-        is looping using the CA bit from one sv.addeo on another batch to do
+        this is remarkably simple, each sv.adde uses and produces a CA which
+        goes into the next sv.adde.  arbitrary size is possible (1024+) as
+        is looping using the CA bit from one sv.adde on another batch to do
         unlimited-size biginteger add.
 
         r3/r2: 0x0000_0000_0000_0001 0xffff_ffff_ffff_ffff +