Update doc

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index b0251de50776820ebd8788bf57522f869ce69a50..5ccc47ba8a4b2f04fb7998741401d9588d05cd6f 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -578,7 +578,8 @@ struct XilinxDspPass : public Pass {
                log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
                log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
                log("input to the post-adder -- a pattern common for summing partial products to\n");
-               log("implement wide multipliers).\n");
+               log("implement wide multipliers). Initial support also exists for similar cascading\n");
+               log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n");
                log("\n");
                log("\n");
                log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");