liteeth: add phy autodetect function (phy can still be instanciated directly)

diff --git a/misoclib/com/liteeth/phy/__init__.py b/misoclib/com/liteeth/phy/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..8a96d7fb324d0dc6cc30ca02b7d33cca89ab46c5 100644 (file)
--- a/misoclib/com/liteeth/phy/__init__.py
+++ b/misoclib/com/liteeth/phy/__init__.py
@@ -0,0 +1,17 @@
+from misoclib.com.liteeth.common import *
+from misoclib.com.liteeth.generic import *
+
+from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
+from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
+from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
+
+def LiteEthPHY(clock_pads, pads, **kwargs):
+       # Autodetect PHY
+       if hasattr(pads, "source_stb"):
+               return LiteEthPHYSim(pads)
+       elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
+               return LiteEthPHYGMII(clock_pads, pads, **kwargs)
+       elif flen(pads.tx_data) == 4:
+               return LiteEthPHYMII(clock_pads, pads, **kwargs)
+       else:
+               raise ValueError("Unable to autodetect PHY from platform file, use direct instanciation")

diff --git a/targets/kc705.py b/targets/kc705.py
index 0281691c01c25e8a3b533f4020dafcdacdc415fb..6eae2d1ded9038dd39b97bc4b272d85979019674 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -7,7 +7,7 @@ from misoclib.mem.flash import spiflash
 from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 
-from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
+from misoclib.com.liteeth.phy import LiteEthPHY
 from misoclib.com.liteeth.mac import LiteEthMAC
 
 class _CRG(Module):
@@ -133,7 +133,7 @@ class MiniSoC(BaseSoC):
        def __init__(self, platform, **kwargs):
                BaseSoC.__init__(self, platform, **kwargs)
 
-               self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
+               self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
                self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
                self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
                self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index a281bf8f00e92fda73e02ccf54ae80207ba03561..b20d801f5307a4faec479a7c666da49a5155e119 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -13,7 +13,7 @@ from misoclib.video import framebuffer
 from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
 
-from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
+from misoclib.com.liteeth.phy import LiteEthPHY
 from misoclib.com.liteeth.mac import LiteEthMAC
 
 class _MXClockPads:
@@ -111,7 +111,7 @@ class MiniSoC(BaseSoC):
                        self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
                        self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
 
-               self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
+               self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
                self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
                self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
                self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)