add RT as an option for ternary instruction as 3rd register input

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index edf2893b3dec4749822db7d926efb4eaa0eea9b2..7dc213d63e1b99fbcae66e32975d2280ef5dabba 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -362,6 +362,10 @@ class DecodeC(Elaboratable):
             with m.Case(In3Sel.RC):
                 comb += reg.data.eq(self.dec.RC)
                 comb += reg.ok.eq(1)
+            with m.Case(In3Sel.RT):
+                # for TII-form ternary
+                comb += reg.data.eq(self.dec.RT)
+                comb += reg.ok.eq(1)
 
         return m
 

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index ec9ed77d8b4a5d982a6ebf16266d09a13427be63..5757fb6d3471d9b81270e0260124eb1e4c6096e9 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -478,7 +478,8 @@ class In3Sel(Enum):
     FRS = 3
     FRC = 4
     RC = 5  # for SVP64 bit-reverse LD/ST
-    CONST_TII = 6  # for ternaryi
+    CONST_TII = 6  # for ternaryi - XXX TODO: REMOVE THIS (from CSV, first)
+    RT = 7 # for ternary
 
 
 @unique