{
int value = (INT_LOWPART (x) >> 16) & 0xffff;
- /* Solaris assembler doesn't like lis 0,0x80000 */
+ /* Solaris assembler doesn't like lis 0,0x8000 */
if (DEFAULT_ABI == ABI_SOLARIS && (value & 0x8000) != 0)
fprintf (file, "%d", value | (~0 << 16));
else
/* If constant, low-order 16 bits of constant, signed. Otherwise, write
normally. */
if (INT_P (x))
- fprintf (file, "%d",
- (INT_LOWPART (x) & 0xffff) - 2 * (INT_LOWPART (x) & 0x8000));
+ fprintf (file, "%d", ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
else
print_operand (file, x, 0);
return;
reg_names[reg], reg_names[0], reg_names[reg]);
rs6000_pic_labelno++;
}
- else if (!TARGET_64BIT)
+ else if (! TARGET_64BIT)
{
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
asm_fprintf (file, "\t{liu|lis} %s,", reg_names[reg]);
if (copy_r12)
fprintf (file, "\tmr %s,%s\n", reg_names[12], reg_names[1]);
- asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
+ asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file,
reg_names[1], neg_size, reg_names[1]);
else
{
- asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
+ asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
asm_fprintf (file, "\t{cax|add} %s,%s,%s\n", reg_names[1],
{
int neg_size = info->main_save_offset - info->total_size;
loc = 0;
- asm_fprintf (file, "\t{liu|lis} %s,%d\n\t{oril|ori} %s,%s,%d\n",
+ asm_fprintf (file, "\t{liu|lis} %s,0x%x\n\t{oril|ori} %s,%s,%d\n",
reg_names[0], (neg_size >> 16) & 0xffff,
reg_names[0], reg_names[0], neg_size & 0xffff);
(define_insn "*addsi3_internal1"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
- (match_operand:SI 2 "add_operand" "r,I,I,J")))]
+ (match_operand:SI 2 "add_operand" "r,I,I,L")))]
""
"@
{cax|add} %0,%1,%2
(define_insn "andsi3"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
- (match_operand:SI 2 "and_operand" "?r,L,K,J")))
+ (match_operand:SI 2 "and_operand" "?r,T,K,J")))
(clobber (match_scratch:CC 3 "=X,X,x,x"))]
""
"@
(define_insn "*andsi3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L"))
+ (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
(const_int 0)))
(clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
(clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
(define_insn "*andsi3_internal3"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
- (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L"))
+ (match_operand:SI 2 "and_operand" "r,K,J,T,r,K,J,T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
(and:SI (match_dup 1)
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
- (match_operand:SI 3 "mask_operand" "L")))]
+ (match_operand:SI 3 "mask_operand" "T")))]
""
"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
""
(compare:CC (and:SI
(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_cint_operand" "ri"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L")))]
+ (match_operand:SI 3 "mask_operand" "T")))]
"includes_lshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_lshift_p (operands[2], operands[3])"
(compare:CC
(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L")))]
+ (match_operand:SI 3 "mask_operand" "T")))]
"includes_rshift_p (operands[2], operands[3])"
"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(clobber (match_scratch:SI 4 "=r"))]
"includes_rshift_p (operands[2], operands[3])"
(compare:CC
(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i"))
- (match_operand:SI 3 "mask_operand" "L"))
+ (match_operand:SI 3 "mask_operand" "T"))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
(define_insn "*adddi3_internal1"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
- (match_operand:DI 2 "add_operand" "r,I,I,J")))]
+ (match_operand:DI 2 "add_operand" "r,I,I,L")))]
"TARGET_POWERPC64"
"@
add %0,%1,%2
and. %0,%1,%2
andi. %0,%1,%b2
andis. %0,%1,%u2
- rldic%B2. %3,%1,0,%S2"
+ rldic%B2. %0,%1,0,%S2"
[(set_attr "type" "compare,compare,compare,delayed_compare")])
(define_expand "iordi3"
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))]
+ (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
"@
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
- (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
+ (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
"@
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
- (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
+ (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"