aarch64: Add support for unpacked sub [PR96366]

The test case bb-slp-20.c in the gcc testsuit will cause an
ICE in the expand pass due to the lack of a pattern for
subtraction of the VNx2SI mode. This patch solve this problem
by adding support for unpacked sub.

gcc/ChangeLog:

	* config/aarch64/aarch64-sve.md (sub<mode>3): Add support for
	unpacked vectors.

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 9d06bf719b5bd2d3405db89d49f9b4a4b893cee8..182813c1c5c36043c5fb29a352d7904b8a6e8c0e 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3644,10 +3644,10 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn "sub<mode>3"
-  [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w")
-       (minus:SVE_FULL_I
-         (match_operand:SVE_FULL_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa")
-         (match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w")))]
+  [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
+       (minus:SVE_I
+         (match_operand:SVE_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa")
+         (match_operand:SVE_I 2 "register_operand" "w, 0, w")))]
   "TARGET_SVE"
   "@
    sub\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>