call value_bits_sign direct

diff --git a/pipestage.py b/pipestage.py
index 60741ea66c025bcafd916f244dec3e2444960147..91087a0ae54e9eae0a80739aa8a41be2edbe176d 100644 (file)
--- a/pipestage.py
+++ b/pipestage.py
@@ -1,8 +1,9 @@
 """ Example 5: Making use of PyRTL and Introspection. """
 
 from copy import deepcopy
-from migen import *
+from migen import Module, Signal
 from migen.fhdl import verilog
+from migen.fhdl.bitcontainer import value_bits_sign
 
 
 # The following example shows how pyrtl can be used to make some interesting
@@ -46,7 +47,7 @@ class SimplePipeline(object):
             next_stage = self._current_stage_num + 1
             pipereg_id = str(self._current_stage_num) + 'to' + str(next_stage)
             rname = 'pipereg_' + pipereg_id + '_' + name
-            new_pipereg = Signal(len(value), name_override=rname)
+            new_pipereg = Signal(value_bits_sign(value), name_override=rname)
             if next_stage not in self._pipeline_register_map:
                 self._pipeline_register_map[next_stage] = {}
             self._pipeline_register_map[next_stage][name] = new_pipereg
@@ -58,11 +59,10 @@ class SimplePipelineExample(SimplePipeline):
 
     def __init__(self, pipe):
         super(SimplePipelineExample, self).__init__(pipe)
-        self._loopback = Signal()
+        self._loopback = Signal(4)
         self._setup()
 
     def stage0(self):
-        n = Signal()
         self.n = ~self._loopback
 
     def stage1(self):