fhdl.ast.Signal: implement attrs field.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 6fe578802a488705f7bc47d6ec6faca898d6fead..2bc20a4300c0765c317aacc77f3d2c01fc45683e 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -62,6 +62,12 @@ class _ModuleBuilder(_Namer, _Bufferer):
         self._append("end\n")
         self.rtlil._buffer.write(str(self))
 
+    def attribute(self, name, value):
+        if isinstance(value, str):
+            self._append("attribute \\{} \"{}\"\n", name, value.replace("\"", "\\\""))
+        else:
+            self._append("attribute \\{} {}\n", name, int(value))
+
     def wire(self, width, port_id=None, port_kind=None, name=None, src=""):
         self._src(src)
         name = self._make_name(name, local=False)
@@ -260,6 +266,8 @@ class _ValueTransformer(xfrm.ValueTransformer):
                 wire_name = "{}_{}".format(self.sub_name, node.name)
             else:
                 wire_name = node.name
+            for attr_name, attr_value in node.attrs.items():
+                self.rtlil.attribute(attr_name, attr_value)
             wire_curr = self.rtlil.wire(width=node.nbits, name=wire_name,
                                         port_id=port_id, port_kind=port_kind)
             if node in self.driven:

diff --git a/nmigen/fhdl/ast.py b/nmigen/fhdl/ast.py
index 74a0ca56158fb6f184b84502acfc16a39a429b3a..0c832fe9e60567519c1ba0df66a172da2c27beb6 100644 (file)
--- a/nmigen/fhdl/ast.py
+++ b/nmigen/fhdl/ast.py
@@ -502,6 +502,8 @@ class Signal(Value, DUID):
         If `bits_sign` is `None`, the signal bit width and signedness are
         determined by the integer range given by `min` (inclusive,
         defaults to 0) and `max` (exclusive, defaults to 2).
+    attrs : dict
+        Dictionary of synthesis attributes.
 
     Attributes
     ----------
@@ -509,9 +511,12 @@ class Signal(Value, DUID):
     signed : bool
     name : str
     reset : int
+    reset_less : bool
+    attrs : dict
     """
 
-    def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=None, max=None):
+    def __init__(self, bits_sign=None, name=None, reset=0, reset_less=False, min=None, max=None,
+                 attrs=None):
         super().__init__()
 
         if name is None:
@@ -546,6 +551,8 @@ class Signal(Value, DUID):
         self.reset = reset
         self.reset_less = reset_less
 
+        self.attrs = OrderedDict(() if attrs is None else attrs)
+
     def bits_sign(self):
         return self.nbits, self.signed
 

diff --git a/nmigen/genlib/cdc.py b/nmigen/genlib/cdc.py
index 122dcbce79a6c2fa29f1c594d43a49f7826f32e8..a6c1fc266381fbf3a715dbd13083621aea08f15e 100644 (file)
--- a/nmigen/genlib/cdc.py
+++ b/nmigen/genlib/cdc.py
@@ -4,14 +4,14 @@ from ..fhdl import *
 __all__ = ["MultiReg"]
 
 
-class MultiReg(Module):
+class MultiReg:
     def __init__(self, i, o, odomain="sys", n=2, reset=0):
         self.i = i
         self.o = o
         self.odomain = odomain
 
         self._regs = [Signal(self.i.bits_sign(), name="cdc{}".format(i),
-                             reset=reset, reset_less=True)#, attrs=("no_retiming",))
+                             reset=reset, reset_less=True, attrs={"no_retiming": True})
                       for i in range(n)]
 
     def get_fragment(self, platform):