abc9 cleanup

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 68e54f51817bce9ba83332ef951dde30bb8c6843..de47de92e5433541565f7168dc499603dc2a0364 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -892,21 +892,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                        log_assert(GetSize(signal) >= GetSize(remap_wire));
 
+                       log_assert(w->port_input || w->port_output);
+                       RTLIL::SigSig conn;
                        if (w->port_input) {
-                               RTLIL::SigSig conn;
                                conn.first = remap_wire;
                                conn.second = signal;
                                in_wires++;
-                               module->connect(conn);
                        }
-                       else if (w->port_output) {
-                               RTLIL::SigSig conn;
+                       if (w->port_output) {
                                conn.first = signal;
                                conn.second = remap_wire;
                                out_wires++;
-                               module->connect(conn);
                        }
-                       else log_abort();
+                       module->connect(conn);
                }
 
                //log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);