"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
{
blorp_init(&brw->blorp, brw, &brw->isl_dev);
- brw->blorp.compiler = brw->intelScreen->compiler;
+ brw->blorp.compiler = brw->screen->compiler;
switch (brw->gen) {
case 6:
/* Begin the compilation:
*/
- brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx);
+ brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
c.func.single_program_flow = 1;
if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) {
fprintf(stderr, "clip:\n");
- brw_disassemble(brw->intelScreen->devinfo, c.func.store,
+ brw_disassemble(brw->screen->devinfo, c.func.store,
0, program_size, stderr);
fprintf(stderr, "\n");
}
const char *const brw_vendor_string = "Intel Open Source Technology Center";
static const char *
-get_bsw_model(const struct intel_screen *intelScreen)
+get_bsw_model(const struct intel_screen *screen)
{
- switch (intelScreen->eu_total) {
+ switch (screen->eu_total) {
case 16:
return "405";
case 12:
}
const char *
-brw_get_renderer_string(const struct intel_screen *intelScreen)
+brw_get_renderer_string(const struct intel_screen *screen)
{
const char *chipset;
static char buffer[128];
char *bsw = NULL;
- switch (intelScreen->deviceID) {
+ switch (screen->deviceID) {
#undef CHIPSET
#define CHIPSET(id, symbol, str) case id: chipset = str; break;
#include "pci_ids/i965_pci_ids.h"
}
/* Braswell branding is funny, so we have to fix it up here */
- if (intelScreen->deviceID == 0x22B1) {
+ if (screen->deviceID == 0x22B1) {
bsw = strdup(chipset);
char *needle = strstr(bsw, "XXX");
if (needle) {
- memcpy(needle, get_bsw_model(intelScreen), 3);
+ memcpy(needle, get_bsw_model(screen), 3);
chipset = bsw;
}
}
case GL_RENDERER:
return
- (GLubyte *) brw_get_renderer_string(brw->intelScreen);
+ (GLubyte *) brw_get_renderer_string(brw->screen);
default:
return NULL;
/* Quantize the derived default number of samples
*/
fb->DefaultGeometry._NumSamples =
- intel_quantize_num_samples(brw->intelScreen,
+ intel_quantize_num_samples(brw->screen,
fb->DefaultGeometry.NumSamples);
}
const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format);
- if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+ if (isl_format_supports_lossless_compression(brw->screen->devinfo,
brw_format))
return false;
struct brw_context *brw = brw_context(ctx);
__DRIcontext *driContext = brw->driContext;
__DRIdrawable *driDrawable = driContext->driDrawablePriv;
- __DRIscreen *const dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *const dri_screen = brw->screen->driScrnPriv;
if (brw->front_buffer_dirty && _mesa_is_winsys_fbo(ctx->DrawBuffer)) {
if (flushFront(dri_screen) && driDrawable &&
functions->NewTransformFeedback = brw_new_transform_feedback;
functions->DeleteTransformFeedback = brw_delete_transform_feedback;
- if (brw->intelScreen->has_mi_math_and_lrr) {
+ if (brw->screen->has_mi_math_and_lrr) {
functions->BeginTransformFeedback = hsw_begin_transform_feedback;
functions->EndTransformFeedback = hsw_end_transform_feedback;
functions->PauseTransformFeedback = hsw_pause_transform_feedback;
brw_initialize_context_constants(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
const bool stage_exists[MESA_SHADER_STAGES] = {
[MESA_SHADER_VERTEX] = true,
BRW_MAX_SOL_BINDINGS / BRW_MAX_SOL_BUFFERS;
ctx->Const.AlwaysUseGetTransformFeedbackVertexCount =
- !brw->intelScreen->has_mi_math_and_lrr;
+ !brw->screen->has_mi_math_and_lrr;
int max_samples;
- const int *msaa_modes = intel_supported_msaa_modes(brw->intelScreen);
+ const int *msaa_modes = intel_supported_msaa_modes(brw->screen);
const int clamp_max_samples =
driQueryOptioni(&brw->optionCache, "clamp_max_samples");
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
ctx->Const.ShaderCompilerOptions[i] =
- brw->intelScreen->compiler->glsl_compiler_options[i];
+ brw->screen->compiler->glsl_compiler_options[i];
}
if (brw->gen >= 7) {
brw_initialize_cs_context_constants(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
- const struct intel_screen *screen = brw->intelScreen;
+ const struct intel_screen *screen = brw->screen;
const struct gen_device_info *devinfo = screen->devinfo;
/* FINISHME: Do this for all platforms that the kernel supports */
struct gl_context *ctx = &brw->ctx;
driOptionCache *options = &brw->optionCache;
- driParseConfigFiles(options, &brw->intelScreen->optionCache,
+ driParseConfigFiles(options, &brw->screen->optionCache,
brw->driContext->driScreenPriv->myNum, "i965");
int bo_reuse_mode = driQueryOptioni(options, "bo_reuse");
brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
if (driQueryOptionb(&brw->optionCache, "precise_trig"))
- brw->intelScreen->compiler->precise_trig = true;
+ brw->screen->compiler->precise_trig = true;
ctx->Const.ForceGLSLExtensionsWarn =
driQueryOptionb(options, "force_glsl_extensions_warn");
driContextPriv->driverPrivate = brw;
brw->driContext = driContextPriv;
- brw->intelScreen = screen;
+ brw->screen = screen;
brw->bufmgr = screen->bufmgr;
brw->gen = devinfo->gen;
intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
{
struct brw_context *brw = context->driverPrivate;
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
/* Set this up front, so that in case our buffers get invalidated
* while we're getting new buffers, we don't clobber the stamp and
__DRIbuffer **buffers,
int *buffer_count)
{
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
struct gl_framebuffer *fb = drawable->driverPrivate;
int i = 0;
unsigned attachments[8];
intel_update_image_buffers(struct brw_context *brw, __DRIdrawable *drawable)
{
struct gl_framebuffer *fb = drawable->driverPrivate;
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
struct intel_renderbuffer *front_rb;
struct intel_renderbuffer *back_rb;
struct __DRIimageList images;
bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
__DRIcontext *driContext;
- struct intel_screen *intelScreen;
+ struct intel_screen *screen;
};
/*======================================================================
extern const char *const brw_vendor_string;
extern const char *
-brw_get_renderer_string(const struct intel_screen *intelScreen);
+brw_get_renderer_string(const struct intel_screen *screen);
enum {
DRI_CONF_BO_REUSE_DISABLED,
prog_data.base.total_shared = prog->Comp.SharedSize;
}
- assign_cs_binding_table_offsets(brw->intelScreen->devinfo, prog,
+ assign_cs_binding_table_offsets(brw->screen->devinfo, prog,
&cp->program.Base, &prog_data);
/* Allocate the references to the uniforms that will end up in the
st_index = brw_get_shader_time_index(brw, prog, &cp->program.Base, ST_CS);
char *error_str;
- program = brw_compile_cs(brw->intelScreen->compiler, brw, mem_ctx,
+ program = brw_compile_cs(brw->screen->compiler, brw, mem_ctx,
key, &prog_data, cp->program.Base.nir,
st_index, &program_size, &error_str);
if (program == NULL) {
}
}
- const unsigned subslices = MAX2(brw->intelScreen->subslice_total, 1);
+ const unsigned subslices = MAX2(brw->screen->subslice_total, 1);
/* WaCSScratchSize:hsw
*
/* Begin the compilation:
*/
- brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx);
+ brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
c.func.single_program_flow = 1;
if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
fprintf(stderr, "gs:\n");
- brw_disassemble(brw->intelScreen->devinfo, c.func.store,
+ brw_disassemble(brw->screen->devinfo, c.func.store,
0, program_size, stderr);
fprintf(stderr, "\n");
}
struct brw_geometry_program *gp,
struct brw_gs_prog_key *key)
{
- struct brw_compiler *compiler = brw->intelScreen->compiler;
+ struct brw_compiler *compiler = brw->screen->compiler;
struct brw_stage_state *stage_state = &brw->gs.base;
struct brw_gs_prog_data prog_data;
bool start_busy = false;
memset(&prog_data, 0, sizeof(prog_data));
- assign_gs_binding_table_offsets(brw->intelScreen->devinfo, prog,
+ assign_gs_binding_table_offsets(brw->screen->devinfo, prog,
&gp->program.Base, &prog_data);
/* Allocate the references to the uniforms that will end up in the
((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
gp->program.Base.ClipDistanceArraySize;
- brw_compute_vue_map(brw->intelScreen->devinfo,
+ brw_compute_vue_map(brw->screen->devinfo,
&prog_data.base.vue_map, outputs_written,
prog->SeparateShader);
unsigned program_size;
char *error_str;
const unsigned *program =
- brw_compile_gs(brw->intelScreen->compiler, brw, mem_ctx, key,
+ brw_compile_gs(brw->screen->compiler, brw, mem_ctx, key,
&prog_data, gs->Program->nir, prog,
st_index, &program_size, &error_str);
if (program == NULL) {
struct gl_linked_shader *shader)
{
struct gl_context *ctx = &brw->ctx;
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
const struct gl_shader_compiler_options *options =
&ctx->Const.ShaderCompilerOptions[shader->Stage];
brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
{
struct brw_context *brw = brw_context(ctx);
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
unsigned int stage;
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
(void)progress;
- nir = brw_preprocess_nir(brw->intelScreen->compiler, nir);
+ nir = brw_preprocess_nir(brw->screen->compiler, nir);
if (stage == MESA_SHADER_FRAGMENT) {
static const struct nir_lower_wpos_ytransform_options wpos_options = {
case GL_VERTEX_PROGRAM_ARB: {
struct brw_vertex_program *prog = CALLOC_STRUCT(brw_vertex_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
}
case GL_FRAGMENT_PROGRAM_ARB: {
struct brw_fragment_program *prog = CALLOC_STRUCT(brw_fragment_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
}
case GL_GEOMETRY_PROGRAM_NV: {
struct brw_geometry_program *prog = CALLOC_STRUCT(brw_geometry_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
} else {
case GL_TESS_CONTROL_PROGRAM_NV: {
struct brw_tess_ctrl_program *prog = CALLOC_STRUCT(brw_tess_ctrl_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
} else {
case GL_TESS_EVALUATION_PROGRAM_NV: {
struct brw_tess_eval_program *prog = CALLOC_STRUCT(brw_tess_eval_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
} else {
case GL_COMPUTE_PROGRAM_NV: {
struct brw_compute_program *prog = CALLOC_STRUCT(brw_compute_program);
if (prog) {
- prog->id = get_new_program_id(brw->intelScreen);
+ prog->id = get_new_program_id(brw->screen);
return _mesa_init_gl_program(&prog->program.Base, target, id);
} else {
struct gl_program *prog)
{
struct brw_context *brw = brw_context(ctx);
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
switch (target) {
case GL_FRAGMENT_PROGRAM_ARB: {
if (newFP == curFP)
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
- newFP->id = get_new_program_id(brw->intelScreen);
+ newFP->id = get_new_program_id(brw->screen);
brw_add_texrect_params(prog);
if (newVP->program.IsPositionInvariant) {
_mesa_insert_mvp_code(ctx, &newVP->program);
}
- newVP->id = get_new_program_id(brw->intelScreen);
+ newVP->id = get_new_program_id(brw->screen);
/* Also tell tnl about it:
*/
struct brw_context *brw = brw_context(ctx);
uint64_t result = 0;
- switch (brw->intelScreen->hw_has_timestamp) {
+ switch (brw->screen->hw_has_timestamp) {
case 3: /* New kernel, always full 36bit accuracy */
drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result);
break;
mem_ctx = ralloc_context(NULL);
/* Begin the compilation:
*/
- brw_init_codegen(brw->intelScreen->devinfo, &c.func, mem_ctx);
+ brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
c.key = *key;
c.vue_map = brw->vue_map_geom_out;
if (unlikely(INTEL_DEBUG & DEBUG_SF)) {
fprintf(stderr, "sf:\n");
- brw_disassemble(brw->intelScreen->devinfo,
+ brw_disassemble(brw->screen->devinfo,
c.func.store, 0, program_size, stderr);
fprintf(stderr, "\n");
}
}
fprintf(stderr, "%s:\n", name);
- brw_disassemble(brw->intelScreen->devinfo, brw->cache.bo->virtual,
+ brw_disassemble(brw->screen->devinfo, brw->cache.bo->virtual,
item->offset, item->size, stderr);
}
}
void
brw_init_surface_formats(struct brw_context *brw)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
struct gl_context *ctx = &brw->ctx;
int gen;
mesa_format format;
struct brw_tcs_prog_key *key)
{
struct gl_context *ctx = &brw->ctx;
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
const struct gen_device_info *devinfo = compiler->devinfo;
struct brw_stage_state *stage_state = &brw->tcs.base;
nir_shader *nir;
struct brw_tess_eval_program *tep,
struct brw_tes_prog_key *key)
{
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct brw_compiler *compiler = brw->screen->compiler;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
struct brw_stage_state *stage_state = &brw->tes.base;
nir_shader *nir = tep->program.Base.nir;
struct brw_tes_prog_data prog_data;
struct brw_vertex_program *vp,
struct brw_vs_prog_key *key)
{
- const struct brw_compiler *compiler = brw->intelScreen->compiler;
+ const struct brw_compiler *compiler = brw->screen->compiler;
GLuint program_size;
const GLuint *program;
struct brw_vs_prog_data prog_data;
mem_ctx = ralloc_context(NULL);
brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX,
- brw->intelScreen->devinfo,
+ brw->screen->devinfo,
prog, &vp->program.Base,
&prog_data.base.base, 0);
((1 << vp->program.Base.CullDistanceArraySize) - 1) <<
vp->program.Base.ClipDistanceArraySize;
- brw_compute_vue_map(brw->intelScreen->devinfo,
+ brw_compute_vue_map(brw->screen->devinfo,
&prog_data.base.vue_map, outputs_written,
prog ? prog->SeparateShader ||
prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]
if (!prog)
prog_data.base.use_alt_mode = true;
- assign_fs_binding_table_offsets(brw->intelScreen->devinfo, prog,
+ assign_fs_binding_table_offsets(brw->screen->devinfo, prog,
&fp->program.Base, key, &prog_data);
/* Allocate the references to the uniforms that will end up in the
}
char *error_str = NULL;
- program = brw_compile_fs(brw->intelScreen->compiler, brw, mem_ctx,
+ program = brw_compile_fs(brw->screen->compiler, brw, mem_ctx,
key, &prog_data, fp->program.Base.nir,
&fp->program.Base, st_index8, st_index16,
true, brw->use_rep_send,
surf.dim = get_isl_surf_dim(target);
const enum isl_dim_layout dim_layout =
- get_isl_dim_layout(brw->intelScreen->devinfo, mt->tiling, target);
+ get_isl_dim_layout(brw->screen->devinfo, mt->tiling, target);
if (surf.dim_layout != dim_layout) {
/* The layout of the specified texture target is not compatible with the
if (!intel_miptree_is_lossless_compressed(brw, mt))
return true;
- if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+ if (isl_format_supports_lossless_compression(brw->screen->devinfo,
format))
return true;
if (irb) {
const unsigned format = brw->render_target_format[
_mesa_get_render_format(ctx, intel_rb_format(irb))];
- assert(isl_format_supports_sampling(brw->intelScreen->devinfo,
+ assert(isl_format_supports_sampling(brw->screen->devinfo,
format));
/* Override the target of the texture if the render buffer is a
static uint32_t
get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
uint32_t hw_format = brw_format_for_mesa_format(format);
if (access == GL_WRITE_ONLY) {
return hw_format;
struct brw_stage_state *stage_state = &brw->cs.base;
struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
brw_emit_buffer_surface_state(
const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0;
const uint32_t vfe_gpgpu_mode =
brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0;
- const uint32_t subslices = MAX2(brw->intelScreen->subslice_total, 1);
+ const uint32_t subslices = MAX2(brw->screen->subslice_total, 1);
OUT_BATCH(SET_FIELD(brw->max_cs_threads * subslices - 1,
MEDIA_VFE_STATE_MAX_THREADS) |
SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) |
needs_slm |= prog_data && prog_data->total_shared;
}
- return gen_get_default_l3_weights(brw->intelScreen->devinfo,
+ return gen_get_default_l3_weights(brw->screen->devinfo,
needs_dc, needs_slm);
}
ADVANCE_BATCH();
- if (brw->is_haswell && brw->intelScreen->cmd_parser_version >= 4) {
+ if (brw->is_haswell && brw->screen->cmd_parser_version >= 4) {
/* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
* them disabled to avoid crashing the system hard.
*/
static void
update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
if (brw->urb.size != sz) {
if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
const struct gen_l3_config *const cfg =
- gen_get_l3_config(brw->intelScreen->devinfo, w);
+ gen_get_l3_config(brw->screen->devinfo, w);
setup_l3_config(brw, cfg);
update_urb_size(brw, cfg);
void
gen7_restore_default_l3_config(struct brw_context *brw)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
bool gs_present, bool tess_present)
{
- const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->screen->devinfo;
const int push_size_kB =
(brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
struct intel_batchbuffer *batch = &brw->batch;
int ret;
- decode = drm_intel_decode_context_alloc(brw->intelScreen->deviceID);
+ decode = drm_intel_decode_context_alloc(brw->screen->deviceID);
if (!decode)
return;
}
if (brw->need_flush_throttle) {
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
drmCommandNone(dri_screen->fd, DRM_I915_GEM_THROTTLE);
brw->need_flush_throttle = false;
}
}
}
- if (!brw->intelScreen->no_hw) {
+ if (!brw->screen->no_hw) {
int flags;
if (brw->gen >= 6 && batch->ring == BLT_RING) {
ctx->Extensions.OES_depth_texture_cube_map = true;
ctx->Extensions.OES_sample_variables = true;
- ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp;
+ ctx->Extensions.ARB_timer_query = brw->screen->hw_has_timestamp;
/* Only enable this in core profile because other parts of Mesa behave
* slightly differently when the extension is enabled.
ctx->Extensions.ARB_transform_feedback3 = true;
ctx->Extensions.ARB_transform_feedback_instanced = true;
- if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) &&
+ if ((brw->gen >= 8 || brw->screen->cmd_parser_version >= 5) &&
ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
ctx->Extensions.ARB_compute_shader = true;
ctx->Extensions.ARB_ES3_1_compatibility =
brw->gen >= 8 || brw->is_haswell;
}
- if (brw->intelScreen->cmd_parser_version >= 2)
+ if (brw->screen->cmd_parser_version >= 2)
brw->predicate.supported = true;
}
}
ctx->Extensions.ARB_robust_buffer_access_behavior = true;
}
- if (brw->intelScreen->has_mi_math_and_lrr) {
+ if (brw->screen->has_mi_math_and_lrr) {
ctx->Extensions.ARB_query_buffer_object = true;
}
GLuint width, GLuint height)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_screen *screen = brw->intelScreen;
+ struct intel_screen *screen = brw->screen;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
assert(rb->Format != MESA_FORMAT_NONE);
{
struct brw_context *brw = brw_context(ctx);
struct intel_renderbuffer *irb;
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
__DRIimage *image;
image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle,
if (brw->gen >= 9) {
mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
const uint32_t brw_format = brw_format_for_mesa_format(linear_format);
- return isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+ return isl_format_supports_lossless_compression(brw->screen->devinfo,
brw_format);
} else
return true;
struct isl_surf *surf)
{
surf->dim = get_isl_surf_dim(mt->target);
- surf->dim_layout = get_isl_dim_layout(brw->intelScreen->devinfo,
+ surf->dim_layout = get_isl_dim_layout(brw->screen->devinfo,
mt->tiling, mt->target);
if (mt->num_samples > 1) {
int width, int height, int format,
int name, int pitch, void *loaderPrivate)
{
- struct intel_screen *intelScreen = dri_screen->driverPrivate;
+ struct intel_screen *screen = dri_screen->driverPrivate;
__DRIimage *image;
int cpp;
image->width = width;
image->height = height;
image->pitch = pitch * cpp;
- image->bo = drm_intel_bo_gem_create_from_name(intelScreen->bufmgr, "image",
+ image->bo = drm_intel_bo_gem_create_from_name(screen->bufmgr, "image",
name);
if (!image->bo) {
free(image);
void *loaderPrivate)
{
__DRIimage *image;
- struct intel_screen *intelScreen = dri_screen->driverPrivate;
+ struct intel_screen *screen = dri_screen->driverPrivate;
uint32_t tiling;
int cpp;
unsigned long pitch;
return NULL;
cpp = _mesa_get_format_bytes(image->format);
- image->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr, "image",
+ image->bo = drm_intel_bo_alloc_tiled(screen->bufmgr, "image",
width, height, cpp, &tiling,
&pitch, 0);
if (image->bo == NULL) {
int *fds, int num_fds, int *strides, int *offsets,
void *loaderPrivate)
{
- struct intel_screen *intelScreen = dri_screen->driverPrivate;
+ struct intel_screen *screen = dri_screen->driverPrivate;
struct intel_image_format *f;
__DRIimage *image;
int i, index;
size = end;
}
- image->bo = drm_intel_bo_gem_create_from_prime(intelScreen->bufmgr,
+ image->bo = drm_intel_bo_gem_create_from_prime(screen->bufmgr,
fds[0], size);
if (image->bo == NULL) {
free(image);
brw_query_renderer_integer(__DRIscreen *dri_screen,
int param, unsigned int *value)
{
- const struct intel_screen *const intelScreen =
+ const struct intel_screen *const screen =
(struct intel_screen *) dri_screen->driverPrivate;
switch (param) {
value[0] = 0x8086;
return 0;
case __DRI2_RENDERER_DEVICE_ID:
- value[0] = intelScreen->deviceID;
+ value[0] = screen->deviceID;
return 0;
case __DRI2_RENDERER_ACCELERATED:
value[0] = 1;
brw_query_renderer_string(__DRIscreen *dri_screen,
int param, const char **value)
{
- const struct intel_screen *intelScreen =
+ const struct intel_screen *screen =
(struct intel_screen *) dri_screen->driverPrivate;
switch (param) {
value[0] = brw_vendor_string;
return 0;
case __DRI2_RENDERER_DEVICE_ID:
- value[0] = brw_get_renderer_string(intelScreen);
+ value[0] = brw_get_renderer_string(screen);
return 0;
default:
break;
.base = { __DRI2_ROBUSTNESS, 1 }
};
-static const __DRIextension *intelScreenExtensions[] = {
+static const __DRIextension *screenExtensions[] = {
&intelTexBufferExtension.base,
&intelFenceExtension.base,
&intelFlushExtension.base,
static void
intelDestroyScreen(__DRIscreen * sPriv)
{
- struct intel_screen *intelScreen = sPriv->driverPrivate;
+ struct intel_screen *screen = sPriv->driverPrivate;
- dri_bufmgr_destroy(intelScreen->bufmgr);
- driDestroyOptionInfo(&intelScreen->optionCache);
+ dri_bufmgr_destroy(screen->bufmgr);
+ driDestroyOptionInfo(&screen->optionCache);
- ralloc_free(intelScreen);
+ ralloc_free(screen);
sPriv->driverPrivate = NULL;
}
}
static void
-intel_detect_sseu(struct intel_screen *intelScreen)
+intel_detect_sseu(struct intel_screen *screen)
{
- assert(intelScreen->devinfo->gen >= 8);
+ assert(screen->devinfo->gen >= 8);
int ret;
- intelScreen->subslice_total = -1;
- intelScreen->eu_total = -1;
+ screen->subslice_total = -1;
+ screen->eu_total = -1;
- ret = intel_get_param(intelScreen, I915_PARAM_SUBSLICE_TOTAL,
- &intelScreen->subslice_total);
+ ret = intel_get_param(screen, I915_PARAM_SUBSLICE_TOTAL,
+ &screen->subslice_total);
if (ret < 0 && ret != -EINVAL)
goto err_out;
- ret = intel_get_param(intelScreen,
- I915_PARAM_EU_TOTAL, &intelScreen->eu_total);
+ ret = intel_get_param(screen,
+ I915_PARAM_EU_TOTAL, &screen->eu_total);
if (ret < 0 && ret != -EINVAL)
goto err_out;
* and we have to use conservative numbers for GPGPU on many platforms, but
* otherwise, things will just work.
*/
- if (intelScreen->subslice_total < 1 || intelScreen->eu_total < 1)
+ if (screen->subslice_total < 1 || screen->eu_total < 1)
_mesa_warning(NULL,
"Kernel 4.1 required to properly query GPU properties.\n");
return;
err_out:
- intelScreen->subslice_total = -1;
- intelScreen->eu_total = -1;
+ screen->subslice_total = -1;
+ screen->eu_total = -1;
_mesa_warning(NULL, "Failed to query GPU properties (%s).\n", strerror(-ret));
}
static bool
-intel_init_bufmgr(struct intel_screen *intelScreen)
+intel_init_bufmgr(struct intel_screen *screen)
{
- __DRIscreen *dri_screen = intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = screen->driScrnPriv;
- intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL;
+ screen->no_hw = getenv("INTEL_NO_HW") != NULL;
- intelScreen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
- if (intelScreen->bufmgr == NULL) {
+ screen->bufmgr = intel_bufmgr_gem_init(dri_screen->fd, BATCH_SZ);
+ if (screen->bufmgr == NULL) {
fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
__func__, __LINE__);
return false;
}
- drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
+ drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr);
- if (!intel_get_boolean(intelScreen, I915_PARAM_HAS_RELAXED_DELTA)) {
+ if (!intel_get_boolean(screen, I915_PARAM_HAS_RELAXED_DELTA)) {
fprintf(stderr, "[%s: %u] Kernel 2.6.39 required.\n", __func__, __LINE__);
return false;
}
static const
__DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
{
- struct intel_screen *intelScreen;
+ struct intel_screen *screen;
if (dri_screen->image.loader) {
} else if (dri_screen->dri2.loader->base.version <= 2 ||
}
/* Allocate the private area */
- intelScreen = rzalloc(NULL, struct intel_screen);
- if (!intelScreen) {
+ screen = rzalloc(NULL, struct intel_screen);
+ if (!screen) {
fprintf(stderr, "\nERROR! Allocating private area failed\n");
return false;
}
/* parse information in __driConfigOptions */
- driParseOptionInfo(&intelScreen->optionCache, brw_config_options.xml);
+ driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
- intelScreen->driScrnPriv = dri_screen;
- dri_screen->driverPrivate = (void *) intelScreen;
+ screen->driScrnPriv = dri_screen;
+ dri_screen->driverPrivate = (void *) screen;
- if (!intel_init_bufmgr(intelScreen))
+ if (!intel_init_bufmgr(screen))
return false;
- intelScreen->deviceID = drm_intel_bufmgr_gem_get_devid(intelScreen->bufmgr);
- intelScreen->devinfo = gen_get_device_info(intelScreen->deviceID);
- if (!intelScreen->devinfo)
+ screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
+ screen->devinfo = gen_get_device_info(screen->deviceID);
+ if (!screen->devinfo)
return false;
brw_process_intel_debug_variable();
if (INTEL_DEBUG & DEBUG_BUFMGR)
- dri_bufmgr_set_debug(intelScreen->bufmgr, true);
+ dri_bufmgr_set_debug(screen->bufmgr, true);
- if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intelScreen->devinfo->gen < 7) {
+ if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo->gen < 7) {
fprintf(stderr,
"shader_time debugging requires gen7 (Ivybridge) or better.\n");
INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
}
if (INTEL_DEBUG & DEBUG_AUB)
- drm_intel_bufmgr_gem_set_aub_dump(intelScreen->bufmgr, true);
+ drm_intel_bufmgr_gem_set_aub_dump(screen->bufmgr, true);
#ifndef I915_PARAM_MMAP_GTT_VERSION
#define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */
#endif
- if (intel_get_integer(intelScreen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
+ if (intel_get_integer(screen, I915_PARAM_MMAP_GTT_VERSION) >= 1) {
/* Theorectically unlimited! At least for individual objects...
*
* Currently the entire (global) address space for all GTT maps is
* objects of the current maximum allocable size before running out
* of mmap space.
*/
- intelScreen->max_gtt_map_object_size = UINT64_MAX;
+ screen->max_gtt_map_object_size = UINT64_MAX;
} else {
/* Estimate the size of the mappable aperture into the GTT. There's an
* ioctl to get the whole GTT size, but not one to get the mappable subset.
* taken up by things like the framebuffer and the ringbuffer and such, so
* be more conservative.
*/
- intelScreen->max_gtt_map_object_size = gtt_size / 4;
+ screen->max_gtt_map_object_size = gtt_size / 4;
}
- intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen);
- intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen);
+ screen->hw_has_swizzling = intel_detect_swizzling(screen);
+ screen->hw_has_timestamp = intel_detect_timestamp(screen);
/* GENs prior to 8 do not support EU/Subslice info */
- if (intelScreen->devinfo->gen >= 8) {
- intel_detect_sseu(intelScreen);
- } else if (intelScreen->devinfo->gen == 7) {
- intelScreen->subslice_total = 1 << (intelScreen->devinfo->gt - 1);
+ if (screen->devinfo->gen >= 8) {
+ intel_detect_sseu(screen);
+ } else if (screen->devinfo->gen == 7) {
+ screen->subslice_total = 1 << (screen->devinfo->gt - 1);
}
const char *force_msaa = getenv("INTEL_FORCE_MSAA");
if (force_msaa) {
- intelScreen->winsys_msaa_samples_override =
- intel_quantize_num_samples(intelScreen, atoi(force_msaa));
+ screen->winsys_msaa_samples_override =
+ intel_quantize_num_samples(screen, atoi(force_msaa));
printf("Forcing winsys sample count to %d\n",
- intelScreen->winsys_msaa_samples_override);
+ screen->winsys_msaa_samples_override);
} else {
- intelScreen->winsys_msaa_samples_override = -1;
+ screen->winsys_msaa_samples_override = -1;
}
- set_max_gl_versions(intelScreen);
+ set_max_gl_versions(screen);
/* Notification of GPU resets requires hardware contexts and a kernel new
* enough to support DRM_IOCTL_I915_GET_RESET_STATS. If the ioctl is
*
* Don't even try on pre-Gen6, since we don't attempt to use contexts there.
*/
- if (intelScreen->devinfo->gen >= 6) {
+ if (screen->devinfo->gen >= 6) {
struct drm_i915_reset_stats stats;
memset(&stats, 0, sizeof(stats));
const int ret = drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats);
- intelScreen->has_context_reset_notification =
+ screen->has_context_reset_notification =
(ret != -1 || errno != EINVAL);
}
- if (intel_get_param(intelScreen, I915_PARAM_CMD_PARSER_VERSION,
- &intelScreen->cmd_parser_version) < 0) {
- intelScreen->cmd_parser_version = 0;
+ if (intel_get_param(screen, I915_PARAM_CMD_PARSER_VERSION,
+ &screen->cmd_parser_version) < 0) {
+ screen->cmd_parser_version = 0;
}
/* Haswell requires command parser version 6 in order to write to the
* MI_MATH GPR registers, and version 7 in order to use
* MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
*/
- intelScreen->has_mi_math_and_lrr = intelScreen->devinfo->gen >= 8 ||
- (intelScreen->devinfo->is_haswell &&
- intelScreen->cmd_parser_version >= 7);
-
- dri_screen->extensions = !intelScreen->has_context_reset_notification
- ? intelScreenExtensions : intelRobustScreenExtensions;
-
- intelScreen->compiler = brw_compiler_create(intelScreen,
- intelScreen->devinfo);
- intelScreen->compiler->shader_debug_log = shader_debug_log_mesa;
- intelScreen->compiler->shader_perf_log = shader_perf_log_mesa;
- intelScreen->program_id = 1;
-
- if (intelScreen->devinfo->has_resource_streamer) {
- intelScreen->has_resource_streamer =
- intel_get_boolean(intelScreen, I915_PARAM_HAS_RESOURCE_STREAMER);
+ screen->has_mi_math_and_lrr = screen->devinfo->gen >= 8 ||
+ (screen->devinfo->is_haswell &&
+ screen->cmd_parser_version >= 7);
+
+ dri_screen->extensions = !screen->has_context_reset_notification
+ ? screenExtensions : intelRobustScreenExtensions;
+
+ screen->compiler = brw_compiler_create(screen,
+ screen->devinfo);
+ screen->compiler->shader_debug_log = shader_debug_log_mesa;
+ screen->compiler->shader_perf_log = shader_perf_log_mesa;
+ screen->program_id = 1;
+
+ if (screen->devinfo->has_resource_streamer) {
+ screen->has_resource_streamer =
+ intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
}
return (const __DRIconfig**) intel_screen_make_configs(dri_screen);
int width, int height)
{
struct intel_buffer *intelBuffer;
- struct intel_screen *intelScreen = dri_screen->driverPrivate;
+ struct intel_screen *screen = dri_screen->driverPrivate;
assert(attachment == __DRI_BUFFER_FRONT_LEFT ||
attachment == __DRI_BUFFER_BACK_LEFT);
uint32_t tiling = I915_TILING_X;
unsigned long pitch;
int cpp = format / 8;
- intelBuffer->bo = drm_intel_bo_alloc_tiled(intelScreen->bufmgr,
+ intelBuffer->bo = drm_intel_bo_alloc_tiled(screen->bufmgr,
"intelAllocateBuffer",
width,
height,
/* Quantize sample count */
if (image->NumSamples) {
- image->NumSamples = intel_quantize_num_samples(brw->intelScreen, image->NumSamples);
+ image->NumSamples = intel_quantize_num_samples(brw->screen, image->NumSamples);
if (!image->NumSamples)
return false;
}
struct brw_context *brw = brw_context(ctx);
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
struct gl_texture_image *first_image = texobj->Image[0][0];
- int num_samples = intel_quantize_num_samples(brw->intelScreen,
+ int num_samples = intel_quantize_num_samples(brw->screen,
first_image->NumSamples);
const int numFaces = _mesa_num_tex_faces(texobj->Target);
int face;
{
struct brw_context *brw = brw_context(ctx);
struct intel_mipmap_tree *mt;
- __DRIscreen *dri_screen = brw->intelScreen->driScrnPriv;
+ __DRIscreen *dri_screen = brw->screen->driScrnPriv;
__DRIimage *image;
image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle,
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