#define PRINTF_WHERE_LIKE(FCN) \
void FCN (const char *file, unsigned int line, const char *format, ...) \
__attribute__ ((__format__ (__printf__, 3, 4)))
+#define PRINTF_INDENT_LIKE(FCN) \
+ void FCN (const char *file, unsigned int line, unsigned int indent, \
+ const char *format, ...) \
+ __attribute__ ((__format__ (__printf__, 4, 5)))
#else /* __GNUC__ < 2 || defined(VMS) */
#define PRINTF_WHERE_LIKE(FCN) void FCN (const char *file, \
unsigned int line, \
const char *format, ...)
+#define PRINTF_INDENT_LIKE(FCN) void FCN (const char *file, \
+ unsigned int line, \
+ unsigned int indent, \
+ const char *format, ...)
#endif /* __GNUC__ < 2 || defined(VMS) */
PRINTF_LIKE (as_warn);
PRINTF_WHERE_LIKE (as_bad_where);
PRINTF_WHERE_LIKE (as_warn_where);
+PRINTF_INDENT_LIKE (as_info_where);
void as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
void signal_init (void);
void cond_exit_macro (int);
int seen_at_least_1_file (void);
void app_pop (char *);
+void as_report_context (void);
const char * as_where (unsigned int *);
+const char * as_where_top (unsigned int *);
const char * as_where_physical (unsigned int *);
void bump_line_counters (void);
void do_scrub_begin (int);
static unsigned int physical_input_line;
static unsigned int logical_input_line;
+/* Indicator whether the origin of an update was a .linefile directive. */
+static bool is_linefile;
+
/* Struct used to save the state of the input handler during include files */
struct input_save {
char * buffer_start;
const char * logical_input_file;
unsigned int physical_input_line;
unsigned int logical_input_line;
+ bool is_linefile;
size_t sb_index;
sb from_sb;
enum expansion from_sb_expansion; /* Should we do a conditional check? */
saved->logical_input_file = logical_input_file;
saved->physical_input_line = physical_input_line;
saved->logical_input_line = logical_input_line;
+ saved->is_linefile = is_linefile;
saved->sb_index = sb_index;
saved->from_sb = from_sb;
saved->from_sb_expansion = from_sb_expansion;
logical_input_file = saved->logical_input_file;
physical_input_line = saved->physical_input_line;
logical_input_line = saved->logical_input_line;
+ is_linefile = saved->is_linefile;
sb_index = saved->sb_index;
from_sb = saved->from_sb;
from_sb_expansion = saved->from_sb_expansion;
as_fatal (_("macros nested too deeply"));
++macro_nest;
- gas_assert (expansion < expanding_nested);
-
#ifdef md_macro_start
if (expansion == expanding_macro)
{
expansion. */
newline = from->len >= 1 && from->ptr[0] != '\n';
sb_build (&from_sb, from->len + newline + 2 * sizeof (".linefile") + 30);
- if (expansion == expanding_repeat && from_sb_expansion >= expanding_macro)
- expansion = expanding_nested;
from_sb_expansion = expansion;
if (newline)
{
if (sb_index == (size_t) -1)
++physical_input_line;
- /* PR gas/16908 workaround: Don't bump logical line numbers while
- expanding macros, unless file (and maybe line; see as_where()) are
- used inside the macro. */
- if (logical_input_line != -1u && from_sb_expansion < expanding_macro)
+ if (logical_input_line != -1u)
++logical_input_line;
}
\f
case 1 << 3:
if (line_number < 0 || fname != NULL)
abort ();
- /* PR gas/16908 workaround: Ignore updates when nested inside a macro
- expansion. */
- if (from_sb_expansion == expanding_nested)
- return;
if (next_saved_file == NULL)
fname = physical_input_file;
else if (next_saved_file->logical_input_file)
abort ();
}
+ is_linefile = flags != 1 && (flags != 0 || fname);
+
if (line_number >= 0)
logical_input_line = line_number;
else if (line_number == -1 && fname && !*fname && (flags & (1 << 2)))
&& (logical_input_file == NULL
|| filename_cmp (logical_input_file, fname)))
logical_input_file = fname;
-
- /* When encountering file or line changes inside a macro, arrange for
- bump_line_counters() to henceforth increment the logical line number
- again, just like it does when expanding repeats. See as_where() for
- why changing file or line alone doesn't alter expansion mode. */
- if (from_sb_expansion == expanding_macro
- && logical_input_file != NULL
- && logical_input_line != -1u)
- from_sb_expansion = expanding_repeat;
}
void
new_logical_line_flags (fname, line_number, 0);
}
+void
+as_report_context (void)
+{
+ const struct input_save *saved = next_saved_file;
+ enum expansion expansion = from_sb_expansion;
+ int indent = 1;
+
+ if (!macro_nest)
+ return;
+
+ do
+ {
+ if (expansion != expanding_macro)
+ /* Nothing. */;
+ else if (saved->logical_input_file != NULL
+ && saved->logical_input_line != -1u)
+ as_info_where (saved->logical_input_file, saved->logical_input_line,
+ indent, _("macro invoked from here"));
+ else
+ as_info_where (saved->physical_input_file, saved->physical_input_line,
+ indent, _("macro invoked from here"));
+
+ expansion = saved->from_sb_expansion;
+ ++indent;
+ }
+ while ((saved = saved->next_saved_file) != NULL);
+}
\f
/* Return the current physical input file name and line number, if known */
return NULL;
}
-/* Return the current file name and line number. */
+/* Return the file name and line number at the top most macro
+ invocation, unless .file / .line were used inside a macro. */
const char *
as_where (unsigned int *linep)
+{
+ const char *file = as_where_top (linep);
+
+ if (macro_nest && is_linefile)
+ {
+ const struct input_save *saved = next_saved_file;
+ enum expansion expansion = from_sb_expansion;
+
+ do
+ {
+ if (!saved->is_linefile)
+ break;
+
+ if (expansion != expanding_macro)
+ /* Nothing. */;
+ else if (saved->logical_input_file != NULL
+ && (linep == NULL || saved->logical_input_line != -1u))
+ {
+ if (linep != NULL)
+ *linep = saved->logical_input_line;
+ file = saved->logical_input_file;
+ }
+ else if (saved->physical_input_file != NULL)
+ {
+ if (linep != NULL)
+ *linep = saved->physical_input_line;
+ file = saved->physical_input_file;
+ }
+
+ expansion = saved->from_sb_expansion;
+ }
+ while ((saved = saved->next_saved_file) != NULL);
+ }
+
+ return file;
+}
+
+/* Return the current file name and line number. */
+
+const char *
+as_where_top (unsigned int *linep)
{
if (logical_input_file != NULL
&& (linep == NULL || logical_input_line != -1u))
return as_where_physical (linep);
}
-
else
from_len = strlen (from);
- /* Except for macros record the present source position, such that
- diagnostics and debug info will be properly associated with the
- respective original lines, rather than with the line of the ending
- directive (TO). */
- if (from == NULL || strcasecmp (from, "MACRO") != 0)
- {
- unsigned int line;
- char *linefile;
-
- as_where (&line);
- if (!flag_m68k_mri)
- linefile = xasprintf ("\t.linefile %u .", line + 1);
- else
- linefile = xasprintf ("\tlinefile %u .", line + 1);
- sb_add_string (ptr, linefile);
- xfree (linefile);
- }
+ /* Record the present source position, such that diagnostics and debug info
+ can be properly associated with the respective original lines, rather
+ than with the line of the ending directive (TO). */
+ {
+ unsigned int line;
+ char *linefile;
+
+ as_where_top (&line);
+ if (!flag_m68k_mri)
+ linefile = xasprintf ("\t.linefile %u .", line + 1);
+ else
+ linefile = xasprintf ("\tlinefile %u .", line + 1);
+ sb_add_string (ptr, linefile);
+ xfree (linefile);
+ }
while (more)
{
}
/* PR gas/16908
- Apply and discard .linefile directives that appear within
- the macro. For long macros, one might want to report the
- line number information associated with the lines within
- the macro definition, but we would need more infrastructure
- to make that happen correctly (e.g. resetting the line
- number when expanding the macro), and since for short
- macros we clearly prefer reporting the point of expansion
- anyway, there's not an obviously better fix here. */
+ Apply .linefile directives that appear within the macro, alongside
+ keeping them for later expansion of the macro. */
if (from != NULL && strcasecmp (from, "MACRO") == 0
&& len >= 8 && strncasecmp (ptr->ptr + i, "linefile", 8) == 0)
{
s_linefile (0);
restore_ilp ();
ptr->ptr[ptr->len] = saved_eol_char;
- ptr->len = line_start;
}
}
02110-1301, USA. */
#include "as.h"
+#include <limits.h>
#include <signal.h>
/* If the system doesn't provide strsignal, we get it defined in
const char *file;
unsigned int line;
- file = as_where (&line);
+ file = as_where_top (&line);
identify (file);
if (file)
{
}
}
+/* Send to stderr a string as information, with location data passed in.
+ Note that for now this is not intended for general use. */
+
+void
+as_info_where (const char *file, unsigned int line, unsigned int indent,
+ const char *format, ...)
+{
+ va_list args;
+ char buffer[2000];
+
+ gas_assert (file != NULL && line > 0 && indent <= INT_MAX);
+
+ va_start (args, format);
+ vsnprintf (buffer, sizeof (buffer), format, args);
+ va_end (args);
+ fprintf (stderr, "%s:%u: %*s%s%s\n",
+ file, line, (int)indent, "", _("Info: "), buffer);
+}
+
/* Send to stderr a string as a warning, and locate warning
in input file(s).
Please only use this for when we have some recovery action.
vfprintf (stderr, format, args);
va_end (args);
(void) putc ('\n', stderr);
+ as_report_context ();
}
/* The common portion of as_warn and as_warn_where. */
static void
as_warn_internal (const char *file, unsigned int line, char *buffer)
{
+ bool context = false;
+
++warning_count;
if (file == NULL)
- file = as_where (&line);
+ {
+ file = as_where_top (&line);
+ context = true;
+ }
identify (file);
if (file)
}
else
fprintf (stderr, "%s%s\n", _("Warning: "), buffer);
+
+ if (context)
+ as_report_context ();
+
#ifndef NO_LISTING
listing_warning (buffer);
#endif
}
}
-/* Like as_bad but the file name and line number are passed in.
+/* Like as_warn but the file name and line number are passed in.
Unfortunately, we have to repeat the function in order to handle
the varargs correctly and portably. */
static void
as_bad_internal (const char *file, unsigned int line, char *buffer)
{
+ bool context = false;
+
++error_count;
if (file == NULL)
- file = as_where (&line);
+ {
+ file = as_where_top (&line);
+ context = true;
+ }
identify (file);
if (file)
}
else
fprintf (stderr, "%s%s\n", _("Error: "), buffer);
+
+ if (context)
+ as_report_context ();
+
#ifndef NO_LISTING
listing_error (buffer);
#endif
vfprintf (stderr, format, args);
(void) putc ('\n', stderr);
va_end (args);
+ as_report_context ();
/* Delete the output file, if it exists. This will prevent make from
thinking that a file was created and hence does not need rebuilding. */
if (out_file_name != NULL)
fprintf (stderr, _("Internal error in %s at %s:%d.\n"), fn, file, line);
else
fprintf (stderr, _("Internal error at %s:%d.\n"), file, line);
+ as_report_context ();
fprintf (stderr, _("Please report this bug.\n"));
/* Actually in input-scrub.c. */
enum expansion {
- /* Note: Order matters! */
expanding_none,
expanding_repeat,
expanding_macro,
- expanding_nested, /* Only for internal use of input-scrub.c. */
};
extern void input_scrub_include_sb (sb *, char *, enum expansion);
[^:]*: Assembler messages:
-[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:18: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:19: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:20: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:21: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:22: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:23: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:24: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:25: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:26: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:27: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:28: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:29: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:30: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:31: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:32: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:33: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:34: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:35: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:36: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:37: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:38: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:39: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:40: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:41: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:42: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:43: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v16.h\[0\]'
-[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v27.h\[0\]'
-[^:]*:44: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v31.h\[0\]'
-[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:45: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:46: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:47: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:48: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v16.h\[0\]'
-[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v27.h\[0\]'
-[^:]*:49: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v31.h\[0\]'
-[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v16.h\[0\]'
-[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v27.h\[0\]'
-[^:]*:50: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v31.h\[0\]'
-[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v16.h\[0\]'
-[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v27.h\[0\]'
-[^:]*:52: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v31.h\[0\]'
-[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v16.h\[0\]'
-[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v27.h\[0\]'
-[^:]*:53: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v31.h\[0\]'
-[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v16.h\[0\]'
-[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v27.h\[0\]'
-[^:]*:54: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v31.h\[0\]'
-[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v16.h\[0\]'
-[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v27.h\[0\]'
-[^:]*:55: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v31.h\[0\]'
-[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v16.h\[0\]'
-[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v27.h\[0\]'
-[^:]*:56: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v31.h\[0\]'
-[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v16.h\[0\]'
-[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v27.h\[0\]'
-[^:]*:57: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v31.h\[0\]'
-[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v16.h\[0\]'
-[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v27.h\[0\]'
-[^:]*:58: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v31.h\[0\]'
-[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v16.h\[0\]'
-[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v27.h\[0\]'
-[^:]*:59: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v31.h\[0\]'
-[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v16.h\[0\]'
-[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v27.h\[0\]'
-[^:]*:60: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v31.h\[0\]'
-[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v16.h\[0\]'
-[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v27.h\[0\]'
-[^:]*:61: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v31.h\[0\]'
-[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v16.h\[0\]'
-[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v27.h\[0\]'
-[^:]*:62: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v31.h\[0\]'
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:18: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:18: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmla v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:18: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:19: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:19: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:19: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:20: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:20: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlal2 v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:20: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmls v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:22: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:22: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:22: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmlsl2 v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:24: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:24: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmul v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:24: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:25: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:25: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `fmulx v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:25: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:26: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:26: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mla v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:26: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:27: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:27: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mls v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:27: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:28: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:28: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `mul v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:28: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:29: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:29: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:29: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:30: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:30: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlal2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:30: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:31: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:31: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:31: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:32: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:32: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smlsl2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:32: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:33: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:33: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:33: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:34: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:34: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `smull2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:34: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:35: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:35: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:35: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:36: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:36: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:36: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:37: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:37: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:37: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:38: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:38: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:38: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:39: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:39: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:39: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:40: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:40: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:40: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:41: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:41: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:41: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:42: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:42: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:42: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:43: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:43: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:43: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v16.h\[0\]'
+[^:]*:44: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v27.h\[0\]'
+[^:]*:44: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh v2.4h,v12.4h,v31.h\[0\]'
+[^:]*:44: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:45: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:45: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:45: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:46: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:46: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlal2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:46: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:47: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:47: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:47: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:48: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:48: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umlsl2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:48: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v16.h\[0\]'
+[^:]*:49: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v27.h\[0\]'
+[^:]*:49: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull v2.4s,v12.4h,v31.h\[0\]'
+[^:]*:49: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v16.h\[0\]'
+[^:]*:50: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v27.h\[0\]'
+[^:]*:50: *Info: macro .*
+[^:]*:4: Error: register number out of range 0 to 15 at operand 3 -- `umull2 v2.4s,v12.8h,v31.h\[0\]'
+[^:]*:50: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v16.h\[0\]'
+[^:]*:52: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v27.h\[0\]'
+[^:]*:52: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlal s2,h12,v31.h\[0\]'
+[^:]*:52: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v16.h\[0\]'
+[^:]*:53: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v27.h\[0\]'
+[^:]*:53: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmlsl s2,h12,v31.h\[0\]'
+[^:]*:53: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v16.h\[0\]'
+[^:]*:54: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v27.h\[0\]'
+[^:]*:54: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmull s2,h12,v31.h\[0\]'
+[^:]*:54: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v16.h\[0\]'
+[^:]*:55: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v27.h\[0\]'
+[^:]*:55: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqdmulh h2,h12,v31.h\[0\]'
+[^:]*:55: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v16.h\[0\]'
+[^:]*:56: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v27.h\[0\]'
+[^:]*:56: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmulh h2,h12,v31.h\[0\]'
+[^:]*:56: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v16.h\[0\]'
+[^:]*:57: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v27.h\[0\]'
+[^:]*:57: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmla h2,h12,v31.h\[0\]'
+[^:]*:57: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v16.h\[0\]'
+[^:]*:58: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v27.h\[0\]'
+[^:]*:58: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmls h2,h12,v31.h\[0\]'
+[^:]*:58: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v16.h\[0\]'
+[^:]*:59: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v27.h\[0\]'
+[^:]*:59: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmul h2,h12,v31.h\[0\]'
+[^:]*:59: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v16.h\[0\]'
+[^:]*:60: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v27.h\[0\]'
+[^:]*:60: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `fmulx h2,h12,v31.h\[0\]'
+[^:]*:60: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v16.h\[0\]'
+[^:]*:61: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v27.h\[0\]'
+[^:]*:61: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlah h2,h12,v31.h\[0\]'
+[^:]*:61: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v16.h\[0\]'
+[^:]*:62: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v27.h\[0\]'
+[^:]*:62: *Info: macro .*
+[^:]*:12: Error: register number out of range 0 to 15 at operand 3 -- `sqrdmlsh h2,h12,v31.h\[0\]'
+[^:]*:62: *Info: macro .*
[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]'
[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]'
[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]'
-[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
-[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
-[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
-[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
-[^:]+:23: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
-[^:]+:23: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!'
-[^:]+:23: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8'
+[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]'
+[^:]+:23: Info: macro .*
+[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]'
+[^:]+:23: Info: macro .*
+[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!'
+[^:]+:23: Info: macro .*
+[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8'
+[^:]+:23: Info: macro .*
+[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]'
+[^:]+:23: Info: macro .*
+[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]'
+[^:]+:23: Info: macro .*
+[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!'
+[^:]+:23: Info: macro .*
+[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8'
+[^:]+:23: Info: macro .*
+[^:]+:5: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]'
+[^:]+:23: Info: macro .*
+[^:]+:6: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]'
+[^:]+:23: Info: macro .*
+[^:]+:7: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!'
+[^:]+:23: Info: macro .*
+[^:]+:8: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8'
+[^:]+:23: Info: macro .*
[^:]*: Assembler messages:
-[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cas w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casa w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casl w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casal w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casb w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casb w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `cash w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cash w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casab w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casab w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `caslb w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `caslb w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casalb w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casalb w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casah w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casah w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `caslh w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `caslh w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casalh w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casalh w2,w3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `cas x2,x3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casa x2,x3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casl x2,x3,\[w4\]'
-[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]'
-[^:]*:68: Error: 64-bit integer or SP register expected at operand 3 -- `casal x2,x3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swp w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpa w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpl w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpal w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpb w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpb w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swph w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swph w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpab w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpab w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swplb w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swplb w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpalb w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpalb w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpah w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpah w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swplh w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swplh w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpalh w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpalh w2,w3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swp x2,x3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpa x2,x3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpl x2,x3,\[w4\]'
-[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
-[^:]*:69: Error: 64-bit integer or SP register expected at operand 3 -- `swpal x2,x3,\[w4\]'
-[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]'
-[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `casp w4,w4,w6,w7,\[sp\]'
-[^:]*:70: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]'
-[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `casp x4,x5,x6,x7,\[w8\]'
-[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]'
-[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspa w4,w4,w6,w7,\[sp\]'
-[^:]*:70: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]'
-[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]'
-[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]'
-[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspl w4,w4,w6,w7,\[sp\]'
-[^:]*:70: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]'
-[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]'
-[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]'
-[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspal w4,w4,w6,w7,\[sp\]'
-[^:]*:70: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]'
-[^:]*:70: Error: 64-bit integer or SP register expected at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]'
-[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldset w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldseth w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseth w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldset x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminab w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminab w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalb w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminah w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminah w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalh w2,w3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl x2,x3,\[w4\]'
-[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
-[^:]*:71: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal x2,x3,\[w4\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stadd w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `staddb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `staddh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `staddlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `staddlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stadd x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `staddl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclr w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stclrb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stclrh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stclrlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stclrlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclr x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steor w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `steorb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `steorh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `steorlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `steorlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steor x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `steorl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stset w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsetb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stseth x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stseth w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsetlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsetlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stset x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsmaxb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsmaxh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsmaxlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsmaxlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsminb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsminh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsminlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stsminlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumax w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stumaxb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stumaxh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stumaxlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stumaxlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumax x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumin w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stuminb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stuminh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminh w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stuminlb x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlb w2,\[w3\]'
-[^:]*:72: Error: operand mismatch -- `stuminlh x0,\[x2\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlh w2,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stumin x0,\[w3\]'
-[^:]*:72: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl x0,\[w3\]'
+[^:]*:26: Error: operand mismatch -- `cas w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cas w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casa w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casa w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casl w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casl w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casal w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casal w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casb w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casb w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `cash w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `cash w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casab w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casab w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `caslb w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslb w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casalb w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalb w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casah w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casah w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `caslh w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `caslh w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `casalh w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `casalh w2,w3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `cas w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `cas x2,x3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `casa w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casa x2,x3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `casl w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casl x2,x3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `casal w0,x1,\[x2\]'
+[^:]*:68: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `casal x2,x3,\[w4\]'
+[^:]*:68: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swp w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swp w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpa w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpl w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpal w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpb w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpb w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swph w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swph w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpab w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpab w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swplb w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplb w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpalb w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalb w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpah w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpah w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swplh w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swplh w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `swpalh w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `swpalh w2,w3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `swp w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swp x2,x3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `swpa w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpa x2,x3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `swpl w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpl x2,x3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `swpal w0,x1,\[x2\]'
+[^:]*:69: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `swpal x2,x3,\[w4\]'
+[^:]*:69: *Info: macro .*
+[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]'
+[^:]*:70: *Info: macro .*
+[^:]*:48: Error: reg pair must be contiguous at operand 2 -- `casp w4,w4,w6,w7,\[sp\]'
+[^:]*:70: *Info: macro .*
+[^:]*:49: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]'
+[^:]*:70: *Info: macro .*
+[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `casp x4,x5,x6,x7,\[w8\]'
+[^:]*:70: *Info: macro .*
+[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]'
+[^:]*:70: *Info: macro .*
+[^:]*:48: Error: reg pair must be contiguous at operand 2 -- `caspa w4,w4,w6,w7,\[sp\]'
+[^:]*:70: *Info: macro .*
+[^:]*:49: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]'
+[^:]*:70: *Info: macro .*
+[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspa x4,x5,x6,x7,\[w8\]'
+[^:]*:70: *Info: macro .*
+[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]'
+[^:]*:70: *Info: macro .*
+[^:]*:48: Error: reg pair must be contiguous at operand 2 -- `caspl w4,w4,w6,w7,\[sp\]'
+[^:]*:70: *Info: macro .*
+[^:]*:49: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]'
+[^:]*:70: *Info: macro .*
+[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspl x4,x5,x6,x7,\[w8\]'
+[^:]*:70: *Info: macro .*
+[^:]*:47: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]'
+[^:]*:70: *Info: macro .*
+[^:]*:48: Error: reg pair must be contiguous at operand 2 -- `caspal w4,w4,w6,w7,\[sp\]'
+[^:]*:70: *Info: macro .*
+[^:]*:49: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]'
+[^:]*:70: *Info: macro .*
+[^:]*:50: Error: 64-bit integer or SP register expected at operand 5 -- `caspal x4,x5,x6,x7,\[w8\]'
+[^:]*:70: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldadd w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadd x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldadda w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldadda x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldaddal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldclralh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldclr w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclr x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldclra w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclra x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclrl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldclral w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldclral x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoralh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldeor w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeor x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldeora w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeora x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeorl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldeoral x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldset w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldseth w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldseth w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldset w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldset x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldseta w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldseta x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsetal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmax x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxa x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmaxal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmin x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsmina x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldsminal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumax w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumax x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxa x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumaxal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminab w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminab w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalb w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminah w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminah w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminlh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:26: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:27: Error: 64-bit integer or SP register expected at operand 3 -- `lduminalh w2,w3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumin w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumin x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `ldumina w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `ldumina x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `lduminl w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminl x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:30: Error: operand mismatch -- `lduminal w0,x1,\[x2\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:31: Error: 64-bit integer or SP register expected at operand 3 -- `lduminal x2,x3,\[w4\]'
+[^:]*:56: *Info: macro .*
+[^:]*:71: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stadd w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `staddb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `staddh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `staddlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `staddlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `staddlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stadd x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `staddl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclr w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stclrb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stclrh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stclrlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stclrlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stclrlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclr x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stclrl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steor w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `steorb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `steorh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `steorlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `steorlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `steorlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steor x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `steorl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stset w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsetb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stseth x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stseth w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsetlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsetlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsetlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stset x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsetl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsmaxb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsmaxh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsmaxlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsmaxlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmax x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmaxl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsminb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsminh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsminlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stsminlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stsminlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsmin x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stsminl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumax w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stumaxb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stumaxh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stumaxlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stumaxlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumax x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumaxl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stumin w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stuminb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stuminh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stuminlb x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlb w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:37: Error: operand mismatch -- `stuminlh x0,\[x2\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:38: Error: 64-bit integer or SP register expected at operand 2 -- `stuminlh w2,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stumin x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
+[^:]*:41: Error: 64-bit integer or SP register expected at operand 2 -- `stuminl x0,\[w3\]'
+[^:]*:62: *Info: macro .*
+[^:]*:72: *Info: macro .*
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apiakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apiakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apiakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apiakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apibkeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apibkeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apibkeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apibkeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdbkeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdbkeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdbkeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apdbkeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apgakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apgakeylo_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apgakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
[^:]*:[0-9]+: Error: selected processor does not support system register name 'apgakeyhi_el1'
+[^:]*:[0-9]+: *Info: macro .*
.*: Assembler messages:
.*: Error: selected processor does not support system register name 'lorid_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'ccsidr2_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'pmmir_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el12'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'trfcr_el12'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcfgr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcgcr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amuserenr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amuserenr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenclr0_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenclr0_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenset0_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenset0_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenclr1_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenclr1_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenset1_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcntenset1_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr00_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr00_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr01_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr01_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr02_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr02_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr03_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr03_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper00_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper01_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper02_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper03_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr10_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr10_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr11_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr11_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr12_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr12_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr13_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr13_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr14_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr14_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr15_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr15_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr16_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr16_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr17_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr17_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr18_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr18_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr19_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr19_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr110_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr110_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr111_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr111_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr112_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr112_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr113_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr113_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr114_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr114_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr115_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntr115_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper10_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper10_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper11_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper11_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper12_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper12_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper13_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper13_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper14_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper14_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper15_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper15_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper16_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper16_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper17_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper17_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper18_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper18_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper19_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper19_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper110_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper110_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper111_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper111_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper112_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper112_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper113_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper113_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper114_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper114_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper115_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevtyper115_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amcg1idr_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'cntpctss_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'cntvctss_el0'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgwtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgwtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgitr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hfgitr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hdfgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hdfgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hdfgwtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hdfgwtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hafgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hafgrtr_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff00_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff00_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff01_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff01_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff02_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff02_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff03_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff03_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff04_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff04_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff05_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff05_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff06_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff06_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff07_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff07_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff08_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff08_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff09_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff09_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff010_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff010_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff011_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff011_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff012_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff012_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff013_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff013_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff014_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff014_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff015_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff015_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff10_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff10_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff11_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff11_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff12_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff12_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff13_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff13_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff14_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff14_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff15_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff15_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff16_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff16_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff17_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff17_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff18_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff18_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff19_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff19_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff110_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff110_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff111_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff111_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff112_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff112_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff113_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff113_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff114_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff114_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff115_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'amevcntvoff115_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'cntpoff_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'cntpoff_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'pmsnevfr_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'pmsnevfr_el1'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hcrx_el2'
+.*: *Info: macro .*
.*: Error: selected processor does not support system register name 'hcrx_el2'
+.*: *Info: macro .*
.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1 -- `msr id_dfr1_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr id_mmfr5_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr id_isar6_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_iar0_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_eoir0_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_hppir0_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_dir_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_rpr_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_sgi1r_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_asgi1r_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_sgi0r_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_iar1_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,icc_eoir1_el1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr icc_hppir1_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_misr_el2,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_eisr_el2,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_elrsr_el2,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr lorid_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr ccsidr2_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr pmmir_el1,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amcfgr_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amcgcr_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper00_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper01_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper02_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amevtyper03_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr amcg1idr_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr cntpctss_el0,x1'
+.*: *Info: macro .*
.*: Warning: specified register cannot be written to at operand 1 -- `msr cntvctss_el0,x1'
+.*: *Info: macro .*
[^:]*:235: Error: .*`msr SPSel,#2'
[^:]*:237: Error: .*`tbl v0.16b,{v1.16b,v3.16b,v5.16b},v2.16b'
[^:]*:238: Error: .*`tbx v0.8b,{v1.16b,v3.16b,v5.16b,v7.16b},v2.8b'
-[^:]*:262: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
-[^:]*:262: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
-[^:]*:262: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
-[^:]*:262: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
-[^:]*:262: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
-[^:]*:262: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
-[^:]*:262: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
-[^:]*:262: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
-[^:]*:262: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
-[^:]*:262: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
-[^:]*:262: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
-[^:]*:262: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
-[^:]*:262: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
-[^:]*:262: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
-[^:]*:262: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
-[^:]*:262: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
-[^:]*:262: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
-[^:]*:262: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
-[^:]*:262: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
-[^:]*:268: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
-[^:]*:268: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
-[^:]*:268: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
-[^:]*:268: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
-[^:]*:268: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
-[^:]*:268: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
-[^:]*:268: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
-[^:]*:268: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
-[^:]*:268: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
-[^:]*:268: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
-[^:]*:268: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
-[^:]*:268: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
-[^:]*:268: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
-[^:]*:268: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
-[^:]*:268: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
-[^:]*:268: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
-[^:]*:268: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
-[^:]*:268: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
-[^:]*:288: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
-[^:]*:288: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
-[^:]*:288: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
-[^:]*:288: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
-[^:]*:288: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
-[^:]*:288: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
-[^:]*:288: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
-[^:]*:288: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
-[^:]*:288: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
-[^:]*:288: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
-[^:]*:288: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
-[^:]*:288: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
-[^:]*:288: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
-[^:]*:288: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
-[^:]*:288: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
-[^:]*:288: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
-[^:]*:288: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
-[^:]*:288: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
-[^:]*:288: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
-[^:]*:288: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
-[^:]*:288: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
-[^:]*:288: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
-[^:]*:288: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
-[^:]*:288: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
-[^:]*:294: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
-[^:]*:294: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
-[^:]*:294: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
-[^:]*:294: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
-[^:]*:294: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
-[^:]*:294: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
-[^:]*:294: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
-[^:]*:294: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
-[^:]*:294: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
-[^:]*:294: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
-[^:]*:294: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
-[^:]*:294: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
-[^:]*:294: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
-[^:]*:294: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
-[^:]*:294: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
-[^:]*:294: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
-[^:]*:294: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
-[^:]*:294: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
-[^:]*:294: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
-[^:]*:294: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
-[^:]*:294: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
-[^:]*:294: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
-[^:]*:294: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
-[^:]*:294: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
-[^:]*:294: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
-[^:]*:294: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
-[^:]*:294: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
-[^:]*:294: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
-[^:]*:294: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
-[^:]*:294: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
-[^:]*:294: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
-[^:]*:294: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:243: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`ld2 {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`ld2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:243: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`ld2 {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`ld2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:243: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`ld2 {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`ld2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:243: Error: .*`st2 {v0.8b,v2.8b},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`st2 {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`st2 {v0.8b,v1.8b,v2.8b,v3.8b},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:243: Error: .*`st2 {v0.4h,v2.4h},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`st2 {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`st2 {v0.4h,v1.4h,v2.4h,v3.4h},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:243: Error: .*`st2 {v0.2s,v2.2s},\[x0\],#16'
+[^:]*:262: *Info: macro .*
+[^:]*:244: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],#32'
+[^:]*:262: *Info: macro .*
+[^:]*:246: Error: .*`st2 {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:247: Error: .*`st2 {v0.2s,v1.2s,v2.2s,v3.2s},\[x0\],x7'
+[^:]*:262: *Info: macro .*
+[^:]*:252: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`ld2 {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`ld2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`ld2 {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`ld2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`ld2 {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`ld2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`ld2 {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`ld2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`st2 {v0.16b,v2.16b},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`st2 {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`st2 {v0.16b,v1.16b,v2.16b,v3.16b},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`st2 {v0.8h,v2.8h},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`st2 {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`st2 {v0.8h,v1.8h,v2.8h,v3.8h},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`st2 {v0.4s,v2.4s},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`st2 {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`st2 {v0.4s,v1.4s,v2.4s,v3.4s},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:252: Error: .*`st2 {v0.2d,v2.2d},\[x0\],#32'
+[^:]*:268: *Info: macro .*
+[^:]*:253: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],#64'
+[^:]*:268: *Info: macro .*
+[^:]*:255: Error: .*`st2 {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:256: Error: .*`st2 {v0.2d,v1.2d,v2.2d,v3.2d},\[x0\],x7'
+[^:]*:268: *Info: macro .*
+[^:]*:273: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`ld3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`ld4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:273: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`ld3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`ld4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:273: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`ld3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`ld4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:273: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`st3 {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`st4 {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:273: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`st3 {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`st4 {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:273: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],#24'
+[^:]*:288: *Info: macro .*
+[^:]*:274: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#32'
+[^:]*:288: *Info: macro .*
+[^:]*:275: Error: .*`st3 {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:276: Error: .*`st4 {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:288: *Info: macro .*
+[^:]*:280: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`ld3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`ld4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`ld3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`ld4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`ld3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`ld4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`ld3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`ld4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`st3 {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`st4 {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`st3 {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`st4 {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`st3 {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`st4 {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:280: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],#48'
+[^:]*:294: *Info: macro .*
+[^:]*:281: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#64'
+[^:]*:294: *Info: macro .*
+[^:]*:282: Error: .*`st3 {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:294: *Info: macro .*
+[^:]*:283: Error: .*`st4 {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:294: *Info: macro .*
[^:]*:300: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],#1'
[^:]*:301: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],#1'
[^:]*:302: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],#2'
[^:]*:305: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],#4'
[^:]*:306: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],#8'
[^:]*:307: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],#8'
-[^:]*:316: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
-[^:]*:316: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
-[^:]*:316: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
-[^:]*:319: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
-[^:]*:319: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
-[^:]*:319: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
-[^:]*:319: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
-[^:]*:319: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
-[^:]*:319: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
-[^:]*:316: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
-[^:]*:316: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
-[^:]*:316: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
-[^:]*:331: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
-[^:]*:331: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
-[^:]*:331: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
-[^:]*:334: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
-[^:]*:334: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
-[^:]*:334: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
-[^:]*:334: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
-[^:]*:334: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
-[^:]*:334: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
-[^:]*:331: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
-[^:]*:331: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
-[^:]*:331: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
-[^:]*:346: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
-[^:]*:346: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
-[^:]*:346: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
-[^:]*:349: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
-[^:]*:349: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
-[^:]*:349: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
-[^:]*:349: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
-[^:]*:349: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
-[^:]*:349: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
-[^:]*:346: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
-[^:]*:346: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
-[^:]*:346: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
+[^:]*:310: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],#4'
+[^:]*:316: *Info: macro .*
+[^:]*:311: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
+[^:]*:316: *Info: macro .*
+[^:]*:312: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
+[^:]*:316: *Info: macro .*
+[^:]*:310: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],#4'
+[^:]*:319: *Info: macro .*
+[^:]*:311: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],#6'
+[^:]*:319: *Info: macro .*
+[^:]*:312: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],#8'
+[^:]*:319: *Info: macro .*
+[^:]*:310: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],#4'
+[^:]*:319: *Info: macro .*
+[^:]*:311: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],#6'
+[^:]*:319: *Info: macro .*
+[^:]*:312: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],#8'
+[^:]*:319: *Info: macro .*
+[^:]*:310: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],#4'
+[^:]*:316: *Info: macro .*
+[^:]*:311: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],#6'
+[^:]*:316: *Info: macro .*
+[^:]*:312: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],#8'
+[^:]*:316: *Info: macro .*
+[^:]*:325: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],#8'
+[^:]*:331: *Info: macro .*
+[^:]*:326: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
+[^:]*:331: *Info: macro .*
+[^:]*:327: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
+[^:]*:331: *Info: macro .*
+[^:]*:325: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],#8'
+[^:]*:334: *Info: macro .*
+[^:]*:326: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],#12'
+[^:]*:334: *Info: macro .*
+[^:]*:327: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],#16'
+[^:]*:334: *Info: macro .*
+[^:]*:325: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],#8'
+[^:]*:334: *Info: macro .*
+[^:]*:326: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],#12'
+[^:]*:334: *Info: macro .*
+[^:]*:327: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],#16'
+[^:]*:334: *Info: macro .*
+[^:]*:325: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],#8'
+[^:]*:331: *Info: macro .*
+[^:]*:326: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],#12'
+[^:]*:331: *Info: macro .*
+[^:]*:327: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],#16'
+[^:]*:331: *Info: macro .*
+[^:]*:340: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],#16'
+[^:]*:346: *Info: macro .*
+[^:]*:341: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
+[^:]*:346: *Info: macro .*
+[^:]*:342: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
+[^:]*:346: *Info: macro .*
+[^:]*:340: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],#16'
+[^:]*:349: *Info: macro .*
+[^:]*:341: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],#24'
+[^:]*:349: *Info: macro .*
+[^:]*:342: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],#32'
+[^:]*:349: *Info: macro .*
+[^:]*:340: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],#16'
+[^:]*:349: *Info: macro .*
+[^:]*:341: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],#24'
+[^:]*:349: *Info: macro .*
+[^:]*:342: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],#32'
+[^:]*:349: *Info: macro .*
+[^:]*:340: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],#16'
+[^:]*:346: *Info: macro .*
+[^:]*:341: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],#24'
+[^:]*:346: *Info: macro .*
+[^:]*:342: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],#32'
+[^:]*:346: *Info: macro .*
[^:]*:355: Error: .*`ld1r {v0.8b,v1.8b},\[x0\],x7'
[^:]*:355: Error: .*`ld1r {v0.16b,v1.16b},\[x0\],x7'
[^:]*:355: Error: .*`ld1r {v0.4h,v1.4h},\[x0\],x7'
[^:]*:355: Error: .*`ld1r {v0.4s,v1.4s},\[x0\],x7'
[^:]*:355: Error: .*`ld1r {v0.1d,v1.1d},\[x0\],x7'
[^:]*:355: Error: .*`ld1r {v0.2d,v1.2d},\[x0\],x7'
-[^:]*:366: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
-[^:]*:370: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
-[^:]*:370: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
-[^:]*:370: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
-[^:]*:366: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
-[^:]*:366: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
-[^:]*:396: Error: .*`ld2 {v0.8B,v2.8B},\[x0\]'
-[^:]*:396: Error: .*`ld3 {v0.8B,v2.8B,v4.8B},\[x0\]'
-[^:]*:396: Error: .*`ld4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
-[^:]*:397: Error: .*`st2 {v0.8B,v2.8B},\[x0\]'
-[^:]*:397: Error: .*`st3 {v0.8B,v2.8B,v4.8B},\[x0\]'
-[^:]*:397: Error: .*`st4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
-[^:]*:399: Error: .*`ld2 {v0.16B,v2.16B},\[x0\]'
-[^:]*:399: Error: .*`ld3 {v0.16B,v2.16B,v4.16B},\[x0\]'
-[^:]*:399: Error: .*`ld4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
-[^:]*:400: Error: .*`st2 {v0.16B,v2.16B},\[x0\]'
-[^:]*:400: Error: .*`st3 {v0.16B,v2.16B,v4.16B},\[x0\]'
-[^:]*:400: Error: .*`st4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
-[^:]*:402: Error: .*`ld2 {v0.4H,v2.4H},\[x0\]'
-[^:]*:402: Error: .*`ld3 {v0.4H,v2.4H,v4.4H},\[x0\]'
-[^:]*:402: Error: .*`ld4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
-[^:]*:403: Error: .*`st2 {v0.4H,v2.4H},\[x0\]'
-[^:]*:403: Error: .*`st3 {v0.4H,v2.4H,v4.4H},\[x0\]'
-[^:]*:403: Error: .*`st4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
-[^:]*:405: Error: .*`ld2 {v0.8H,v2.8H},\[x0\]'
-[^:]*:405: Error: .*`ld3 {v0.8H,v2.8H,v4.8H},\[x0\]'
-[^:]*:405: Error: .*`ld4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
-[^:]*:406: Error: .*`st2 {v0.8H,v2.8H},\[x0\]'
-[^:]*:406: Error: .*`st3 {v0.8H,v2.8H,v4.8H},\[x0\]'
-[^:]*:406: Error: .*`st4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
-[^:]*:408: Error: .*`ld2 {v0.2S,v2.2S},\[x0\]'
-[^:]*:408: Error: .*`ld3 {v0.2S,v2.2S,v4.2S},\[x0\]'
-[^:]*:408: Error: .*`ld4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
-[^:]*:409: Error: .*`st2 {v0.2S,v2.2S},\[x0\]'
-[^:]*:409: Error: .*`st3 {v0.2S,v2.2S,v4.2S},\[x0\]'
-[^:]*:409: Error: .*`st4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
-[^:]*:411: Error: .*`ld2 {v0.4S,v2.4S},\[x0\]'
-[^:]*:411: Error: .*`ld3 {v0.4S,v2.4S,v4.4S},\[x0\]'
-[^:]*:411: Error: .*`ld4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
-[^:]*:412: Error: .*`st2 {v0.4S,v2.4S},\[x0\]'
-[^:]*:412: Error: .*`st3 {v0.4S,v2.4S,v4.4S},\[x0\]'
-[^:]*:412: Error: .*`st4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
-[^:]*:414: Error: .*`ld2 {v0.2D,v2.2D},\[x0\]'
-[^:]*:414: Error: .*`ld3 {v0.2D,v2.2D,v4.2D},\[x0\]'
-[^:]*:414: Error: .*`ld4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
-[^:]*:415: Error: .*`st2 {v0.2D,v2.2D},\[x0\]'
-[^:]*:415: Error: .*`st3 {v0.2D,v2.2D,v4.2D},\[x0\]'
-[^:]*:415: Error: .*`st4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
-[^:]*:423: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
-[^:]*:423: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
-[^:]*:423: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
-[^:]*:424: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
-[^:]*:424: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
-[^:]*:424: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
-[^:]*:426: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
-[^:]*:426: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
-[^:]*:426: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
-[^:]*:427: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
-[^:]*:427: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
-[^:]*:427: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
-[^:]*:429: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
-[^:]*:429: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
-[^:]*:429: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
-[^:]*:430: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
-[^:]*:430: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
-[^:]*:430: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
-[^:]*:432: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
-[^:]*:432: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
-[^:]*:432: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
-[^:]*:433: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
-[^:]*:433: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
-[^:]*:433: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
-[^:]*:435: Error: .*`ld2 {v0.D,v2.D}\[1\],\[x0\]'
-[^:]*:435: Error: .*`ld3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
-[^:]*:435: Error: .*`ld4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
-[^:]*:436: Error: .*`st2 {v0.D,v2.D}\[1\],\[x0\]'
-[^:]*:436: Error: .*`st3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
-[^:]*:436: Error: .*`st4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
-[^:]*:438: Error: .*`ld1r {v0.8B,v1.8B},\[x0\]'
-[^:]*:438: Error: .*`ld2r {v0.8B,v2.8B},\[x0\]'
-[^:]*:438: Error: .*`ld3r {v0.8B,v2.8B,v4.8B},\[x0\]'
-[^:]*:438: Error: .*`ld4r {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
-[^:]*:440: Error: .*`ld1r {v0.16B,v1.16B},\[x0\]'
-[^:]*:440: Error: .*`ld2r {v0.16B,v2.16B},\[x0\]'
-[^:]*:440: Error: .*`ld3r {v0.16B,v2.16B,v4.16B},\[x0\]'
-[^:]*:440: Error: .*`ld4r {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
-[^:]*:442: Error: .*`ld1r {v0.4H,v1.4H},\[x0\]'
-[^:]*:442: Error: .*`ld2r {v0.4H,v2.4H},\[x0\]'
-[^:]*:442: Error: .*`ld3r {v0.4H,v2.4H,v4.4H},\[x0\]'
-[^:]*:442: Error: .*`ld4r {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
-[^:]*:444: Error: .*`ld1r {v0.8H,v1.8H},\[x0\]'
-[^:]*:444: Error: .*`ld2r {v0.8H,v2.8H},\[x0\]'
-[^:]*:444: Error: .*`ld3r {v0.8H,v2.8H,v4.8H},\[x0\]'
-[^:]*:444: Error: .*`ld4r {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
-[^:]*:446: Error: .*`ld1r {v0.2S,v1.2S},\[x0\]'
-[^:]*:446: Error: .*`ld2r {v0.2S,v2.2S},\[x0\]'
-[^:]*:446: Error: .*`ld3r {v0.2S,v2.2S,v4.2S},\[x0\]'
-[^:]*:446: Error: .*`ld4r {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
-[^:]*:448: Error: .*`ld1r {v0.4S,v1.4S},\[x0\]'
-[^:]*:448: Error: .*`ld2r {v0.4S,v2.4S},\[x0\]'
-[^:]*:448: Error: .*`ld3r {v0.4S,v2.4S,v4.4S},\[x0\]'
-[^:]*:448: Error: .*`ld4r {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
-[^:]*:450: Error: .*`ld1r {v0.1D,v1.1D},\[x0\]'
-[^:]*:450: Error: .*`ld2r {v0.1D,v2.1D},\[x0\]'
-[^:]*:450: Error: .*`ld3r {v0.1D,v2.1D,v4.1D},\[x0\]'
-[^:]*:450: Error: .*`ld4r {v0.1D,v2.1D,v4.1D,v6.1D},\[x0\]'
-[^:]*:452: Error: .*`ld1r {v0.2D,v1.2D},\[x0\]'
-[^:]*:452: Error: .*`ld2r {v0.2D,v2.2D},\[x0\]'
-[^:]*:452: Error: .*`ld3r {v0.2D,v2.2D,v4.2D},\[x0\]'
-[^:]*:452: Error: .*`ld4r {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:359: Error: .*`ld2 {v0.b,v2.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`ld3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`ld4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`ld2 {v0.h,v2.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`ld3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`ld4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`ld2 {v0.s,v2.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`ld3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`ld4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`ld2 {v0.d,v2.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`ld3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`ld4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.8b,v2.8b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.8b,v2.8b,v4.8b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.8b,v2.8b,v4.8b,v6.8b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.16b,v2.16b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.16b,v2.16b,v4.16b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.16b,v2.16b,v4.16b,v6.16b},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.4h,v2.4h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.4h,v2.4h,v4.4h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.4h,v2.4h,v4.4h,v6.4h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.8h,v2.8h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.8h,v2.8h,v4.8h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.8h,v2.8h,v4.8h,v6.8h},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.2s,v2.2s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.2s,v2.2s,v4.2s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.2s,v2.2s,v4.2s,v6.2s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.4s,v2.4s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.4s,v2.4s,v4.4s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.4s,v2.4s,v4.4s,v6.4s},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.1d,v2.1d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.1d,v2.1d,v4.1d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.1d,v2.1d,v4.1d,v6.1d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`ld2r {v0.2d,v2.2d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:360: Error: .*`ld3r {v0.2d,v2.2d,v4.2d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:361: Error: .*`ld4r {v0.2d,v2.2d,v4.2d,v6.2d},\[x0\],x7'
+[^:]*:370: *Info: macro .*
+[^:]*:359: Error: .*`st2 {v0.b,v2.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`st3 {v0.b,v2.b,v4.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`st4 {v0.b,v2.b,v4.b,v6.b}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`st2 {v0.h,v2.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`st3 {v0.h,v2.h,v4.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`st4 {v0.h,v2.h,v4.h,v6.h}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`st2 {v0.s,v2.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`st3 {v0.s,v2.s,v4.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`st4 {v0.s,v2.s,v4.s,v6.s}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:359: Error: .*`st2 {v0.d,v2.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:360: Error: .*`st3 {v0.d,v2.d,v4.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:361: Error: .*`st4 {v0.d,v2.d,v4.d,v6.d}\[1\],\[x0\],x7'
+[^:]*:366: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.8B,v2.8B},\[x0\]'
+[^:]*:396: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:396: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:396: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.8B,v2.8B},\[x0\]'
+[^:]*:397: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:397: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:397: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.16B,v2.16B},\[x0\]'
+[^:]*:399: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:399: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:399: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.16B,v2.16B},\[x0\]'
+[^:]*:400: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:400: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:400: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.4H,v2.4H},\[x0\]'
+[^:]*:402: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:402: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:402: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.4H,v2.4H},\[x0\]'
+[^:]*:403: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:403: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:403: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.8H,v2.8H},\[x0\]'
+[^:]*:405: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:405: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:405: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.8H,v2.8H},\[x0\]'
+[^:]*:406: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:406: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:406: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.2S,v2.2S},\[x0\]'
+[^:]*:408: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:408: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:408: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.2S,v2.2S},\[x0\]'
+[^:]*:409: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:409: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:409: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.4S,v2.4S},\[x0\]'
+[^:]*:411: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:411: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:411: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.4S,v2.4S},\[x0\]'
+[^:]*:412: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:412: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:412: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.2D,v2.2D},\[x0\]'
+[^:]*:414: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:414: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:414: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.2D,v2.2D},\[x0\]'
+[^:]*:415: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:415: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:415: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:423: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:423: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:423: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:424: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:424: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:424: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:426: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:426: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:426: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.H,v2.H}\[1\],\[x0\]'
+[^:]*:427: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.H,v2.H,v4.H}\[1\],\[x0\]'
+[^:]*:427: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.H,v2.H,v4.H,v6.H}\[1\],\[x0\]'
+[^:]*:427: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:429: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:429: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:429: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:430: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:430: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:430: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:432: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:432: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:432: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.S,v2.S}\[1\],\[x0\]'
+[^:]*:433: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.S,v2.S,v4.S}\[1\],\[x0\]'
+[^:]*:433: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.S,v2.S,v4.S,v6.S}\[1\],\[x0\]'
+[^:]*:433: *Info: macro .*
+[^:]*:383: Error: .*`ld2 {v0.D,v2.D}\[1\],\[x0\]'
+[^:]*:435: *Info: macro .*
+[^:]*:387: Error: .*`ld3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
+[^:]*:435: *Info: macro .*
+[^:]*:391: Error: .*`ld4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
+[^:]*:435: *Info: macro .*
+[^:]*:383: Error: .*`st2 {v0.D,v2.D}\[1\],\[x0\]'
+[^:]*:436: *Info: macro .*
+[^:]*:387: Error: .*`st3 {v0.D,v2.D,v4.D}\[1\],\[x0\]'
+[^:]*:436: *Info: macro .*
+[^:]*:391: Error: .*`st4 {v0.D,v2.D,v4.D,v6.D}\[1\],\[x0\]'
+[^:]*:436: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.8B,v1.8B},\[x0\]'
+[^:]*:438: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.8B,v2.8B},\[x0\]'
+[^:]*:438: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.8B,v2.8B,v4.8B},\[x0\]'
+[^:]*:438: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.8B,v2.8B,v4.8B,v6.8B},\[x0\]'
+[^:]*:438: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.16B,v1.16B},\[x0\]'
+[^:]*:440: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.16B,v2.16B},\[x0\]'
+[^:]*:440: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.16B,v2.16B,v4.16B},\[x0\]'
+[^:]*:440: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.16B,v2.16B,v4.16B,v6.16B},\[x0\]'
+[^:]*:440: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.4H,v1.4H},\[x0\]'
+[^:]*:442: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.4H,v2.4H},\[x0\]'
+[^:]*:442: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.4H,v2.4H,v4.4H},\[x0\]'
+[^:]*:442: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.4H,v2.4H,v4.4H,v6.4H},\[x0\]'
+[^:]*:442: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.8H,v1.8H},\[x0\]'
+[^:]*:444: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.8H,v2.8H},\[x0\]'
+[^:]*:444: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.8H,v2.8H,v4.8H},\[x0\]'
+[^:]*:444: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.8H,v2.8H,v4.8H,v6.8H},\[x0\]'
+[^:]*:444: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.2S,v1.2S},\[x0\]'
+[^:]*:446: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.2S,v2.2S},\[x0\]'
+[^:]*:446: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.2S,v2.2S,v4.2S},\[x0\]'
+[^:]*:446: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.2S,v2.2S,v4.2S,v6.2S},\[x0\]'
+[^:]*:446: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.4S,v1.4S},\[x0\]'
+[^:]*:448: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.4S,v2.4S},\[x0\]'
+[^:]*:448: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.4S,v2.4S,v4.4S},\[x0\]'
+[^:]*:448: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.4S,v2.4S,v4.4S,v6.4S},\[x0\]'
+[^:]*:448: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.1D,v1.1D},\[x0\]'
+[^:]*:450: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.1D,v2.1D},\[x0\]'
+[^:]*:450: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.1D,v2.1D,v4.1D},\[x0\]'
+[^:]*:450: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.1D,v2.1D,v4.1D,v6.1D},\[x0\]'
+[^:]*:450: *Info: macro .*
+[^:]*:378: Error: .*`ld1r {v0.2D,v1.2D},\[x0\]'
+[^:]*:452: *Info: macro .*
+[^:]*:383: Error: .*`ld2r {v0.2D,v2.2D},\[x0\]'
+[^:]*:452: *Info: macro .*
+[^:]*:387: Error: .*`ld3r {v0.2D,v2.2D,v4.2D},\[x0\]'
+[^:]*:452: *Info: macro .*
+[^:]*:391: Error: .*`ld4r {v0.2D,v2.2D,v4.2D,v6.2D},\[x0\]'
+[^:]*:452: *Info: macro .*
[^:]*:454: Error: .*`pmull v0.1q,v1.1d,v2.1d'
[^:]*:455: Error: .*`pmull2 v0.1q,v1.2d,v2.2d'
[^:]*:459: Error: .*`scvtf d0,w1,33'
[^:]*: Assembler messages:
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.h,p1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.s,p1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `incp z1.d,p1.d'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.h,p1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.s,p1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `decp z1.d,p1.d'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.h,p1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.s,p1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqincp z1.d,p1.d'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.h,p1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.s,p1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `sqdecp z1.d,p1.d'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.b,p1,z1.b,z1.b'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.h,p1,z1.h,z1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.s,p1,z1.s,z1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clasta z1.d,p1,z1.d,z1.d'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.b,p1,z1.b,z1.b'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.h,p1,z1.h,z1.h'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.s,p1,z1.s,z1.s'
+.*: *Info: macro .*
.*: Warning: merging predicate expected due to preceding `movprfx' at operand 2 -- `clastb z1.d,p1,z1.d,z1.d'
+.*: *Info: macro .*
[^:]*: Assembler messages:
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.S,P1/M,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvt Z0.D,P1/M,Z2.S'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.S,P1/M,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzs Z0.D,P1/M,Z2.S'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.S,P1/M,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtzu Z0.D,P1/M,Z2.S'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.S,P1/M,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `scvtf Z0.D,P1/M,Z2.S'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.S,P1/M,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `ucvtf Z0.D,P1/M,Z2.S'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsl Z0.B,P1/M,Z0.B,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `lsr Z0.B,P1/M,Z0.B,Z2.D'
+.*: *Info: macro .*
.*: Warning: register size not compatible with previous `movprfx' at operand 1 -- `asr Z0.B,P1/M,Z0.B,Z2.D'
+.*: *Info: macro .*
.*:93: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.u32.f16 s11,s11,#0'
.*:94: Error: immediate value out of range -- `vcvt.f16.s32 s12,s12,#34'
.*:95: Error: immediate value out of range -- `vcvt.f16.u32 s12,s12,#-1'
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:98: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:99: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:100: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:101: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:102: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:103: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:104: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:105: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:106: Error: instruction cannot be conditional.*
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
-.*:110: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
-.*:110: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:98: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:12: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:99: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:20: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:100: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:28: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:101: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:36: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:102: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:44: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:103: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:52: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:104: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:60: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:105: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:68: Error: instruction cannot be conditional.*
+.*:106: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
+.*:78: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+.*:110: *Info: macro .*
+.*:78: IT blocks containing 32-bit Thumb instructions are performance deprecated in ARMv8-A and ARMv8-R
+.*:110: *Info: macro .*
.*:87: Error: co-processor offset out of range
.*:88: Error: co-processor offset out of range
.*:89: Error: co-processor offset out of range
[^:]*: Assembler messages:
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vabd.f16 d2,d4,d14'
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vabd.f16 q2,q4,q14'
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vmax.f16 d2,d4,d14'
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vmax.f16 q2,q4,q14'
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vmin.f16 d2,d4,d14'
-[^:]*:163: Error: selected processor does not support fp16 instruction -- `vmin.f16 q2,q4,q14'
-[^:]*:164: Error: selected processor does not support fp16 instruction -- `vabdq.f16 q0,q8,q14'
-[^:]*:164: Error: selected processor does not support fp16 instruction -- `vmaxq.f16 q0,q8,q14'
-[^:]*:164: Error: selected processor does not support fp16 instruction -- `vminq.f16 q0,q8,q14'
-[^:]*:165: Error: selected processor does not support fp16 instruction -- `vabd.f16 d1,d3,d15'
-[^:]*:166: Error: selected processor does not support fp16 instruction -- `vabd.f16 d0,d1,d8'
-[^:]*:169: Error: selected processor does not support fp16 instruction -- `vabs.f16 d0,d8'
-[^:]*:169: Error: selected processor does not support fp16 instruction -- `vabs.f16 q0,q8'
-[^:]*:169: Error: selected processor does not support fp16 instruction -- `vneg.f16 d0,d8'
-[^:]*:169: Error: selected processor does not support fp16 instruction -- `vneg.f16 q0,q8'
-[^:]*:170: Error: selected processor does not support fp16 instruction -- `vabsq.f16 q2,q6'
-[^:]*:170: Error: selected processor does not support fp16 instruction -- `vnegq.f16 q2,q6'
-[^:]*:171: Error: selected processor does not support fp16 instruction -- `vabs.f16 d7,d3'
-[^:]*:172: Error: selected processor does not support fp16 instruction -- `vneg.f16 d9,d1'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacge.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacge.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacgt.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacgt.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vaclt.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vaclt.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacle.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vacle.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vceq.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vceq.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcge.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcge.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcgt.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcgt.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcle.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vcle.f16 q2,q4,q14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vclt.f16 d2,d4,d14'
-[^:]*:175: Error: selected processor does not support fp16 instruction -- `vclt.f16 q2,q4,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vacgeq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vacgtq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vacltq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vacleq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vceqq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vcgeq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vcgtq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vcleq.f16 q0,q8,q14'
-[^:]*:176: Error: selected processor does not support fp16 instruction -- `vcltq.f16 q0,q8,q14'
-[^:]*:179: Error: selected processor does not support fp16 instruction -- `vadd.f16 d2,d4,d14'
-[^:]*:179: Error: selected processor does not support fp16 instruction -- `vadd.f16 q2,q4,q14'
-[^:]*:179: Error: selected processor does not support fp16 instruction -- `vsub.f16 d2,d4,d14'
-[^:]*:179: Error: selected processor does not support fp16 instruction -- `vsub.f16 q2,q4,q14'
-[^:]*:180: Error: selected processor does not support fp16 instruction -- `vaddq.f16 q0,q8,q14'
-[^:]*:180: Error: selected processor does not support fp16 instruction -- `vsubq.f16 q0,q8,q14'
-[^:]*:183: Error: selected processor does not support fp16 instruction -- `vmaxnm.f16 d2,d4,d14'
-[^:]*:183: Error: selected processor does not support fp16 instruction -- `vmaxnm.f16 q2,q4,q14'
-[^:]*:183: Error: selected processor does not support fp16 instruction -- `vminnm.f16 d2,d4,d14'
-[^:]*:183: Error: selected processor does not support fp16 instruction -- `vminnm.f16 q2,q4,q14'
-[^:]*:186: Error: selected processor does not support fp16 instruction -- `vfma.f16 d2,d4,d14'
-[^:]*:186: Error: selected processor does not support fp16 instruction -- `vfma.f16 q2,q4,q14'
-[^:]*:186: Error: selected processor does not support fp16 instruction -- `vfms.f16 d2,d4,d14'
-[^:]*:186: Error: selected processor does not support fp16 instruction -- `vfms.f16 q2,q4,q14'
-[^:]*:189: Error: selected processor does not support fp16 instruction -- `vmla.f16 d2,d4,d14'
-[^:]*:189: Error: selected processor does not support fp16 instruction -- `vmla.f16 q2,q4,q14'
-[^:]*:189: Error: selected processor does not support fp16 instruction -- `vmls.f16 d2,d4,d14'
-[^:]*:189: Error: selected processor does not support fp16 instruction -- `vmls.f16 q2,q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintz.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintz.f16 q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintx.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintx.f16 q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrinta.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrinta.f16 q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintn.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintn.f16 q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintp.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintp.f16 q4,q14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintm.f16 d4,d14'
-[^:]*:192: Error: selected processor does not support fp16 instruction -- `vrintm.f16 q4,q14'
-[^:]*:195: Error: selected processor does not support fp16 instruction -- `vpadd.f16 d4,d8,d14'
-[^:]*:198: Error: selected processor does not support fp16 instruction -- `vrecpe.f16 d4,d8'
-[^:]*:198: Error: selected processor does not support fp16 instruction -- `vrecpe.f16 q4,q8'
-[^:]*:198: Error: selected processor does not support fp16 instruction -- `vrsqrte.f16 d4,d8'
-[^:]*:198: Error: selected processor does not support fp16 instruction -- `vrsqrte.f16 q4,q8'
-[^:]*:199: Error: selected processor does not support fp16 instruction -- `vrecpeq.f16 q0,q10'
-[^:]*:199: Error: selected processor does not support fp16 instruction -- `vrsqrteq.f16 q0,q10'
-[^:]*:202: Error: selected processor does not support fp16 instruction -- `vrecps.f16 d8,d10,d12'
-[^:]*:202: Error: selected processor does not support fp16 instruction -- `vrecps.f16 q8,q10,q12'
-[^:]*:202: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 d8,d10,d12'
-[^:]*:202: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 q8,q10,q12'
-[^:]*:203: Error: selected processor does not support fp16 instruction -- `vrecpsq.f16 q2,q0,q4'
-[^:]*:203: Error: selected processor does not support fp16 instruction -- `vrsqrtsq.f16 q2,q0,q4'
-[^:]*:206: Error: selected processor does not support fp16 instruction -- `vpmax.f16 d4,d8,d14'
-[^:]*:207: Error: selected processor does not support fp16 instruction -- `vpmin.f16 d10,d8,d2'
-[^:]*:210: Error: selected processor does not support fp16 instruction -- `vmul.f16 d4,d8,d14'
-[^:]*:211: Error: selected processor does not support fp16 instruction -- `vmul.f16 d7,d0,d1'
-[^:]*:212: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,q0'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvta.s16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvta.s16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtm.s16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtm.s16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtn.s16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtn.s16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtp.s16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtp.s16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvta.u16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvta.u16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtm.u16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtm.u16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtn.u16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtn.u16.f16 q6,q12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtp.u16.f16 d6,d12'
-[^:]*:215: Error: selected processor does not support fp16 instruction -- `vcvtp.u16.f16 q6,q12'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 d14,d0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 q14,q0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 q14,q0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 d14,d0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 q14,q0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0'
-[^:]*:218: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 q14,q0'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 d14,d0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 q14,q0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 q14,q0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 d14,d0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 q14,q0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0,#3'
-[^:]*:221: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 q14,q0,#3'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vceq.f16 d14,d2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vceq.f16 q14,q2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcge.f16 d14,d2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcge.f16 q14,q2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcgt.f16 d14,d2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcgt.f16 q14,q2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcle.f16 d14,d2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vcle.f16 q14,q2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vclt.f16 d14,d2,#0'
-[^:]*:224: Error: selected processor does not support fp16 instruction -- `vclt.f16 q14,q2,#0'
-[^:]*:242: Error: selected processor does not support fp16 instruction -- `vmul.f16 d7,d0,d1\[0\]'
-[^:]*:243: Error: selected processor does not support fp16 instruction -- `vmul.f16 d4,d8,d6\[2\]'
-[^:]*:244: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,d0\[1\]'
-[^:]*:245: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,d7\[3\]'
-[^:]*:248: Error: selected processor does not support fp16 instruction -- `vmla.f16 d2,d4,d1\[0\]'
-[^:]*:248: Error: selected processor does not support fp16 instruction -- `vmla.f16 q2,q4,d1\[0\]'
-[^:]*:248: Error: selected processor does not support fp16 instruction -- `vmls.f16 d2,d4,d1\[0\]'
-[^:]*:248: Error: selected processor does not support fp16 instruction -- `vmls.f16 q2,q4,d1\[0\]'
-[^:]*:249: Error: selected processor does not support fp16 instruction -- `vmla.f16 d1,d8,d7\[3\]'
-[^:]*:249: Error: selected processor does not support fp16 instruction -- `vmla.f16 q1,q8,d7\[3\]'
-[^:]*:249: Error: selected processor does not support fp16 instruction -- `vmls.f16 d1,d8,d7\[3\]'
-[^:]*:249: Error: selected processor does not support fp16 instruction -- `vmls.f16 q1,q8,d7\[3\]'
+[^:]*:3: Error: selected processor does not support fp16 instruction -- `vabd.f16 d2,d4,d14'
+[^:]*:163: *Info: macro .*
+[^:]*:4: Error: selected processor does not support fp16 instruction -- `vabd.f16 q2,q4,q14'
+[^:]*:163: *Info: macro .*
+[^:]*:3: Error: selected processor does not support fp16 instruction -- `vmax.f16 d2,d4,d14'
+[^:]*:163: *Info: macro .*
+[^:]*:4: Error: selected processor does not support fp16 instruction -- `vmax.f16 q2,q4,q14'
+[^:]*:163: *Info: macro .*
+[^:]*:3: Error: selected processor does not support fp16 instruction -- `vmin.f16 d2,d4,d14'
+[^:]*:163: *Info: macro .*
+[^:]*:4: Error: selected processor does not support fp16 instruction -- `vmin.f16 q2,q4,q14'
+[^:]*:163: *Info: macro .*
+[^:]*:10: Error: selected processor does not support fp16 instruction -- `vabdq.f16 q0,q8,q14'
+[^:]*:164: *Info: macro .*
+[^:]*:10: Error: selected processor does not support fp16 instruction -- `vmaxq.f16 q0,q8,q14'
+[^:]*:164: *Info: macro .*
+[^:]*:10: Error: selected processor does not support fp16 instruction -- `vminq.f16 q0,q8,q14'
+[^:]*:164: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vabd.f16 d1,d3,d15'
+[^:]*:165: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vabd.f16 d0,d1,d8'
+[^:]*:166: *Info: macro .*
+[^:]*:16: Error: selected processor does not support fp16 instruction -- `vabs.f16 d0,d8'
+[^:]*:169: *Info: macro .*
+[^:]*:17: Error: selected processor does not support fp16 instruction -- `vabs.f16 q0,q8'
+[^:]*:169: *Info: macro .*
+[^:]*:16: Error: selected processor does not support fp16 instruction -- `vneg.f16 d0,d8'
+[^:]*:169: *Info: macro .*
+[^:]*:17: Error: selected processor does not support fp16 instruction -- `vneg.f16 q0,q8'
+[^:]*:169: *Info: macro .*
+[^:]*:23: Error: selected processor does not support fp16 instruction -- `vabsq.f16 q2,q6'
+[^:]*:170: *Info: macro .*
+[^:]*:23: Error: selected processor does not support fp16 instruction -- `vnegq.f16 q2,q6'
+[^:]*:170: *Info: macro .*
+[^:]*:154: Error: selected processor does not support fp16 instruction -- `vabs.f16 d7,d3'
+[^:]*:171: *Info: macro .*
+[^:]*:154: Error: selected processor does not support fp16 instruction -- `vneg.f16 d9,d1'
+[^:]*:172: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vacge.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vacge.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vacgt.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vacgt.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vaclt.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vaclt.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vacle.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vacle.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vceq.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vceq.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vcge.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vcge.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vcgt.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vcgt.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vcle.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vcle.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:29: Error: selected processor does not support fp16 instruction -- `vclt.f16 d2,d4,d14'
+[^:]*:175: *Info: macro .*
+[^:]*:30: Error: selected processor does not support fp16 instruction -- `vclt.f16 q2,q4,q14'
+[^:]*:175: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vacgeq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vacgtq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vacltq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vacleq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vceqq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vcgeq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vcgtq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vcleq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:43: Error: selected processor does not support fp16 instruction -- `vcltq.f16 q0,q8,q14'
+[^:]*:176: *Info: macro .*
+[^:]*:49: Error: selected processor does not support fp16 instruction -- `vadd.f16 d2,d4,d14'
+[^:]*:179: *Info: macro .*
+[^:]*:50: Error: selected processor does not support fp16 instruction -- `vadd.f16 q2,q4,q14'
+[^:]*:179: *Info: macro .*
+[^:]*:49: Error: selected processor does not support fp16 instruction -- `vsub.f16 d2,d4,d14'
+[^:]*:179: *Info: macro .*
+[^:]*:50: Error: selected processor does not support fp16 instruction -- `vsub.f16 q2,q4,q14'
+[^:]*:179: *Info: macro .*
+[^:]*:56: Error: selected processor does not support fp16 instruction -- `vaddq.f16 q0,q8,q14'
+[^:]*:180: *Info: macro .*
+[^:]*:56: Error: selected processor does not support fp16 instruction -- `vsubq.f16 q0,q8,q14'
+[^:]*:180: *Info: macro .*
+[^:]*:62: Error: selected processor does not support fp16 instruction -- `vmaxnm.f16 d2,d4,d14'
+[^:]*:183: *Info: macro .*
+[^:]*:63: Error: selected processor does not support fp16 instruction -- `vmaxnm.f16 q2,q4,q14'
+[^:]*:183: *Info: macro .*
+[^:]*:62: Error: selected processor does not support fp16 instruction -- `vminnm.f16 d2,d4,d14'
+[^:]*:183: *Info: macro .*
+[^:]*:63: Error: selected processor does not support fp16 instruction -- `vminnm.f16 q2,q4,q14'
+[^:]*:183: *Info: macro .*
+[^:]*:69: Error: selected processor does not support fp16 instruction -- `vfma.f16 d2,d4,d14'
+[^:]*:186: *Info: macro .*
+[^:]*:70: Error: selected processor does not support fp16 instruction -- `vfma.f16 q2,q4,q14'
+[^:]*:186: *Info: macro .*
+[^:]*:69: Error: selected processor does not support fp16 instruction -- `vfms.f16 d2,d4,d14'
+[^:]*:186: *Info: macro .*
+[^:]*:70: Error: selected processor does not support fp16 instruction -- `vfms.f16 q2,q4,q14'
+[^:]*:186: *Info: macro .*
+[^:]*:76: Error: selected processor does not support fp16 instruction -- `vmla.f16 d2,d4,d14'
+[^:]*:189: *Info: macro .*
+[^:]*:77: Error: selected processor does not support fp16 instruction -- `vmla.f16 q2,q4,q14'
+[^:]*:189: *Info: macro .*
+[^:]*:76: Error: selected processor does not support fp16 instruction -- `vmls.f16 d2,d4,d14'
+[^:]*:189: *Info: macro .*
+[^:]*:77: Error: selected processor does not support fp16 instruction -- `vmls.f16 q2,q4,q14'
+[^:]*:189: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrintz.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrintz.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrintx.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrintx.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrinta.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrinta.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrintn.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrintn.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrintp.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrintp.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:83: Error: selected processor does not support fp16 instruction -- `vrintm.f16 d4,d14'
+[^:]*:192: *Info: macro .*
+[^:]*:84: Error: selected processor does not support fp16 instruction -- `vrintm.f16 q4,q14'
+[^:]*:192: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vpadd.f16 d4,d8,d14'
+[^:]*:195: *Info: macro .*
+[^:]*:90: Error: selected processor does not support fp16 instruction -- `vrecpe.f16 d4,d8'
+[^:]*:198: *Info: macro .*
+[^:]*:91: Error: selected processor does not support fp16 instruction -- `vrecpe.f16 q4,q8'
+[^:]*:198: *Info: macro .*
+[^:]*:90: Error: selected processor does not support fp16 instruction -- `vrsqrte.f16 d4,d8'
+[^:]*:198: *Info: macro .*
+[^:]*:91: Error: selected processor does not support fp16 instruction -- `vrsqrte.f16 q4,q8'
+[^:]*:198: *Info: macro .*
+[^:]*:97: Error: selected processor does not support fp16 instruction -- `vrecpeq.f16 q0,q10'
+[^:]*:199: *Info: macro .*
+[^:]*:97: Error: selected processor does not support fp16 instruction -- `vrsqrteq.f16 q0,q10'
+[^:]*:199: *Info: macro .*
+[^:]*:103: Error: selected processor does not support fp16 instruction -- `vrecps.f16 d8,d10,d12'
+[^:]*:202: *Info: macro .*
+[^:]*:104: Error: selected processor does not support fp16 instruction -- `vrecps.f16 q8,q10,q12'
+[^:]*:202: *Info: macro .*
+[^:]*:103: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 d8,d10,d12'
+[^:]*:202: *Info: macro .*
+[^:]*:104: Error: selected processor does not support fp16 instruction -- `vrsqrts.f16 q8,q10,q12'
+[^:]*:202: *Info: macro .*
+[^:]*:110: Error: selected processor does not support fp16 instruction -- `vrecpsq.f16 q2,q0,q4'
+[^:]*:203: *Info: macro .*
+[^:]*:110: Error: selected processor does not support fp16 instruction -- `vrsqrtsq.f16 q2,q0,q4'
+[^:]*:203: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vpmax.f16 d4,d8,d14'
+[^:]*:206: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vpmin.f16 d10,d8,d2'
+[^:]*:207: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vmul.f16 d4,d8,d14'
+[^:]*:210: *Info: macro .*
+[^:]*:141: Error: selected processor does not support fp16 instruction -- `vmul.f16 d7,d0,d1'
+[^:]*:211: *Info: macro .*
+[^:]*:145: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,q0'
+[^:]*:212: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvta.s16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvta.s16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtm.s16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtm.s16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtn.s16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtn.s16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtp.s16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtp.s16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvta.u16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvta.u16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtm.u16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtm.u16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtn.u16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtn.u16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:116: Error: selected processor does not support fp16 instruction -- `vcvtp.u16.f16 d6,d12'
+[^:]*:215: *Info: macro .*
+[^:]*:117: Error: selected processor does not support fp16 instruction -- `vcvtp.u16.f16 q6,q12'
+[^:]*:215: *Info: macro .*
+[^:]*:123: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 d14,d0'
+[^:]*:218: *Info: macro .*
+[^:]*:124: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 q14,q0'
+[^:]*:218: *Info: macro .*
+[^:]*:123: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0'
+[^:]*:218: *Info: macro .*
+[^:]*:124: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 q14,q0'
+[^:]*:218: *Info: macro .*
+[^:]*:123: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 d14,d0'
+[^:]*:218: *Info: macro .*
+[^:]*:124: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 q14,q0'
+[^:]*:218: *Info: macro .*
+[^:]*:123: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0'
+[^:]*:218: *Info: macro .*
+[^:]*:124: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 q14,q0'
+[^:]*:218: *Info: macro .*
+[^:]*:130: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 d14,d0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:131: Error: selected processor does not support fp16 instruction -- `vcvt.s16.f16 q14,q0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:130: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 d14,d0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:131: Error: selected processor does not support fp16 instruction -- `vcvt.u16.f16 q14,q0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:130: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 d14,d0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:131: Error: selected processor does not support fp16 instruction -- `vcvt.f16.s16 q14,q0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:130: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 d14,d0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:131: Error: selected processor does not support fp16 instruction -- `vcvt.f16.u16 q14,q0,#3'
+[^:]*:221: *Info: macro .*
+[^:]*:36: Error: selected processor does not support fp16 instruction -- `vceq.f16 d14,d2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:37: Error: selected processor does not support fp16 instruction -- `vceq.f16 q14,q2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:36: Error: selected processor does not support fp16 instruction -- `vcge.f16 d14,d2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:37: Error: selected processor does not support fp16 instruction -- `vcge.f16 q14,q2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:36: Error: selected processor does not support fp16 instruction -- `vcgt.f16 d14,d2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:37: Error: selected processor does not support fp16 instruction -- `vcgt.f16 q14,q2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:36: Error: selected processor does not support fp16 instruction -- `vcle.f16 d14,d2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:37: Error: selected processor does not support fp16 instruction -- `vcle.f16 q14,q2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:36: Error: selected processor does not support fp16 instruction -- `vclt.f16 d14,d2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:37: Error: selected processor does not support fp16 instruction -- `vclt.f16 q14,q2,#0'
+[^:]*:224: *Info: macro .*
+[^:]*:227: Error: selected processor does not support fp16 instruction -- `vmul.f16 d7,d0,d1\[0\]'
+[^:]*:242: *Info: macro .*
+[^:]*:227: Error: selected processor does not support fp16 instruction -- `vmul.f16 d4,d8,d6\[2\]'
+[^:]*:243: *Info: macro .*
+[^:]*:231: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,d0\[1\]'
+[^:]*:244: *Info: macro .*
+[^:]*:231: Error: selected processor does not support fp16 instruction -- `vmul.f16 q2,q8,d7\[3\]'
+[^:]*:245: *Info: macro .*
+[^:]*:236: Error: selected processor does not support fp16 instruction -- `vmla.f16 d2,d4,d1\[0\]'
+[^:]*:248: *Info: macro .*
+[^:]*:237: Error: selected processor does not support fp16 instruction -- `vmla.f16 q2,q4,d1\[0\]'
+[^:]*:248: *Info: macro .*
+[^:]*:236: Error: selected processor does not support fp16 instruction -- `vmls.f16 d2,d4,d1\[0\]'
+[^:]*:248: *Info: macro .*
+[^:]*:237: Error: selected processor does not support fp16 instruction -- `vmls.f16 q2,q4,d1\[0\]'
+[^:]*:248: *Info: macro .*
+[^:]*:236: Error: selected processor does not support fp16 instruction -- `vmla.f16 d1,d8,d7\[3\]'
+[^:]*:249: *Info: macro .*
+[^:]*:237: Error: selected processor does not support fp16 instruction -- `vmla.f16 q1,q8,d7\[3\]'
+[^:]*:249: *Info: macro .*
+[^:]*:236: Error: selected processor does not support fp16 instruction -- `vmls.f16 d1,d8,d7\[3\]'
+[^:]*:249: *Info: macro .*
+[^:]*:237: Error: selected processor does not support fp16 instruction -- `vmls.f16 q1,q8,d7\[3\]'
+[^:]*:249: *Info: macro .*
[^:]+: Assembler messages:
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^:]+:[0-9]+: Warning: this instruction implies use of ARMv8.1 AdvSIMD.
+[^:]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmab.bf16 q0,d0,d0\[4\]'
[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmat.bf16 q0,d0,d0\[4\]'
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtb.b16.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtb.bf32.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0.b16,s0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0.bf32,s0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb s0.f32,s0.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtt.b16.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtt.bf32.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0.b16,s0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0.bf32,s0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt s0.f32,s0.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvt.b16.f32 d0,q0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvt.bf32.f32 d0,q0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0.b16,q0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0.bf32,q0.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvt d0.f32,q0.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtt.bf16.f32 s0,s0,#0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtt.bf16.f32 s0,s0,#1'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt.bf16.f32 d0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt.bf16.f32 s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt.bf16.f32 s0,s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt.bf16.f32 s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt.bf16.f32 s0,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt.bf16.f32 s32,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtb.bf16.f32 s0,s0,#0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtb.bf16.f32 s0,s0,#1'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb.bf16.f32 d0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb.bf16.f32 s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb.bf16.f32 s0,s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb.bf16.f32 s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb.bf16.f32 s0,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb.bf16.f32 s32,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vcvtne.bf16.f32 d0,q0'
[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne.bf16 d0,d20,d11'
[^ :]+:[0-9]+: Error: instruction cannot be conditional -- `vdotne.bf16 d0,d20,d11\[1\]'
[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmab\.bf16 q0,d0,d0\[4\]'
[^ :]+:[0-9]+: Error: index must be in the range 0 to 3 -- `vfmat\.bf16 q0,d0,d0\[4\]'
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtb\.b16\.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtb\.bf32\.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0\.b16,s0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb s0\.bf32,s0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb s0\.f32,s0\.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtt\.b16\.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvtt\.bf32\.f32 s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0\.b16,s0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt s0\.bf32,s0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt s0\.f32,s0\.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvt\.b16\.f32 d0,q0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad instruction `vcvt\.bf32\.f32 d0,q0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: unexpected type character `b' -- did you mean `bf'\?
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0\.b16,q0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad size 32 in type specifier
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvt d0\.bf32,q0\.f32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvt d0\.f32,q0\.bf16'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtt\.bf16\.f32 s0,s0,#0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtt\.bf16\.f32 s0,s0,#1'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtt\.bf16\.f32 d0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtt\.bf16\.f32 s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt\.bf16\.f32 s0,s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtt\.bf16\.f32 s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt\.bf16\.f32 s0,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtt\.bf16\.f32 s32,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: immediate value out of range -- `vcvtb\.bf16\.f32 s0,s0,#0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: invalid instruction shape -- `vcvtb\.bf16\.f32 s0,s0,#1'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad type in SIMD instruction -- `vcvtb\.bf16\.f32 d0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: bad arguments to instruction -- `vcvtb\.bf16\.f32 s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb\.bf16\.f32 s0,s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: constant expression required -- `vcvtb\.bf16\.f32 s0,s0,s0'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb\.bf16\.f32 s0,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: VFP single or double precision register expected -- `vcvtb\.bf16\.f32 s32,s32'
+[^ :]+:[0-9]+: *Info: macro .*
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdotne\.bf16 d0,d20,d11'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vdotne\.bf16 d0,d20,d11\[1\]'
[^ :]+:[0-9]+: Error: instruction not allowed in IT block -- `vmmlane\.bf16 q0,q0,q0'
[^:]*: Assembler messages:
-[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]'
-[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]'
-[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]'
-[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]'
-[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]'
-[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:25: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:25: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:25: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:25: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:25: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:26: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:26: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:26: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:26: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:26: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:27: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:27: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:27: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:27: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:28: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:28: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:28: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:28: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:28: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:30: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:30: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:30: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:30: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:30: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:31: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:31: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:31: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:31: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:31: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:32: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:32: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:32: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:32: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:32: *Info: macro .*
+[^:]*:5: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:33: *Info: macro .*
+[^:]*:6: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:33: *Info: macro .*
+[^:]*:7: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:33: *Info: macro .*
+[^:]*:8: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:33: *Info: macro .*
+[^:]*:10: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]'
+[^:]*:33: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:37: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:37: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:37: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:37: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:37: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:38: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:38: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:38: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:38: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:38: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:39: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:39: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:39: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:39: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:39: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:40: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:40: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:40: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:40: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:40: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:41: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:41: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:41: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:41: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:41: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:42: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:42: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:42: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:42: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:42: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:43: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:43: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:43: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:43: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:43: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:44: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:44: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:44: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:44: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]'
+[^:]*:44: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:48: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:48: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:48: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:48: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]'
+[^:]*:48: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:49: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:49: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:49: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:49: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]'
+[^:]*:49: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:51: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:51: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:51: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:51: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:51: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:52: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:52: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:52: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:52: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:52: *Info: macro .*
[^:]*:54: Error: too many positional arguments
-[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]'
-[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]'
-[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]'
-[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]'
-[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]'
-[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]'
-[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
-[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
-[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
-[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
-[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:55: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:55: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:55: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:55: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]'
+[^:]*:55: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:59: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:59: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:59: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:59: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]'
+[^:]*:59: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:60: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:60: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:60: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:60: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]'
+[^:]*:60: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:61: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:61: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:61: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:61: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]'
+[^:]*:61: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:62: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:62: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:62: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:62: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]'
+[^:]*:62: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:63: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:63: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:63: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:63: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:63: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:64: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:64: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:64: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:64: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:64: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:65: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:65: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:65: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:65: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:65: *Info: macro .*
+[^:]*:16: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
+[^:]*:66: *Info: macro .*
+[^:]*:17: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
+[^:]*:66: *Info: macro .*
+[^:]*:18: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
+[^:]*:66: *Info: macro .*
+[^:]*:19: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
+[^:]*:66: *Info: macro .*
+[^:]*:21: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]'
+[^:]*:66: *Info: macro .*
[^:]*:18: Error: selected FPU does not support instruction -- `vabs.f16 q0,q1'
[^:]*:19: Error: selected FPU does not support instruction -- `vabs.f32 q0,q1'
[^:]*:20: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
[^:]*:22: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
[^:]*:23: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
[^:]*:27: Error: selected FPU does not support instruction -- `vneg.f16 q0,q1'
[^:]*:28: Error: selected FPU does not support instruction -- `vneg.f32 q0,q1'
[^:]*:29: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
[^:]*:32: Error: syntax error -- `vnegeq.s32 q0,q1'
[^:]*:33: Error: syntax error -- `vnegeq.s32 q0,q1'
[^:]*:35: Error: instruction missing MVE vector predication code -- `vneg.s32 q0,q1'
[^:]*:16: Error: bad type in SIMD instruction -- `vabs.u16 q0,q1'
[^:]*:17: Error: bad type in SIMD instruction -- `vabs.u32 q0,q1'
[^:]*:18: Error: bad type in SIMD instruction -- `vabs.s64 q0,q1'
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:19: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: *Info: macro .*
[^:]*:20: Error: bad type in SIMD instruction -- `vneg.p8 q0,q1'
[^:]*:21: Error: bad type in SIMD instruction -- `vneg.p16 q0,q1'
[^:]*:22: Error: bad type in SIMD instruction -- `vneg.u8 q0,q1'
[^:]*:23: Error: bad type in SIMD instruction -- `vneg.u16 q0,q1'
[^:]*:24: Error: bad type in SIMD instruction -- `vneg.u32 q0,q1'
[^:]*:25: Error: bad type in SIMD instruction -- `vneg.s64 q0,q1'
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
[^:]*:28: Error: syntax error -- `vnegeq.f32 q0,q1'
[^:]*:29: Error: syntax error -- `vnegeq.f32 q0,q1'
[^:]*:31: Error: instruction missing MVE vector predication code -- `vneg.f32 q0,q1'
[^:]*:12: Error: selected FPU does not support instruction -- `vadd.f16 q0,q1,q2'
[^:]*:13: Error: selected FPU does not support instruction -- `vadd.f32 q0,q1,q2'
[^:]*:14: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,q2'
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
[^:]*:16: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,q2'
[^:]*:17: Error: selected FPU does not support instruction -- `vsub.f16 q0,q1,q2'
[^:]*:18: Error: selected FPU does not support instruction -- `vsub.f32 q0,q1,q2'
[^:]*:19: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,q2'
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
[^:]*:21: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,r2'
[^:]*:22: Error: selected FPU does not support instruction -- `vadd.f16 q0,q1,r2'
[^:]*:23: Error: selected FPU does not support instruction -- `vadd.f32 q0,q1,r2'
[^:]*:24: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,r2'
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
[^:]*:26: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,r2'
[^:]*:27: Error: selected FPU does not support instruction -- `vsub.f16 q0,q1,r2'
[^:]*:28: Error: selected FPU does not support instruction -- `vsub.f32 q0,q1,r2'
[^:]*:29: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,r2'
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:30: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:30: *Info: macro .*
[^:]*:31: Error: bad type in SIMD instruction -- `vabd.p8 q0,q1,q2'
[^:]*:32: Error: selected FPU does not support instruction -- `vabd.f16 q0,q1,q2'
[^:]*:33: Error: selected FPU does not support instruction -- `vabd.f32 q0,q1,q2'
[^:]*:34: Error: bad type in SIMD instruction -- `vabd.i64 q0,q1,q2'
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:35: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: *Info: macro .*
[^:]*:36: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:37: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:38: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*: Assembler messages:
[^:]*:13: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,q2'
[^:]*:14: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,q2'
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: *Info: macro .*
[^:]*:16: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,q2'
[^:]*:17: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,q2'
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
[^:]*:19: Error: bad type in SIMD instruction -- `vadd.p8 q0,q1,r2'
[^:]*:20: Error: selected FPU does not support instruction -- `vadd.i64 q0,q1,r2'
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
[^:]*:22: Error: bad type in SIMD instruction -- `vsub.p8 q0,q1,r2'
[^:]*:23: Error: selected FPU does not support instruction -- `vsub.i64 q0,q1,r2'
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
[^:]*:25: Error: bad type in SIMD instruction -- `vabd.p8 q0,q1,q2'
[^:]*:26: Error: bad type in SIMD instruction -- `vabd.i64 q0,q1,q2'
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
[^:]*:28: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:29: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:30: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:22: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:23: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:24: Error: garbage following instruction -- `vrhadd.s8 q0,q1,r2'
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:26: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:27: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:29: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:26: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:27: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: *Info: macro .*
[^:]*:31: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
[^:]*:32: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
[^:]*:34: Error: syntax error -- `vhaddeq.s8 q0,q1,r2'
[^:]*:17: Error: bad element type for instruction -- `vldrb.s64 q0,\[r0,q1\]'
[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:19: Error: destination register and offset register may not be the same -- `vldrb.u32 q0,\[r0,q0\]'
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
[^:]*:22: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
[^:]*:23: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
[^:]*:25: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
[^:]*:34: Error: bad element type for instruction -- `vldrh.s64 q0,\[r0,q1\]'
[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:36: Error: destination register and offset register may not be the same -- `vldrh.u32 q0,\[r0,q0\]'
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
[^:]*:39: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
[^:]*:40: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
[^:]*:42: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
[^:]*:49: Error: bad element type for instruction -- `vldrw.s64 q0,\[r0,q1\]'
[^:]*:50: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:51: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[r0,q0\]'
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: *Info: macro .*
[^:]*:54: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
[^:]*:55: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
[^:]*:57: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
[^:]*:79: Error: bad element type for instruction -- `vldrd.u32 q0,\[r0,q1\]'
[^:]*:80: Error: bad element type for instruction -- `vldrd.s32 q0,\[r0,q1\]'
[^:]*:81: Error: bad element type for instruction -- `vldrd.f32 q0,\[r0,q1\]'
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
+[^:]*:65: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: *Info: macro .*
[^:]*:84: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
[^:]*:85: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
[^:]*:87: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
[^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#516\]'
[^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#-516\]'
[^:]*:17: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[q0,#4\]'
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: *Info: macro .*
[^:]*:20: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
[^:]*:21: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
[^:]*:23: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
[^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1024\]'
[^:]*:34: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#-1024\]'
[^:]*:35: Error: destination register and offset register may not be the same -- `vldrd.u64 q0,\[q0,#8\]'
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
[^:]*:38: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
[^:]*:39: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
[^:]*:41: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
[^:]*:35: Error: bad element type for instruction -- `vldrb.16 q0,\[r0\]'
[^:]*:36: Error: bad element type for instruction -- `vldrb.f16 q0,\[r0\]'
[^:]*:37: Error: bad element type for instruction -- `vldrb.p16 q0,\[r0\]'
[^:]*:71: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:72: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:73: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: *Info: macro .*
[^:]*:75: Error: bad element type for instruction -- `vldrh.8 q0,\[r0\]'
[^:]*:76: Error: bad element type for instruction -- `vldrh.u8 q0,\[r0\]'
[^:]*:77: Error: bad element type for instruction -- `vldrh.s8 q0,\[r0\]'
[^:]*:101: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#-516'
[^:]*:102: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:103: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: *Info: macro .*
[^:]*:105: Error: bad element type for instruction -- `vldrw.8 q0,\[r0\]'
[^:]*:106: Error: bad element type for instruction -- `vldrw.u8 q0,\[r0\]'
[^:]*:107: Error: bad element type for instruction -- `vldrw.s8 q0,\[r0\]'
[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:21: Warning: instruction is UNPREDICTABLE with SP operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
[^:]*:27: Error: syntax error -- `vmuleq.f16 q0,q1,q2'
[^:]*:28: Error: syntax error -- `vmuleq.f16 q0,q1,q2'
[^:]*:30: Error: syntax error -- `vmuleq.f16 q0,q1,q2'
[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
[^:]*:27: Error: syntax error -- `vqaddeq.s32 q0,q1,q2'
[^:]*:28: Error: syntax error -- `vqaddeq.s32 q0,q1,q2'
[^:]*:30: Error: syntax error -- `vqaddeq.s32 q0,q1,q2'
[^:]*:19: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:20: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:24: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:25: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:24: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: *Info: macro .*
[^:]*:27: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
[^:]*:28: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
[^:]*:30: Error: syntax error -- `vqdmulheq.s8 q0,q1,q2'
[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:34: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:38: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:39: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: *Info: macro .*
[^:]*:41: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
[^:]*:42: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
[^:]*:44: Error: syntax error -- `vqdmullteq.s32 q0,q1,q2'
[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:19: Error: bad type in SIMD instruction -- `vqshl.s64 q0,q1,q2'
[^:]*:20: Error: bad type in SIMD instruction -- `vqshl.i32 q0,q1,q2'
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:23: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:23: *Info: macro .*
[^:]*:25: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:26: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:28: Error: syntax error -- `vqshleq.s16 q0,q1,#0'
[^:]*:17: Warning: instruction is UNPREDICTABLE with PC operand
[^:]*:18: Error: bad type in SIMD instruction -- `vshl.s64 q0,q1,q2'
[^:]*:19: Error: bad type in SIMD instruction -- `vshl.i32 q0,q1,q2'
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:21: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:21: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
[^:]*:24: Error: syntax error -- `vshleq.i16 q0,q1,#0'
[^:]*:25: Error: syntax error -- `vshleq.i16 q0,q1,#0'
[^:]*:27: Error: syntax error -- `vshleq.i16 q0,q1,#0'
[^:]*:140: Error: selected processor does not support `vld4.8 {q0,q1},\[r0\]' in Thumb mode
[^:]*:141: Error: bad instruction `vld23.32 {q0,q1},\[r0\]'
[^:]*:142: Error: bad instruction `vld44.32 {q0,q1,q2,q3},\[r0\]'
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:160: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:161: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:162: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:163: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:164: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:165: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:160: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:161: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:162: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:163: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:164: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:165: *Info: macro .*
[^:]*:167: Error: syntax error -- `vst20t.32 {q0,q1},\[r0\]'
[^:]*:168: Error: syntax error -- `vst20e.32 {q0,q1},\[r0\]'
[^:]*:170: Error: syntax error -- `vst21t.32 {q0,q1},\[r0\]'
[^:]*:192: Warning: instruction is UNPREDICTABLE in a VPT block
[^:]*:194: Warning: instruction is UNPREDICTABLE in a VPT block
[^:]*:196: Warning: instruction is UNPREDICTABLE in a VPT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:198: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:199: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:200: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:201: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:202: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:203: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:198: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:147: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:199: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:200: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:201: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:202: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
+[^:]*:156: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:203: *Info: macro .*
[^:]*:205: Error: syntax error -- `vld20t.32 {q0,q1},\[r0\]'
[^:]*:206: Error: syntax error -- `vld20e.32 {q0,q1},\[r0\]'
[^:]*:208: Error: syntax error -- `vld21t.32 {q0,q1},\[r0\]'
[^:]*:19: Error: bad element type for instruction -- `vstrb.f32 q0,\[r0,q1\]'
[^:]*:20: Error: bad element type for instruction -- `vstrb.64 q0,\[r0,q1\]'
[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: *Info: macro .*
[^:]*:25: Error: bad element type for instruction -- `vstrh.8 q0,\[r0,q1\]'
[^:]*:26: Error: bad element type for instruction -- `vstrh.s8 q0,\[r0,q1\]'
[^:]*:27: Error: bad element type for instruction -- `vstrh.u8 q0,\[r0,q1\]'
[^:]*:33: Error: bad element type for instruction -- `vstrh.f32 q0,\[r0,q1\]'
[^:]*:34: Error: bad element type for instruction -- `vstrh.64 q0,\[r0,q1\]'
[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: *Info: macro .*
[^:]*:39: Error: shift expression expected -- `vstrh.16 q0,\[r0,q1,#1\]'
[^:]*:40: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrh.16 q0,\[r0,q1,UXTW#2\]'
[^:]*:41: Error: bad element type for instruction -- `vstrw.8 q0,\[r0,q1\]'
[^:]*:50: Error: bad element type for instruction -- `vstrw.f32 q0,\[r0,q1\]'
[^:]*:51: Error: bad element type for instruction -- `vstrw.64 q0,\[r0,q1\]'
[^:]*:52: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: *Info: macro .*
[^:]*:56: Error: shift expression expected -- `vstrw.32 q0,\[r0,q1,#2\]'
[^:]*:57: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#1\]'
[^:]*:58: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#3\]'
[^:]*:70: Error: bad element type for instruction -- `vstrd.f64 q0,\[r0,q1\]'
[^:]*:71: Error: bad element type for instruction -- `vstrd.u64 q0,\[r0,q1\]'
[^:]*:72: Error: bad element type for instruction -- `vstrd.s64 q0,\[r0,q1\]'
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
+[^:]*:77: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: *Info: macro .*
[^:]*:84: Error: shift expression expected -- `vstrd.64 q0,\[r0,q1,#3\]'
[^:]*:85: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#1\]'
[^:]*:86: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#2\]'
[^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#231\]'
[^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#516\]'
[^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#-516\]'
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: *Info: macro .*
[^:]*:19: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
[^:]*:20: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
[^:]*:22: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
[^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#228\]'
[^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#1024\]'
[^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#-1024\]'
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
[^:]*:36: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
[^:]*:37: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
[^:]*:39: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: *Info: macro .*
[^:]*:35: Error: bad element type for instruction -- `vstrb.u16 q0,\[r0\]'
[^:]*:36: Error: bad element type for instruction -- `vstrb.s16 q0,\[r0\]'
[^:]*:37: Error: bad element type for instruction -- `vstrb.f16 q0,\[r0\]'
[^:]*:73: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:74: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:75: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: *Info: macro .*
[^:]*:77: Error: bad element type for instruction -- `vstrh.8 q0,\[r0\]'
[^:]*:78: Error: bad element type for instruction -- `vstrh.u8 q0,\[r0\]'
[^:]*:79: Error: bad element type for instruction -- `vstrh.s8 q0,\[r0\]'
[^:]*:104: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#-516'
[^:]*:105: Warning: instruction is UNPREDICTABLE with SP operand
[^:]*:106: Warning: instruction is UNPREDICTABLE with PC operand
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
-[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
+[^:]*:4: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: *Info: macro .*
[^:]*:108: Error: bad element type for instruction -- `vstrw.8 q0,\[r0\]'
[^:]*:109: Error: bad element type for instruction -- `vstrw.u8 q0,\[r0\]'
[^:]*:110: Error: bad element type for instruction -- `vstrw.s8 q0,\[r0\]'
[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1'
[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0'
[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0'
-[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
-[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2'
-[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
-[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2'
-[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
-[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2'
-[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
-[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'
-[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
-[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2'
+[^:]*:23: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'
+[^:]*:27: *Info: macro .*
+[^:]*:24: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2'
+[^:]*:27: *Info: macro .*
+[^:]*:23: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'
+[^:]*:28: *Info: macro .*
+[^:]*:24: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2'
+[^:]*:28: *Info: macro .*
+[^:]*:23: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'
+[^:]*:29: *Info: macro .*
+[^:]*:24: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2'
+[^:]*:29: *Info: macro .*
+[^:]*:23: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'
+[^:]*:30: *Info: macro .*
+[^:]*:24: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'
+[^:]*:30: *Info: macro .*
+[^:]*:23: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'
+[^:]*:31: *Info: macro .*
+[^:]*:24: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2'
+[^:]*:31: *Info: macro .*
[^:]*:34: Error: instruction cannot be conditional -- `vcvteq\.f16\.f32 d1,q1'
[^:]*:35: Error: instruction cannot be conditional -- `vcvteq\.f32\.f16 q1,d1'
-[^:]*:43: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
-[^:]*:43: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'
-[^:]*:44: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
-[^:]*:44: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'
-[^:]*:52: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
-[^:]*:52: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'
-[^:]*:53: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
-[^:]*:53: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'
-[^:]*:54: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
-[^:]*:54: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'
-[^:]*:55: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'
-[^:]*:55: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'
+[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'
+[^:]*:43: *Info: macro .*
+[^:]*:40: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'
+[^:]*:43: *Info: macro .*
+[^:]*:39: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'
+[^:]*:44: *Info: macro .*
+[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'
+[^:]*:44: *Info: macro .*
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'
+[^:]*:52: *Info: macro .*
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'
+[^:]*:52: *Info: macro .*
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'
+[^:]*:53: *Info: macro .*
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'
+[^:]*:53: *Info: macro .*
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'
+[^:]*:54: *Info: macro .*
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'
+[^:]*:54: *Info: macro .*
+[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'
+[^:]*:55: *Info: macro .*
+[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'
+[^:]*:55: *Info: macro .*
[^:]*:60: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]'
[^:]*:61: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]'
.*shift-bad-pc.s: Assembler messages:
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:20: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
-.*shift-bad-pc.s:21: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:5: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:6: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:7: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:8: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:20: *Info: macro .*
+.*shift-bad-pc.s:14: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:15: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:16: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:14: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:15: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:16: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:14: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:15: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:16: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:14: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:15: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:16: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:14: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:15: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
+.*shift-bad-pc.s:16: Warning: using r15 results in unpredictable behaviour
+.*shift-bad-pc.s:21: *Info: macro .*
[^:]*: Assembler messages:
-[^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 d3,d12,d7\[2\]'
-[^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.i32 q3,q12,d7\[2\]'
-[^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.f32 d3,d12,d7\[2\]'
-[^:]*:21: Error: scalar out of range for multiply instruction -- `vmul.f32 q3,q12,d7\[2\]'
-[^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.i16 d4,d9,d8\[1\]'
-[^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.i16 q4,q9,d8\[1\]'
-[^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.f16 d4,d9,d8\[1\]'
-[^:]*:22: Error: scalar out of range for multiply instruction -- `vmul.f16 q4,q9,d8\[1\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i16 d13,d6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i16 q13,q6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.f16 d13,d6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.f16 q13,q6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i32 d13,d6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.i32 q13,q6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.f32 d13,d6,d15\[3\]'
-[^:]*:23: Error: scalar out of range for multiply instruction -- `vmul.f32 q13,q6,d15\[3\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.i32 d5,d4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.i32 q5,q4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.f32 d5,d4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmla.f32 q5,q4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.i32 d5,d4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.i32 q5,q4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.f32 d5,d4,d6\[2\]'
-[^:]*:25: Error: scalar out of range for multiply instruction -- `vmls.f32 q5,q4,d6\[2\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmla.i16 d4,d13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmla.i16 q4,q13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmla.f16 d4,d13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmla.f16 q4,q13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmls.i16 d4,d13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmls.i16 q4,q13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmls.f16 d4,d13,d10\[1\]'
-[^:]*:26: Error: scalar out of range for multiply instruction -- `vmls.f16 q4,q13,d10\[1\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i16 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i16 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i32 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.i32 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.f16 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.f16 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.f32 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmla.f32 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.i16 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.i16 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.i32 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.i32 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.f16 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.f16 q12,q6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.f32 d12,d6,d13\[3\]'
-[^:]*:27: Error: scalar out of range for multiply instruction -- `vmls.f32 q12,q6,d13\[3\]'
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.i32 d3,d12,d7\[2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.i32 q3,q12,d7\[2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.f32 d3,d12,d7\[2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.f32 q3,q12,d7\[2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.i16 d4,d9,d8\[1\]'
+[^:]*:22: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.i16 q4,q9,d8\[1\]'
+[^:]*:22: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.f16 d4,d9,d8\[1\]'
+[^:]*:22: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.f16 q4,q9,d8\[1\]'
+[^:]*:22: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.i16 d13,d6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.i16 q13,q6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.f16 d13,d6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.f16 q13,q6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.i32 d13,d6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.i32 q13,q6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:3: Error: scalar out of range for multiply instruction -- `vmul.f32 d13,d6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:4: Error: scalar out of range for multiply instruction -- `vmul.f32 q13,q6,d15\[3\]'
+[^:]*:23: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.i32 d5,d4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.i32 q5,q4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.f32 d5,d4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.f32 q5,q4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.i32 d5,d4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.i32 q5,q4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.f32 d5,d4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.f32 q5,q4,d6\[2\]'
+[^:]*:25: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.i16 d4,d13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.i16 q4,q13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.f16 d4,d13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.f16 q4,q13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.i16 d4,d13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.i16 q4,q13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.f16 d4,d13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.f16 q4,q13,d10\[1\]'
+[^:]*:26: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.i16 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.i16 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.i32 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.i32 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.f16 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.f16 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmla.f32 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmla.f32 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.i16 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.i16 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.i32 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.i32 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.f16 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.f16 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:10: Error: scalar out of range for multiply instruction -- `vmls.f32 d12,d6,d13\[3\]'
+[^:]*:27: *Info: macro .*
+[^:]*:11: Error: scalar out of range for multiply instruction -- `vmls.f32 q12,q6,d13\[3\]'
+[^:]*:27: *Info: macro .*
[^:]*: Assembler messages:
-[^:]*:27: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:27: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:27: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\]'
-[^:]*:28: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:28: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:28: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]'
-[^:]*:29: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:29: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:29: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp\]'
-[^:]*:30: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:30: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:30: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp,#0\]'
-[^:]*:31: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:31: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:31: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0\]'
-[^:]*:32: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:32: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:32: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,#0\]'
-[^:]*:33: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:33: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:33: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#-4\]'
-[^:]*:34: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:34: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:34: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\],#4'
-[^:]*:35: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:35: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:35: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]!'
-[^:]*:38: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:38: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:38: Error: branch must be last instruction in IT block -- `ldreq r15,label'
-[^:]*:39: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:39: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:39: Error: branch must be last instruction in IT block -- `ldreq.w r15,label'
-[^:]*:40: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:40: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:40: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[pc,#-0\]'
-[^:]*:43: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:43: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:43: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,r1\]'
-[^:]*:44: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:44: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:44: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]'
-[^:]*:45: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
-[^:]*:45: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
-[^:]*:45: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:27: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:27: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:27: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:28: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:28: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:28: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:29: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:29: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp\]'
+[^:]*:17: *Info: macro .*
+[^:]*:29: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:30: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:30: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp,#0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:30: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:31: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:31: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:31: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:32: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:32: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,#0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:32: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:33: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:33: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#-4\]'
+[^:]*:17: *Info: macro .*
+[^:]*:33: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:34: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:34: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\],#4'
+[^:]*:17: *Info: macro .*
+[^:]*:34: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:35: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:35: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]!'
+[^:]*:17: *Info: macro .*
+[^:]*:35: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,label'
+[^:]*:17: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:39: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:39: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,label'
+[^:]*:21: *Info: macro .*
+[^:]*:39: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:40: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:40: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[pc,#-0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:40: *Info: macro .*
+[^:]*:6: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:17: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:6: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:17: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,r1\]'
+[^:]*:17: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]'
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:12: IT blocks containing 16-bit Thumb instructions of the following class are performance deprecated in ARMv8-A and ARMv8-R: Short branches, Undefined, SVC, LDM/STM
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
+[^:]*:12: IT blocks containing more than one conditional instruction are performance deprecated in ARMv8-A and ARMv8-R
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
[^:]*:48: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]'
[^:]*:51: Error: r15 not allowed here -- `ldrb.w pc,\[r0,#4\]'
[^:]*:52: Error: r15 not allowed here -- `ldrb pc,\[r0,#-4\]'
[^:]*: Assembler messages:
-[^:]*:27: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\]'
-[^:]*:28: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]'
-[^:]*:29: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp\]'
-[^:]*:30: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp,#0\]'
-[^:]*:31: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0\]'
-[^:]*:32: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,#0\]'
-[^:]*:33: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#-4\]'
-[^:]*:34: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\],#4'
-[^:]*:35: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]!'
-[^:]*:38: Error: branch must be last instruction in IT block -- `ldreq r15,label'
-[^:]*:39: Error: branch must be last instruction in IT block -- `ldreq.w r15,label'
-[^:]*:40: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[pc,#-0\]'
-[^:]*:43: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,r1\]'
-[^:]*:44: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]'
-[^:]*:45: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:27: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:28: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp\]'
+[^:]*:17: *Info: macro .*
+[^:]*:29: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp,#0\]'
+[^:]*:17: *Info: macro .*
+[^:]*:30: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:31: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,#0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:32: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#-4\]'
+[^:]*:17: *Info: macro .*
+[^:]*:33: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\],#4'
+[^:]*:17: *Info: macro .*
+[^:]*:34: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]!'
+[^:]*:17: *Info: macro .*
+[^:]*:35: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,label'
+[^:]*:17: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,label'
+[^:]*:21: *Info: macro .*
+[^:]*:39: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[pc,#-0\]'
+[^:]*:21: *Info: macro .*
+[^:]*:40: *Info: macro .*
+[^:]*:6: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,r1\]'
+[^:]*:17: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]'
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:12: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
[^:]*:48: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]'
[^:]*:50: Error: r13 not allowed here -- `ldrb.w sp,\[r0,#4\]'
[^:]*:51: Error: r15 not allowed here -- `ldrb.w pc,\[r0,#4\]'
[^:]*: Assembler messages:
-[^:]*:36: Error: lo register required -- `tst r8,r0'
-[^:]*:36: Error: lo register required -- `tst r0,r8'
-[^:]*:36: Error: unshifted register required -- `tst r0,#12'
-[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl#2'
-[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl r3'
-[^:]*:37: Error: lo register required -- `cmn r8,r0'
-[^:]*:37: Error: lo register required -- `cmn r0,r8'
-[^:]*:37: Error: unshifted register required -- `cmn r0,#12'
-[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl#2'
-[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl r3'
-[^:]*:38: Error: lo register required -- `mvn r8,r0'
-[^:]*:38: Error: lo register required -- `mvn r0,r8'
-[^:]*:38: Error: unshifted register required -- `mvn r0,#12'
-[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl#2'
-[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl r3'
-[^:]*:39: Error: lo register required -- `neg r8,r0'
-[^:]*:39: Error: lo register required -- `neg r0,r8'
-[^:]*:40: Error: lo register required -- `rev r8,r0'
-[^:]*:40: Error: lo register required -- `rev r0,r8'
-[^:]*:41: Error: lo register required -- `rev16 r8,r0'
-[^:]*:41: Error: lo register required -- `rev16 r0,r8'
-[^:]*:42: Error: lo register required -- `revsh r8,r0'
-[^:]*:42: Error: lo register required -- `revsh r0,r8'
-[^:]*:43: Error: lo register required -- `sxtb r8,r0'
-[^:]*:43: Error: lo register required -- `sxtb r0,r8'
-[^:]*:43: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8'
-[^:]*:44: Error: lo register required -- `sxth r8,r0'
-[^:]*:44: Error: lo register required -- `sxth r0,r8'
-[^:]*:44: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8'
-[^:]*:45: Error: lo register required -- `uxtb r8,r0'
-[^:]*:45: Error: lo register required -- `uxtb r0,r8'
-[^:]*:45: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8'
-[^:]*:46: Error: lo register required -- `uxth r8,r0'
-[^:]*:46: Error: lo register required -- `uxth r0,r8'
-[^:]*:46: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8'
-[^:]*:48: Error: dest must overlap one source register -- `adc r1,r2,r3'
-[^:]*:48: Error: lo register required -- `adc r8,r0'
-[^:]*:48: Error: lo register required -- `adc r0,r8'
-[^:]*:48: Error: unshifted register required -- `adc r0,#12'
-[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl#2'
-[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl r3'
-[^:]*:49: Error: dest must overlap one source register -- `and r1,r2,r3'
-[^:]*:49: Error: lo register required -- `and r8,r0'
-[^:]*:49: Error: lo register required -- `and r0,r8'
-[^:]*:49: Error: unshifted register required -- `and r0,#12'
-[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl#2'
-[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl r3'
-[^:]*:50: Error: dest and source1 must be the same register -- `bic r1,r2,r3'
-[^:]*:50: Error: lo register required -- `bic r8,r0'
-[^:]*:50: Error: lo register required -- `bic r0,r8'
-[^:]*:50: Error: unshifted register required -- `bic r0,#12'
-[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl#2'
-[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl r3'
-[^:]*:51: Error: dest must overlap one source register -- `eor r1,r2,r3'
-[^:]*:51: Error: lo register required -- `eor r8,r0'
-[^:]*:51: Error: lo register required -- `eor r0,r8'
-[^:]*:51: Error: unshifted register required -- `eor r0,#12'
-[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl#2'
-[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl r3'
-[^:]*:52: Error: dest must overlap one source register -- `orr r1,r2,r3'
-[^:]*:52: Error: lo register required -- `orr r8,r0'
-[^:]*:52: Error: lo register required -- `orr r0,r8'
-[^:]*:52: Error: unshifted register required -- `orr r0,#12'
-[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl#2'
-[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl r3'
-[^:]*:53: Error: dest and source1 must be the same register -- `sbc r1,r2,r3'
-[^:]*:53: Error: lo register required -- `sbc r8,r0'
-[^:]*:53: Error: lo register required -- `sbc r0,r8'
-[^:]*:53: Error: unshifted register required -- `sbc r0,#12'
-[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl#2'
-[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl r3'
-[^:]*:54: Error: dest must overlap one source register -- `mul r1,r2,r3'
-[^:]*:54: Error: lo register required -- `mul r8,r0'
-[^:]*:54: Error: lo register required -- `mul r0,r8'
-[^:]*:62: Error: lo register required -- `asr r8,r0,#12'
-[^:]*:62: Error: lo register required -- `asr r0,r8,#12'
-[^:]*:62: Error: lo register required -- `asr r8,r0'
-[^:]*:62: Error: lo register required -- `asr r0,r8'
-[^:]*:63: Error: lo register required -- `lsl r8,r0,#12'
-[^:]*:63: Error: lo register required -- `lsl r0,r8,#12'
-[^:]*:63: Error: lo register required -- `lsl r8,r0'
-[^:]*:63: Error: lo register required -- `lsl r0,r8'
-[^:]*:64: Error: lo register required -- `lsr r8,r0,#12'
-[^:]*:64: Error: lo register required -- `lsr r0,r8,#12'
-[^:]*:64: Error: lo register required -- `lsr r8,r0'
-[^:]*:64: Error: lo register required -- `lsr r0,r8'
-[^:]*:65: Error: lo register required -- `ror r8,r0,#12'
-[^:]*:65: Error: lo register required -- `ror r0,r8,#12'
-[^:]*:65: Error: lo register required -- `ror r8,r0'
-[^:]*:65: Error: lo register required -- `ror r0,r8'
+[^:]*:11: Error: lo register required -- `tst r8,r0'
+[^:]*:15: *Info: macro .*
+[^:]*:36: *Info: macro .*
+[^:]*:12: Error: lo register required -- `tst r0,r8'
+[^:]*:15: *Info: macro .*
+[^:]*:36: *Info: macro .*
+[^:]*:16: Error: unshifted register required -- `tst r0,#12'
+[^:]*:36: *Info: macro .*
+[^:]*:17: Error: unshifted register required -- `tst r0,r1,lsl#2'
+[^:]*:36: *Info: macro .*
+[^:]*:18: Error: unshifted register required -- `tst r0,r1,lsl r3'
+[^:]*:36: *Info: macro .*
+[^:]*:11: Error: lo register required -- `cmn r8,r0'
+[^:]*:15: *Info: macro .*
+[^:]*:37: *Info: macro .*
+[^:]*:12: Error: lo register required -- `cmn r0,r8'
+[^:]*:15: *Info: macro .*
+[^:]*:37: *Info: macro .*
+[^:]*:16: Error: unshifted register required -- `cmn r0,#12'
+[^:]*:37: *Info: macro .*
+[^:]*:17: Error: unshifted register required -- `cmn r0,r1,lsl#2'
+[^:]*:37: *Info: macro .*
+[^:]*:18: Error: unshifted register required -- `cmn r0,r1,lsl r3'
+[^:]*:37: *Info: macro .*
+[^:]*:11: Error: lo register required -- `mvn r8,r0'
+[^:]*:15: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:12: Error: lo register required -- `mvn r0,r8'
+[^:]*:15: *Info: macro .*
+[^:]*:38: *Info: macro .*
+[^:]*:16: Error: unshifted register required -- `mvn r0,#12'
+[^:]*:38: *Info: macro .*
+[^:]*:17: Error: unshifted register required -- `mvn r0,r1,lsl#2'
+[^:]*:38: *Info: macro .*
+[^:]*:18: Error: unshifted register required -- `mvn r0,r1,lsl r3'
+[^:]*:38: *Info: macro .*
+[^:]*:11: Error: lo register required -- `neg r8,r0'
+[^:]*:39: *Info: macro .*
+[^:]*:12: Error: lo register required -- `neg r0,r8'
+[^:]*:39: *Info: macro .*
+[^:]*:11: Error: lo register required -- `rev r8,r0'
+[^:]*:40: *Info: macro .*
+[^:]*:12: Error: lo register required -- `rev r0,r8'
+[^:]*:40: *Info: macro .*
+[^:]*:11: Error: lo register required -- `rev16 r8,r0'
+[^:]*:41: *Info: macro .*
+[^:]*:12: Error: lo register required -- `rev16 r0,r8'
+[^:]*:41: *Info: macro .*
+[^:]*:11: Error: lo register required -- `revsh r8,r0'
+[^:]*:42: *Info: macro .*
+[^:]*:12: Error: lo register required -- `revsh r0,r8'
+[^:]*:42: *Info: macro .*
+[^:]*:11: Error: lo register required -- `sxtb r8,r0'
+[^:]*:21: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:12: Error: lo register required -- `sxtb r0,r8'
+[^:]*:21: *Info: macro .*
+[^:]*:43: *Info: macro .*
+[^:]*:22: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8'
+[^:]*:43: *Info: macro .*
+[^:]*:11: Error: lo register required -- `sxth r8,r0'
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:12: Error: lo register required -- `sxth r0,r8'
+[^:]*:21: *Info: macro .*
+[^:]*:44: *Info: macro .*
+[^:]*:22: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8'
+[^:]*:44: *Info: macro .*
+[^:]*:11: Error: lo register required -- `uxtb r8,r0'
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
+[^:]*:12: Error: lo register required -- `uxtb r0,r8'
+[^:]*:21: *Info: macro .*
+[^:]*:45: *Info: macro .*
+[^:]*:22: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8'
+[^:]*:45: *Info: macro .*
+[^:]*:11: Error: lo register required -- `uxth r8,r0'
+[^:]*:21: *Info: macro .*
+[^:]*:46: *Info: macro .*
+[^:]*:12: Error: lo register required -- `uxth r0,r8'
+[^:]*:21: *Info: macro .*
+[^:]*:46: *Info: macro .*
+[^:]*:22: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8'
+[^:]*:46: *Info: macro .*
+[^:]*:25: Error: dest must overlap one source register -- `adc r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:48: *Info: macro .*
+[^:]*:26: Error: lo register required -- `adc r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:48: *Info: macro .*
+[^:]*:27: Error: lo register required -- `adc r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:48: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `adc r0,#12'
+[^:]*:48: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `adc r0,r1,lsl#2'
+[^:]*:48: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `adc r0,r1,lsl r3'
+[^:]*:48: *Info: macro .*
+[^:]*:25: Error: dest must overlap one source register -- `and r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:49: *Info: macro .*
+[^:]*:26: Error: lo register required -- `and r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:49: *Info: macro .*
+[^:]*:27: Error: lo register required -- `and r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:49: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `and r0,#12'
+[^:]*:49: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `and r0,r1,lsl#2'
+[^:]*:49: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `and r0,r1,lsl r3'
+[^:]*:49: *Info: macro .*
+[^:]*:25: Error: dest and source1 must be the same register -- `bic r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:50: *Info: macro .*
+[^:]*:26: Error: lo register required -- `bic r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:50: *Info: macro .*
+[^:]*:27: Error: lo register required -- `bic r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:50: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `bic r0,#12'
+[^:]*:50: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `bic r0,r1,lsl#2'
+[^:]*:50: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `bic r0,r1,lsl r3'
+[^:]*:50: *Info: macro .*
+[^:]*:25: Error: dest must overlap one source register -- `eor r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:51: *Info: macro .*
+[^:]*:26: Error: lo register required -- `eor r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:51: *Info: macro .*
+[^:]*:27: Error: lo register required -- `eor r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:51: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `eor r0,#12'
+[^:]*:51: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `eor r0,r1,lsl#2'
+[^:]*:51: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `eor r0,r1,lsl r3'
+[^:]*:51: *Info: macro .*
+[^:]*:25: Error: dest must overlap one source register -- `orr r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:52: *Info: macro .*
+[^:]*:26: Error: lo register required -- `orr r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:52: *Info: macro .*
+[^:]*:27: Error: lo register required -- `orr r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:52: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `orr r0,#12'
+[^:]*:52: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `orr r0,r1,lsl#2'
+[^:]*:52: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `orr r0,r1,lsl r3'
+[^:]*:52: *Info: macro .*
+[^:]*:25: Error: dest and source1 must be the same register -- `sbc r1,r2,r3'
+[^:]*:30: *Info: macro .*
+[^:]*:53: *Info: macro .*
+[^:]*:26: Error: lo register required -- `sbc r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:53: *Info: macro .*
+[^:]*:27: Error: lo register required -- `sbc r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:53: *Info: macro .*
+[^:]*:31: Error: unshifted register required -- `sbc r0,#12'
+[^:]*:53: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `sbc r0,r1,lsl#2'
+[^:]*:53: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `sbc r0,r1,lsl r3'
+[^:]*:53: *Info: macro .*
+[^:]*:25: Error: dest must overlap one source register -- `mul r1,r2,r3'
+[^:]*:54: *Info: macro .*
+[^:]*:26: Error: lo register required -- `mul r8,r0'
+[^:]*:54: *Info: macro .*
+[^:]*:27: Error: lo register required -- `mul r0,r8'
+[^:]*:54: *Info: macro .*
+[^:]*:58: Error: lo register required -- `asr r8,r0,#12'
+[^:]*:62: *Info: macro .*
+[^:]*:59: Error: lo register required -- `asr r0,r8,#12'
+[^:]*:62: *Info: macro .*
+[^:]*:11: Error: lo register required -- `asr r8,r0'
+[^:]*:60: *Info: macro .*
+[^:]*:62: *Info: macro .*
+[^:]*:12: Error: lo register required -- `asr r0,r8'
+[^:]*:60: *Info: macro .*
+[^:]*:62: *Info: macro .*
+[^:]*:58: Error: lo register required -- `lsl r8,r0,#12'
+[^:]*:63: *Info: macro .*
+[^:]*:59: Error: lo register required -- `lsl r0,r8,#12'
+[^:]*:63: *Info: macro .*
+[^:]*:11: Error: lo register required -- `lsl r8,r0'
+[^:]*:60: *Info: macro .*
+[^:]*:63: *Info: macro .*
+[^:]*:12: Error: lo register required -- `lsl r0,r8'
+[^:]*:60: *Info: macro .*
+[^:]*:63: *Info: macro .*
+[^:]*:58: Error: lo register required -- `lsr r8,r0,#12'
+[^:]*:64: *Info: macro .*
+[^:]*:59: Error: lo register required -- `lsr r0,r8,#12'
+[^:]*:64: *Info: macro .*
+[^:]*:11: Error: lo register required -- `lsr r8,r0'
+[^:]*:60: *Info: macro .*
+[^:]*:64: *Info: macro .*
+[^:]*:12: Error: lo register required -- `lsr r0,r8'
+[^:]*:60: *Info: macro .*
+[^:]*:64: *Info: macro .*
+[^:]*:58: Error: lo register required -- `ror r8,r0,#12'
+[^:]*:65: *Info: macro .*
+[^:]*:59: Error: lo register required -- `ror r0,r8,#12'
+[^:]*:65: *Info: macro .*
+[^:]*:11: Error: lo register required -- `ror r8,r0'
+[^:]*:60: *Info: macro .*
+[^:]*:65: *Info: macro .*
+[^:]*:12: Error: lo register required -- `ror r0,r8'
+[^:]*:60: *Info: macro .*
+[^:]*:65: *Info: macro .*
[^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12'
[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2'
[^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3'
[^:]*:76: Error: dest must overlap one source register -- `add r1,r2,r8'
[^:]*:77: Error: lo register required -- `add r8,pc,#4'
[^:]*:78: Error: lo register required -- `add r8,sp,#4'
-[^:]*:80: Error: lo register required -- `sub r8,r0'
-[^:]*:80: Error: lo register required -- `sub r0,r8'
-[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl#2'
-[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl r3'
+[^:]*:26: Error: lo register required -- `sub r8,r0'
+[^:]*:30: *Info: macro .*
+[^:]*:80: *Info: macro .*
+[^:]*:27: Error: lo register required -- `sub r0,r8'
+[^:]*:30: *Info: macro .*
+[^:]*:80: *Info: macro .*
+[^:]*:32: Error: unshifted register required -- `sub r0,r1,lsl#2'
+[^:]*:80: *Info: macro .*
+[^:]*:33: Error: unshifted register required -- `sub r0,r1,lsl r3'
+[^:]*:80: *Info: macro .*
[^:]*:81: Error: lo register required -- `sub r8,r0,#1'
[^:]*:82: Error: lo register required -- `sub r0,r8,#1'
[^:]*:83: Error: lo register required -- `sub r8,#10'
[^:]*:92: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl#2'
[^:]*:93: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl r3'
[^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255'
-[^:]*:106: Error: lo register required -- `ldr r8,\[r0\]'
-[^:]*:106: Error: lo register required -- `ldr r0,\[r8\]'
-[^:]*:106: Error: lo register required -- `ldr r0,\[r0,r8\]'
-[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!'
-[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4'
-[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]'
-[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2'
-[^:]*:107: Error: lo register required -- `ldrb r8,\[r0\]'
-[^:]*:107: Error: lo register required -- `ldrb r0,\[r8\]'
-[^:]*:107: Error: lo register required -- `ldrb r0,\[r0,r8\]'
-[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!'
-[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4'
-[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]'
-[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2'
-[^:]*:108: Error: lo register required -- `ldrh r8,\[r0\]'
-[^:]*:108: Error: lo register required -- `ldrh r0,\[r8\]'
-[^:]*:108: Error: lo register required -- `ldrh r0,\[r0,r8\]'
-[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!'
-[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4'
-[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]'
-[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2'
-[^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]'
-[^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]'
-[^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]'
-[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!'
-[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4'
-[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]'
-[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2'
-[^:]*:110: Error: lo register required -- `ldrsh r8,\[r0\]'
-[^:]*:110: Error: lo register required -- `ldrsh r0,\[r8\]'
-[^:]*:110: Error: lo register required -- `ldrsh r0,\[r0,r8\]'
-[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!'
-[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4'
-[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]'
-[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2'
-[^:]*:111: Error: lo register required -- `str r8,\[r0\]'
-[^:]*:111: Error: lo register required -- `str r0,\[r8\]'
-[^:]*:111: Error: lo register required -- `str r0,\[r0,r8\]'
-[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!'
-[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4'
-[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]'
-[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2'
-[^:]*:112: Error: lo register required -- `strb r8,\[r0\]'
-[^:]*:112: Error: lo register required -- `strb r0,\[r8\]'
-[^:]*:112: Error: lo register required -- `strb r0,\[r0,r8\]'
-[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!'
-[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4'
-[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]'
-[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2'
-[^:]*:113: Error: lo register required -- `strh r8,\[r0\]'
-[^:]*:113: Error: lo register required -- `strh r0,\[r8\]'
-[^:]*:113: Error: lo register required -- `strh r0,\[r0,r8\]'
-[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!'
-[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4'
-[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]'
-[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2'
+[^:]*:98: Error: lo register required -- `ldr r8,\[r0\]'
+[^:]*:106: *Info: macro .*
+[^:]*:99: Error: lo register required -- `ldr r0,\[r8\]'
+[^:]*:106: *Info: macro .*
+[^:]*:100: Error: lo register required -- `ldr r0,\[r0,r8\]'
+[^:]*:106: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!'
+[^:]*:106: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4'
+[^:]*:106: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]'
+[^:]*:106: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2'
+[^:]*:106: *Info: macro .*
+[^:]*:98: Error: lo register required -- `ldrb r8,\[r0\]'
+[^:]*:107: *Info: macro .*
+[^:]*:99: Error: lo register required -- `ldrb r0,\[r8\]'
+[^:]*:107: *Info: macro .*
+[^:]*:100: Error: lo register required -- `ldrb r0,\[r0,r8\]'
+[^:]*:107: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!'
+[^:]*:107: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4'
+[^:]*:107: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]'
+[^:]*:107: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2'
+[^:]*:107: *Info: macro .*
+[^:]*:98: Error: lo register required -- `ldrh r8,\[r0\]'
+[^:]*:108: *Info: macro .*
+[^:]*:99: Error: lo register required -- `ldrh r0,\[r8\]'
+[^:]*:108: *Info: macro .*
+[^:]*:100: Error: lo register required -- `ldrh r0,\[r0,r8\]'
+[^:]*:108: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!'
+[^:]*:108: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4'
+[^:]*:108: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]'
+[^:]*:108: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2'
+[^:]*:108: *Info: macro .*
+[^:]*:98: Error: lo register required -- `ldrsb r8,\[r0\]'
+[^:]*:109: *Info: macro .*
+[^:]*:99: Error: lo register required -- `ldrsb r0,\[r8\]'
+[^:]*:109: *Info: macro .*
+[^:]*:100: Error: lo register required -- `ldrsb r0,\[r0,r8\]'
+[^:]*:109: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!'
+[^:]*:109: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4'
+[^:]*:109: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]'
+[^:]*:109: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2'
+[^:]*:109: *Info: macro .*
+[^:]*:98: Error: lo register required -- `ldrsh r8,\[r0\]'
+[^:]*:110: *Info: macro .*
+[^:]*:99: Error: lo register required -- `ldrsh r0,\[r8\]'
+[^:]*:110: *Info: macro .*
+[^:]*:100: Error: lo register required -- `ldrsh r0,\[r0,r8\]'
+[^:]*:110: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!'
+[^:]*:110: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4'
+[^:]*:110: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]'
+[^:]*:110: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2'
+[^:]*:110: *Info: macro .*
+[^:]*:98: Error: lo register required -- `str r8,\[r0\]'
+[^:]*:111: *Info: macro .*
+[^:]*:99: Error: lo register required -- `str r0,\[r8\]'
+[^:]*:111: *Info: macro .*
+[^:]*:100: Error: lo register required -- `str r0,\[r0,r8\]'
+[^:]*:111: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!'
+[^:]*:111: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4'
+[^:]*:111: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]'
+[^:]*:111: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2'
+[^:]*:111: *Info: macro .*
+[^:]*:98: Error: lo register required -- `strb r8,\[r0\]'
+[^:]*:112: *Info: macro .*
+[^:]*:99: Error: lo register required -- `strb r0,\[r8\]'
+[^:]*:112: *Info: macro .*
+[^:]*:100: Error: lo register required -- `strb r0,\[r0,r8\]'
+[^:]*:112: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!'
+[^:]*:112: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4'
+[^:]*:112: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]'
+[^:]*:112: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2'
+[^:]*:112: *Info: macro .*
+[^:]*:98: Error: lo register required -- `strh r8,\[r0\]'
+[^:]*:113: *Info: macro .*
+[^:]*:99: Error: lo register required -- `strh r0,\[r8\]'
+[^:]*:113: *Info: macro .*
+[^:]*:100: Error: lo register required -- `strh r0,\[r0,r8\]'
+[^:]*:113: *Info: macro .*
+[^:]*:101: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!'
+[^:]*:113: *Info: macro .*
+[^:]*:102: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4'
+[^:]*:113: *Info: macro .*
+[^:]*:103: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]'
+[^:]*:113: *Info: macro .*
+[^:]*:104: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2'
+[^:]*:113: *Info: macro .*
[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]'
[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]'
[^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}'
-[^;]*: Assembler messages:
-[^;]*:450: s suffix on comparison instruction is deprecated
-[^;]*:450: s suffix on comparison instruction is deprecated
-[^;]*:450: s suffix on comparison instruction is deprecated
-[^;]*:450: s suffix on comparison instruction is deprecated
-[^;]*:451: s suffix on comparison instruction is deprecated
-[^;]*:451: s suffix on comparison instruction is deprecated
-[^;]*:451: s suffix on comparison instruction is deprecated
-[^;]*:451: s suffix on comparison instruction is deprecated
-[^;]*:452: s suffix on comparison instruction is deprecated
-[^;]*:452: s suffix on comparison instruction is deprecated
-[^;]*:452: s suffix on comparison instruction is deprecated
-[^;]*:452: s suffix on comparison instruction is deprecated
-[^;]*:453: s suffix on comparison instruction is deprecated
-[^;]*:453: s suffix on comparison instruction is deprecated
-[^;]*:453: s suffix on comparison instruction is deprecated
-[^;]*:453: s suffix on comparison instruction is deprecated
+[^:]*: Assembler messages:
+[^:]*:438: s suffix on comparison instruction is deprecated
+[^:]*:450: *Info: macro .*
+[^:]*:440: s suffix on comparison instruction is deprecated
+[^:]*:450: *Info: macro .*
+[^:]*:444: s suffix on comparison instruction is deprecated
+[^:]*:450: *Info: macro .*
+[^:]*:445: s suffix on comparison instruction is deprecated
+[^:]*:450: *Info: macro .*
+[^:]*:438: s suffix on comparison instruction is deprecated
+[^:]*:451: *Info: macro .*
+[^:]*:440: s suffix on comparison instruction is deprecated
+[^:]*:451: *Info: macro .*
+[^:]*:444: s suffix on comparison instruction is deprecated
+[^:]*:451: *Info: macro .*
+[^:]*:445: s suffix on comparison instruction is deprecated
+[^:]*:451: *Info: macro .*
+[^:]*:438: s suffix on comparison instruction is deprecated
+[^:]*:452: *Info: macro .*
+[^:]*:440: s suffix on comparison instruction is deprecated
+[^:]*:452: *Info: macro .*
+[^:]*:444: s suffix on comparison instruction is deprecated
+[^:]*:452: *Info: macro .*
+[^:]*:445: s suffix on comparison instruction is deprecated
+[^:]*:452: *Info: macro .*
+[^:]*:438: s suffix on comparison instruction is deprecated
+[^:]*:453: *Info: macro .*
+[^:]*:440: s suffix on comparison instruction is deprecated
+[^:]*:453: *Info: macro .*
+[^:]*:444: s suffix on comparison instruction is deprecated
+[^:]*:453: *Info: macro .*
+[^:]*:445: s suffix on comparison instruction is deprecated
+[^:]*:453: *Info: macro .*
.*bss\.s: Assembler messages:
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store float in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to fill section .\.bss. with non-zero value
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store float in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to fill section .\.bss\.local. with non-zero value
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.bss\.local.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store float in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-empty string in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to fill section .\.private. with non-zero value
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store non-zero value in section .\.private.
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: zero assumed.*
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store float in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to fill absolute section with non-zero value
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Warning: ignoring fill value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*bss\.s:[1-9][0-9]*: Error: attempt to store value in absolute section
+.*bss\.s:[1-9][0-9]*: Info: .*
.*: Assembler messages:
line\.s:[0-9]*18: Warning: \.warning .*
-line\.s:[0-9]*21: Warning: m1/1: 123
-line\.s:[0-9]*21: Warning: m1/2: 123
-line\.s:[0-9]*22: Warning: m1/1: abc
-line\.s:[0-9]*22: Warning: m1/2: abc
-line\.s:[0-9]*23: Warning: m1/1: XYZ
-line\.s:[0-9]*23: Warning: m1/2: XYZ
+line\.s:2: Warning: m1/1: 123
+line\.s:[0-9]*21: Info: .*
+line\.s:4: Warning: m1/2: 123
+line\.s:[0-9]*21: Info: .*
+line\.s:2: Warning: m1/1: abc
+line\.s:[0-9]*22: Info: .*
+line\.s:4: Warning: m1/2: abc
+line\.s:[0-9]*22: Info: .*
+line\.s:2: Warning: m1/1: XYZ
+line\.s:[0-9]*23: Info: .*
+line\.s:4: Warning: m1/2: XYZ
+line\.s:[0-9]*23: Info: .*
line\.s:[0-9]*24: Warning: \.warning .*
Line\.s:10: Warning: m2/1: 987
+line\.s:[0-9]*26: Info: .*
Line\.s:12: Warning: m2/2: 987
+line\.s:[0-9]*26: Info: .*
Line\.s:10: Warning: m2/1: zyx
+line\.s:[0-9]*27: Info: .*
Line\.s:12: Warning: m2/2: zyx
+line\.s:[0-9]*27: Info: .*
Line\.s:10: Warning: m2/1: CBA
+line\.s:[0-9]*28: Info: .*
Line\.s:12: Warning: m2/2: CBA
+line\.s:[0-9]*28: Info: .*
line\.s:[0-9]*29: Warning: \.warning .*
line\.s:[0-9]*35: Warning: irp/1: 123
line\.s:[0-9]*37: Warning: irp/2: 123
.*: Assembler messages:
-.*:33: Error: .*
-.*:34: Error: .*
-.*:37: Error: .*
-.*:39: Error: .*
-.*:40: Error: .*
-.*:41: Error: .*
-.*:42: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:47: Error: .*
-.*:50: Error: .*
-.*:51: Error: .*
-.*:69: Error: .*
-.*:72: Error: .*
-.*:73: Error: .*
-.*:77: Error: .*
-.*:79: Error: .*
-.*:82: Error: .*
-.*:83: Error: .*
-.*:88: Error: .*
-.*:91: Error: .*
-.*:92: Error: .*
-.*:97: Error: .*
-.*:100: Error: .*
-.*:101: Error: .*
-.*:108: Error: .*
-.*:109: Error: .*
-.*:112: Error: .*
-.*:116: Error: .*
-.*:117: Error: .*
-.*:120: Error: .*
-.*:126: Error: .*
-.*:140: Error: .*
-.*:153: Error: .*
-.*:154: Error: .*
-.*:155: Error: .*
-.*:158: Error: .*
-.*:159: Error: .*
-.*:160: Error: .*
-.*:161: Error: .*
-.*:162: Error: .*
-.*:163: Error: .*
-.*:167: Error: .*
-.*:168: Error: .*
-.*:169: Error: .*
-.*:172: Error: .*
-.*:173: Error: .*
-.*:174: Error: .*
-.*:175: Error: .*
-.*:176: Error: .*
-.*:177: Error: .*
-.*:190: Error: .*
+.*:3: Error: .*
+.*:33: Info: .*
+.*:3: Error: .*
+.*:34: Info: .*
+.*:3: Error: .*
+.*:37: Info: .*
+.*:3: Error: .*
+.*:39: Info: .*
+.*:3: Error: .*
+.*:40: Info: .*
+.*:3: Error: .*
+.*:41: Info: .*
+.*:3: Error: .*
+.*:42: Info: .*
+.*:3: Error: .*
+.*:43: Info: .*
+.*:3: Error: .*
+.*:44: Info: .*
+.*:3: Error: .*
+.*:45: Info: .*
+.*:3: Error: .*
+.*:47: Info: .*
+.*:3: Error: .*
+.*:50: Info: .*
+.*:3: Error: .*
+.*:51: Info: .*
+.*:3: Error: .*
+.*:69: Info: .*
+.*:3: Error: .*
+.*:72: Info: .*
+.*:3: Error: .*
+.*:73: Info: .*
+.*:3: Error: .*
+.*:77: Info: .*
+.*:3: Error: .*
+.*:79: Info: .*
+.*:3: Error: .*
+.*:82: Info: .*
+.*:3: Error: .*
+.*:83: Info: .*
+.*:3: Error: .*
+.*:88: Info: .*
+.*:3: Error: .*
+.*:91: Info: .*
+.*:3: Error: .*
+.*:92: Info: .*
+.*:3: Error: .*
+.*:97: Info: .*
+.*:3: Error: .*
+.*:100: Info: .*
+.*:3: Error: .*
+.*:101: Info: .*
+.*:3: Error: .*
+.*:108: Info: .*
+.*:3: Error: .*
+.*:109: Info: .*
+.*:3: Error: .*
+.*:112: Info: .*
+.*:3: Error: .*
+.*:116: Info: .*
+.*:3: Error: .*
+.*:117: Info: .*
+.*:3: Error: .*
+.*:120: Info: .*
+.*:3: Error: .*
+.*:126: Info: .*
+.*:3: Error: .*
+.*:140: Info: .*
+.*:3: Error: .*
+.*:153: Info: .*
+.*:3: Error: .*
+.*:154: Info: .*
+.*:3: Error: .*
+.*:155: Info: .*
+.*:3: Error: .*
+.*:158: Info: .*
+.*:3: Error: .*
+.*:159: Info: .*
+.*:3: Error: .*
+.*:160: Info: .*
+.*:3: Error: .*
+.*:161: Info: .*
+.*:3: Error: .*
+.*:162: Info: .*
+.*:3: Error: .*
+.*:163: Info: .*
+.*:3: Error: .*
+.*:167: Info: .*
+.*:3: Error: .*
+.*:168: Info: .*
+.*:3: Error: .*
+.*:169: Info: .*
+.*:3: Error: .*
+.*:172: Info: .*
+.*:3: Error: .*
+.*:173: Info: .*
+.*:3: Error: .*
+.*:174: Info: .*
+.*:3: Error: .*
+.*:175: Info: .*
+.*:3: Error: .*
+.*:176: Info: .*
+.*:3: Error: .*
+.*:177: Info: .*
+.*:3: Error: .*
+.*:190: Info: .*
.*:193: Error: .* too large for field of 4 bytes at .*
.*:194: Error: .* too large for field of 4 bytes at .*
.*:195: Error: .* too large for field of 4 bytes at .*
.*: Assembler messages:
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `iret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lcall'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ljmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ptwrite'
+.*:[1-9][0-9]*: Info: .*
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sysexit'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sysret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*: Assembler messages:
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*: Assembler messages:
-.*:14: Warning: .*shortened.*
-.*:18: Warning: .*shortened.*
-.*:22: Warning: .*shortened.*
-.*:31: Warning: .*shortened.*
-.*:79: Warning: .*shortened.*
-.*:95: Warning: .*shortened.*
-.*:124: Warning: .*shortened.*
-.*:148: Warning: .*shortened.*
-.*:151: Warning: .*shortened.*
-.*:161: Warning: .*shortened.*
+.*:3: Warning: .*shortened.*
+.*:14: Info: .*
+.*:3: Warning: .*shortened.*
+.*:18: Info: .*
+.*:3: Warning: .*shortened.*
+.*:22: Info: .*
+.*:3: Warning: .*shortened.*
+.*:31: Info: .*
+.*:3: Warning: .*shortened.*
+.*:79: Info: .*
+.*:3: Warning: .*shortened.*
+.*:95: Info: .*
+.*:3: Warning: .*shortened.*
+.*:124: Info: .*
+.*:3: Warning: .*shortened.*
+.*:148: Info: .*
+.*:3: Warning: .*shortened.*
+.*:151: Info: .*
+.*:3: Warning: .*shortened.*
+.*:161: Info: .*
.*: Assembler messages:
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*: Assembler messages:
-.*:30: Warning: .*shortened.*
-.*:34: Warning: .*shortened.*
-.*:38: Warning: .*shortened.*
-.*:47: Warning: .*shortened.*
-.*:99: Warning: .*shortened.*
-.*:117: Warning: .*shortened.*
-.*:146: Warning: .*shortened.*
-.*:170: Warning: .*shortened.*
-.*:175: Warning: .*shortened.*
-.*:179: Warning: .*shortened.*
+.*:3: Warning: .*shortened.*
+.*:30: Info: .*
+.*:3: Warning: .*shortened.*
+.*:34: Info: .*
+.*:3: Warning: .*shortened.*
+.*:38: Info: .*
+.*:3: Warning: .*shortened.*
+.*:47: Info: .*
+.*:3: Warning: .*shortened.*
+.*:99: Info: .*
+.*:3: Warning: .*shortened.*
+.*:117: Info: .*
+.*:3: Warning: .*shortened.*
+.*:146: Info: .*
+.*:3: Warning: .*shortened.*
+.*:170: Info: .*
+.*:3: Warning: .*shortened.*
+.*:175: Info: .*
+.*:3: Warning: .*shortened.*
+.*:179: Info: .*
.*: Assembler messages:
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `crc32'
+.*:[1-9][0-9]*: Info: .*
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `iret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `lret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ptwrite'
+.*:[1-9][0-9]*: Info: .*
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sysexit'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `sysret'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Info: .*
.*: Assembler messages:
-.*:30: Error: .*
-.*:31: Error: .*
-.*:33: Error: .*
-.*:34: Error: .*
-.*:37: Error: .*
-.*:38: Error: .*
-.*:40: Error: .*
-.*:41: Error: .*
-.*:51: Error: .*
-.*:52: Error: .*
-.*:54: Error: .*
-.*:56: Error: .*
-.*:59: Error: .*
-.*:60: Error: .*
-.*:62: Error: .*
-.*:63: Error: .*
-.*:66: Error: .*
-.*:67: Error: .*
-.*:69: Error: .*
-.*:70: Error: .*
-.*:73: Error: .*
-.*:74: Error: .*
-.*:76: Error: .*
-.*:77: Error: .*
-.*:80: Error: .*
-.*:81: Error: .*
-.*:83: Error: .*
-.*:84: Error: .*
-.*:87: Error: .*
-.*:88: Error: .*
-.*:90: Error: .*
-.*:91: Error: .*
-.*:94: Error: .*
-.*:95: Error: .*
-.*:97: Error: .*
-.*:98: Error: .*
-.*:101: Error: .*
-.*:102: Error: .*
-.*:104: Error: .*
-.*:105: Error: .*
-.*:108: Error: .*
-.*:109: Error: .*
-.*:111: Error: .*
-.*:112: Error: .*
-.*:133: Error: .*
-.*:134: Error: .*
-.*:137: Error: .*
-.*:138: Error: .*
-.*:139: Error: .*
-.*:140: Error: .*
-.*:141: Error: .*
-.*:142: Error: .*
-.*:143: Error: .*
-.*:144: Error: .*
-.*:145: Error: .*
-.*:149: Error: .*
-.*:150: Error: .*
-.*:153: Error: .*
-.*:154: Error: .*
-.*:155: Error: .*
-.*:156: Error: .*
-.*:157: Error: .*
-.*:158: Error: .*
-.*:159: Error: .*
-.*:160: Error: .*
-.*:161: Error: .*
-.*:164: Error: .*
+.*:3: Error: .*
+.*:30: Info: .*
+.*:3: Error: .*
+.*:31: Info: .*
+.*:3: Error: .*
+.*:33: Info: .*
+.*:3: Error: .*
+.*:34: Info: .*
+.*:3: Error: .*
+.*:37: Info: .*
+.*:3: Error: .*
+.*:38: Info: .*
+.*:3: Error: .*
+.*:40: Info: .*
+.*:3: Error: .*
+.*:41: Info: .*
+.*:3: Error: .*
+.*:51: Info: .*
+.*:3: Error: .*
+.*:52: Info: .*
+.*:3: Error: .*
+.*:54: Info: .*
+.*:3: Error: .*
+.*:56: Info: .*
+.*:3: Error: .*
+.*:59: Info: .*
+.*:3: Error: .*
+.*:60: Info: .*
+.*:3: Error: .*
+.*:62: Info: .*
+.*:3: Error: .*
+.*:63: Info: .*
+.*:3: Error: .*
+.*:66: Info: .*
+.*:3: Error: .*
+.*:67: Info: .*
+.*:3: Error: .*
+.*:69: Info: .*
+.*:3: Error: .*
+.*:70: Info: .*
+.*:3: Error: .*
+.*:73: Info: .*
+.*:3: Error: .*
+.*:74: Info: .*
+.*:3: Error: .*
+.*:76: Info: .*
+.*:3: Error: .*
+.*:77: Info: .*
+.*:3: Error: .*
+.*:80: Info: .*
+.*:3: Error: .*
+.*:81: Info: .*
+.*:3: Error: .*
+.*:83: Info: .*
+.*:3: Error: .*
+.*:84: Info: .*
+.*:3: Error: .*
+.*:87: Info: .*
+.*:3: Error: .*
+.*:88: Info: .*
+.*:3: Error: .*
+.*:90: Info: .*
+.*:3: Error: .*
+.*:91: Info: .*
+.*:3: Error: .*
+.*:94: Info: .*
+.*:3: Error: .*
+.*:95: Info: .*
+.*:3: Error: .*
+.*:97: Info: .*
+.*:3: Error: .*
+.*:98: Info: .*
+.*:3: Error: .*
+.*:101: Info: .*
+.*:3: Error: .*
+.*:102: Info: .*
+.*:3: Error: .*
+.*:104: Info: .*
+.*:3: Error: .*
+.*:105: Info: .*
+.*:3: Error: .*
+.*:108: Info: .*
+.*:3: Error: .*
+.*:109: Info: .*
+.*:3: Error: .*
+.*:111: Info: .*
+.*:3: Error: .*
+.*:112: Info: .*
+.*:3: Error: .*
+.*:133: Info: .*
+.*:3: Error: .*
+.*:134: Info: .*
+.*:3: Error: .*
+.*:137: Info: .*
+.*:3: Error: .*
+.*:138: Info: .*
+.*:3: Error: .*
+.*:139: Info: .*
+.*:3: Error: .*
+.*:140: Info: .*
+.*:3: Error: .*
+.*:141: Info: .*
+.*:3: Error: .*
+.*:142: Info: .*
+.*:3: Error: .*
+.*:143: Info: .*
+.*:3: Error: .*
+.*:144: Info: .*
+.*:3: Error: .*
+.*:145: Info: .*
+.*:3: Error: .*
+.*:149: Info: .*
+.*:3: Error: .*
+.*:150: Info: .*
+.*:3: Error: .*
+.*:153: Info: .*
+.*:3: Error: .*
+.*:154: Info: .*
+.*:3: Error: .*
+.*:155: Info: .*
+.*:3: Error: .*
+.*:156: Info: .*
+.*:3: Error: .*
+.*:157: Info: .*
+.*:3: Error: .*
+.*:158: Info: .*
+.*:3: Error: .*
+.*:159: Info: .*
+.*:3: Error: .*
+.*:160: Info: .*
+.*:3: Error: .*
+.*:161: Info: .*
+.*:3: Error: .*
+.*:164: Info: .*
#pass
.*: Assembler messages:
-.*:35: Error: .*
-.*:36: Error: .*
-.*:37: Error: .*
-.*:39: Error: .*
-.*:40: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:46: Error: .*
-.*:47: Error: .*
-.*:48: Error: .*
-.*:49: Error: .*
-.*:51: Error: .*
-.*:53: Error: .*
-.*:54: Error: .*
-.*:55: Error: .*
-.*:57: Error: .*
-.*:73: Error: .*
-.*:75: Error: .*
-.*:76: Error: .*
-.*:77: Error: .*
-.*:79: Error: .*
-.*:81: Error: .*
-.*:83: Error: .*
-.*:85: Error: .*
-.*:86: Error: .*
-.*:87: Error: .*
-.*:89: Error: .*
-.*:92: Error: .*
-.*:94: Error: .*
-.*:95: Error: .*
-.*:96: Error: .*
-.*:98: Error: .*
-.*:101: Error: .*
-.*:103: Error: .*
-.*:104: Error: .*
-.*:105: Error: .*
-.*:107: Error: .*
-.*:112: Error: .*
-.*:113: Error: .*
-.*:114: Error: .*
-.*:116: Error: .*
-.*:117: Error: .*
-.*:121: Error: .*
-.*:122: Error: .*
-.*:123: Error: .*
-.*:125: Error: .*
-.*:126: Error: .*
-.*:136: Error: .*
-.*:137: Error: .*
-.*:138: Error: .*
-.*:139: Error: .*
-.*:146: Error: .*
-.*:160: Error: .*
-.*:173: Error: .*
-.*:174: Error: .*
-.*:175: Error: .*
-.*:178: Error: .*
-.*:179: Error: .*
-.*:180: Error: .*
-.*:181: Error: .*
-.*:182: Error: .*
-.*:183: Error: .*
-.*:187: Error: .*
-.*:188: Error: .*
-.*:189: Error: .*
-.*:192: Error: .*
-.*:193: Error: .*
-.*:194: Error: .*
-.*:195: Error: .*
-.*:196: Error: .*
-.*:197: Error: .*
-.*:208: Error: .*
-.*:209: Error: .*
-.*:210: Error: .*
-.*:211: Error: .*
-.*:212: Error: .*
-.*:213: Error: .*
-.*:214: Error: .*
-.*:218: Error: .*
-.*:219: Error: .*
-.*:220: Error: .*
-.*:227: Error: .*
+.*:3: Error: .*
+.*:35: Info: .*
+.*:3: Error: .*
+.*:36: Info: .*
+.*:3: Error: .*
+.*:37: Info: .*
+.*:3: Error: .*
+.*:39: Info: .*
+.*:3: Error: .*
+.*:40: Info: .*
+.*:3: Error: .*
+.*:43: Info: .*
+.*:3: Error: .*
+.*:44: Info: .*
+.*:3: Error: .*
+.*:45: Info: .*
+.*:3: Error: .*
+.*:46: Info: .*
+.*:3: Error: .*
+.*:47: Info: .*
+.*:3: Error: .*
+.*:48: Info: .*
+.*:3: Error: .*
+.*:49: Info: .*
+.*:3: Error: .*
+.*:51: Info: .*
+.*:3: Error: .*
+.*:53: Info: .*
+.*:3: Error: .*
+.*:54: Info: .*
+.*:3: Error: .*
+.*:55: Info: .*
+.*:3: Error: .*
+.*:57: Info: .*
+.*:3: Error: .*
+.*:73: Info: .*
+.*:3: Error: .*
+.*:75: Info: .*
+.*:3: Error: .*
+.*:76: Info: .*
+.*:3: Error: .*
+.*:77: Info: .*
+.*:3: Error: .*
+.*:79: Info: .*
+.*:3: Error: .*
+.*:81: Info: .*
+.*:3: Error: .*
+.*:83: Info: .*
+.*:3: Error: .*
+.*:85: Info: .*
+.*:3: Error: .*
+.*:86: Info: .*
+.*:3: Error: .*
+.*:87: Info: .*
+.*:3: Error: .*
+.*:89: Info: .*
+.*:3: Error: .*
+.*:92: Info: .*
+.*:3: Error: .*
+.*:94: Info: .*
+.*:3: Error: .*
+.*:95: Info: .*
+.*:3: Error: .*
+.*:96: Info: .*
+.*:3: Error: .*
+.*:98: Info: .*
+.*:3: Error: .*
+.*:101: Info: .*
+.*:3: Error: .*
+.*:103: Info: .*
+.*:3: Error: .*
+.*:104: Info: .*
+.*:3: Error: .*
+.*:105: Info: .*
+.*:3: Error: .*
+.*:107: Info: .*
+.*:3: Error: .*
+.*:112: Info: .*
+.*:3: Error: .*
+.*:113: Info: .*
+.*:3: Error: .*
+.*:114: Info: .*
+.*:3: Error: .*
+.*:116: Info: .*
+.*:3: Error: .*
+.*:117: Info: .*
+.*:3: Error: .*
+.*:121: Info: .*
+.*:3: Error: .*
+.*:122: Info: .*
+.*:3: Error: .*
+.*:123: Info: .*
+.*:3: Error: .*
+.*:125: Info: .*
+.*:3: Error: .*
+.*:126: Info: .*
+.*:3: Error: .*
+.*:136: Info: .*
+.*:3: Error: .*
+.*:137: Info: .*
+.*:3: Error: .*
+.*:138: Info: .*
+.*:3: Error: .*
+.*:139: Info: .*
+.*:3: Error: .*
+.*:146: Info: .*
+.*:3: Error: .*
+.*:160: Info: .*
+.*:3: Error: .*
+.*:173: Info: .*
+.*:3: Error: .*
+.*:174: Info: .*
+.*:3: Error: .*
+.*:175: Info: .*
+.*:3: Error: .*
+.*:178: Info: .*
+.*:3: Error: .*
+.*:179: Info: .*
+.*:3: Error: .*
+.*:180: Info: .*
+.*:3: Error: .*
+.*:181: Info: .*
+.*:3: Error: .*
+.*:182: Info: .*
+.*:3: Error: .*
+.*:183: Info: .*
+.*:3: Error: .*
+.*:187: Info: .*
+.*:3: Error: .*
+.*:188: Info: .*
+.*:3: Error: .*
+.*:189: Info: .*
+.*:3: Error: .*
+.*:192: Info: .*
+.*:3: Error: .*
+.*:193: Info: .*
+.*:3: Error: .*
+.*:194: Info: .*
+.*:3: Error: .*
+.*:195: Info: .*
+.*:3: Error: .*
+.*:196: Info: .*
+.*:3: Error: .*
+.*:197: Info: .*
+.*:3: Error: .*
+.*:208: Info: .*
+.*:3: Error: .*
+.*:209: Info: .*
+.*:3: Error: .*
+.*:210: Info: .*
+.*:3: Error: .*
+.*:211: Info: .*
+.*:3: Error: .*
+.*:212: Info: .*
+.*:3: Error: .*
+.*:213: Info: .*
+.*:3: Error: .*
+.*:214: Info: .*
+.*:3: Error: .*
+.*:218: Info: .*
+.*:3: Error: .*
+.*:219: Info: .*
+.*:3: Error: .*
+.*:220: Info: .*
+.*:3: Error: .*
+.*:227: Info: .*
.*: Assembler messages:
-.*:23: Error: .*
-.*:25: Error: .*
-.*:27: Error: .*
-.*:31: Error: .*
-.*:33: Error: .*
-.*:35: Error: .*
-.*:39: Error: .*
-.*:41: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:50: Error: .*
-.*:51: Error: .*
-.*:52: Error: .*
-.*:53: Error: .*
-.*:55: Error: .*
-.*:56: Error: .*
-.*:57: Error: .*
-.*:58: Error: .*
-.*:60: Error: .*
-.*:63: Error: .*
-.*:64: Error: .*
-.*:65: Error: .*
-.*:66: Error: .*
-.*:68: Error: .*
-.*:71: Error: .*
-.*:72: Error: .*
-.*:73: Error: .*
-.*:74: Error: .*
-.*:76: Error: .*
-.*:77: Error: .*
-.*:78: Error: .*
-.*:79: Error: .*
-.*:80: Error: .*
-.*:81: Error: .*
-.*:82: Error: .*
-.*:83: Error: .*
-.*:84: Error: .*
-.*:85: Error: .*
-.*:86: Error: .*
-.*:89: Error: .*
-.*:91: Error: .*
-.*:93: Error: .*
-.*:97: Error: .*
-.*:99: Error: .*
-.*:101: Error: .*
-.*:105: Error: .*
-.*:107: Error: .*
-.*:109: Error: .*
-.*:110: Error: .*
-.*:111: Error: .*
-.*:116: Error: .*
-.*:117: Error: .*
-.*:118: Error: .*
-.*:119: Error: .*
-.*:123: Error: .*
-.*:125: Error: .*
-.*:127: Error: .*
-.*:131: Error: .*
-.*:133: Error: .*
-.*:135: Error: .*
-.*:139: Error: .*
-.*:141: Error: .*
-.*:143: Error: .*
-.*:144: Error: .*
-.*:145: Error: .*
-.*:150: Error: .*
-.*:151: Error: .*
-.*:152: Error: .*
-.*:153: Error: .*
+.*:11: Error: .*
+.*:23: *Info: macro .*
+.*:11: Error: .*
+.*:25: *Info: macro .*
+.*:11: Error: .*
+.*:27: *Info: macro .*
+.*:11: Error: .*
+.*:31: *Info: macro .*
+.*:11: Error: .*
+.*:33: *Info: macro .*
+.*:11: Error: .*
+.*:35: *Info: macro .*
+.*:11: Error: .*
+.*:39: *Info: macro .*
+.*:11: Error: .*
+.*:41: *Info: macro .*
+.*:4: Error: .*
+.*:43: *Info: macro .*
+.*:4: Error: .*
+.*:44: *Info: macro .*
+.*:4: Error: .*
+.*:45: *Info: macro .*
+.*:4: Error: .*
+.*:50: *Info: macro .*
+.*:4: Error: .*
+.*:51: *Info: macro .*
+.*:4: Error: .*
+.*:52: *Info: macro .*
+.*:4: Error: .*
+.*:53: *Info: macro .*
+.*:4: Error: .*
+.*:55: *Info: macro .*
+.*:4: Error: .*
+.*:56: *Info: macro .*
+.*:4: Error: .*
+.*:57: *Info: macro .*
+.*:4: Error: .*
+.*:58: *Info: macro .*
+.*:11: Error: .*
+.*:60: *Info: macro .*
+.*:4: Error: .*
+.*:63: *Info: macro .*
+.*:4: Error: .*
+.*:64: *Info: macro .*
+.*:4: Error: .*
+.*:65: *Info: macro .*
+.*:4: Error: .*
+.*:66: *Info: macro .*
+.*:11: Error: .*
+.*:68: *Info: macro .*
+.*:4: Error: .*
+.*:71: *Info: macro .*
+.*:4: Error: .*
+.*:72: *Info: macro .*
+.*:4: Error: .*
+.*:73: *Info: macro .*
+.*:4: Error: .*
+.*:74: *Info: macro .*
+.*:4: Error: .*
+.*:76: *Info: macro .*
+.*:4: Error: .*
+.*:77: *Info: macro .*
+.*:4: Error: .*
+.*:78: *Info: macro .*
+.*:4: Error: .*
+.*:79: *Info: macro .*
+.*:4: Error: .*
+.*:80: *Info: macro .*
+.*:4: Error: .*
+.*:81: *Info: macro .*
+.*:4: Error: .*
+.*:82: *Info: macro .*
+.*:4: Error: .*
+.*:83: *Info: macro .*
+.*:4: Error: .*
+.*:84: *Info: macro .*
+.*:4: Error: .*
+.*:85: *Info: macro .*
+.*:4: Error: .*
+.*:86: *Info: macro .*
+.*:11: Error: .*
+.*:89: *Info: macro .*
+.*:11: Error: .*
+.*:91: *Info: macro .*
+.*:11: Error: .*
+.*:93: *Info: macro .*
+.*:11: Error: .*
+.*:97: *Info: macro .*
+.*:11: Error: .*
+.*:99: *Info: macro .*
+.*:11: Error: .*
+.*:101: *Info: macro .*
+.*:11: Error: .*
+.*:105: *Info: macro .*
+.*:11: Error: .*
+.*:107: *Info: macro .*
+.*:4: Error: .*
+.*:109: *Info: macro .*
+.*:4: Error: .*
+.*:110: *Info: macro .*
+.*:4: Error: .*
+.*:111: *Info: macro .*
+.*:4: Error: .*
+.*:116: *Info: macro .*
+.*:4: Error: .*
+.*:117: *Info: macro .*
+.*:4: Error: .*
+.*:118: *Info: macro .*
+.*:4: Error: .*
+.*:119: *Info: macro .*
+.*:11: Error: .*
+.*:123: *Info: macro .*
+.*:11: Error: .*
+.*:125: *Info: macro .*
+.*:11: Error: .*
+.*:127: *Info: macro .*
+.*:11: Error: .*
+.*:131: *Info: macro .*
+.*:11: Error: .*
+.*:133: *Info: macro .*
+.*:11: Error: .*
+.*:135: *Info: macro .*
+.*:11: Error: .*
+.*:139: *Info: macro .*
+.*:11: Error: .*
+.*:141: *Info: macro .*
+.*:11: Error: .*
+.*:143: *Info: macro .*
+.*:11: Error: .*
+.*:144: *Info: macro .*
+.*:11: Error: .*
+.*:145: *Info: macro .*
+.*:11: Error: .*
+.*:150: *Info: macro .*
+.*:11: Error: .*
+.*:151: *Info: macro .*
+.*:11: Error: .*
+.*:152: *Info: macro .*
+.*:11: Error: .*
+.*:153: *Info: macro .*
.*: Assembler messages:
-.*:28: Error: .*
-.*:29: Error: .*
-.*:36: Error: .*
-.*:37: Error: .*
-.*:43: Error: .*
-.*:44: Error: .*
-.*:45: Error: .*
-.*:46: Error: .*
-.*:47: Error: .*
-.*:48: Error: .*
-.*:49: Error: .*
-.*:50: Error: .*
-.*:51: Error: .*
-.*:52: Error: .*
-.*:53: Error: .*
-.*:55: Error: .*
-.*:56: Error: .*
-.*:57: Error: .*
-.*:58: Error: .*
-.*:61: Error: .*
-.*:62: Error: .*
-.*:63: Error: .*
-.*:64: Error: .*
-.*:65: Error: .*
-.*:66: Error: .*
-.*:69: Error: .*
-.*:70: Error: .*
-.*:71: Error: .*
-.*:72: Error: .*
-.*:73: Error: .*
-.*:74: Error: .*
-.*:76: Error: .*
-.*:77: Error: .*
-.*:78: Error: .*
-.*:79: Error: .*
-.*:80: Error: .*
-.*:81: Error: .*
-.*:82: Error: .*
-.*:83: Error: .*
-.*:84: Error: .*
-.*:85: Error: .*
-.*:86: Error: .*
-.*:94: Error: .*
-.*:95: Error: .*
-.*:102: Error: .*
-.*:103: Error: .*
-.*:109: Error: .*
-.*:110: Error: .*
-.*:111: Error: .*
-.*:112: Error: .*
-.*:113: Error: .*
-.*:114: Error: .*
-.*:115: Error: .*
-.*:116: Error: .*
-.*:117: Error: .*
-.*:118: Error: .*
-.*:119: Error: .*
+.*:17: Error: .*
+.*:28: *Info: macro .*
+.*:17: Error: .*
+.*:29: *Info: macro .*
+.*:17: Error: .*
+.*:36: *Info: macro .*
+.*:17: Error: .*
+.*:37: *Info: macro .*
+.*:4: Error: .*
+.*:43: *Info: macro .*
+.*:4: Error: .*
+.*:44: *Info: macro .*
+.*:4: Error: .*
+.*:45: *Info: macro .*
+.*:17: Error: .*
+.*:46: *Info: macro .*
+.*:17: Error: .*
+.*:47: *Info: macro .*
+.*:17: Error: .*
+.*:48: *Info: macro .*
+.*:17: Error: .*
+.*:49: *Info: macro .*
+.*:4: Error: .*
+.*:50: *Info: macro .*
+.*:4: Error: .*
+.*:51: *Info: macro .*
+.*:4: Error: .*
+.*:52: *Info: macro .*
+.*:4: Error: .*
+.*:53: *Info: macro .*
+.*:4: Error: .*
+.*:55: *Info: macro .*
+.*:4: Error: .*
+.*:56: *Info: macro .*
+.*:4: Error: .*
+.*:57: *Info: macro .*
+.*:4: Error: .*
+.*:58: *Info: macro .*
+.*:17: Error: .*
+.*:61: *Info: macro .*
+.*:17: Error: .*
+.*:62: *Info: macro .*
+.*:4: Error: .*
+.*:63: *Info: macro .*
+.*:4: Error: .*
+.*:64: *Info: macro .*
+.*:4: Error: .*
+.*:65: *Info: macro .*
+.*:4: Error: .*
+.*:66: *Info: macro .*
+.*:17: Error: .*
+.*:69: *Info: macro .*
+.*:17: Error: .*
+.*:70: *Info: macro .*
+.*:4: Error: .*
+.*:71: *Info: macro .*
+.*:4: Error: .*
+.*:72: *Info: macro .*
+.*:4: Error: .*
+.*:73: *Info: macro .*
+.*:4: Error: .*
+.*:74: *Info: macro .*
+.*:4: Error: .*
+.*:76: *Info: macro .*
+.*:4: Error: .*
+.*:77: *Info: macro .*
+.*:4: Error: .*
+.*:78: *Info: macro .*
+.*:4: Error: .*
+.*:79: *Info: macro .*
+.*:4: Error: .*
+.*:80: *Info: macro .*
+.*:4: Error: .*
+.*:81: *Info: macro .*
+.*:4: Error: .*
+.*:82: *Info: macro .*
+.*:4: Error: .*
+.*:83: *Info: macro .*
+.*:4: Error: .*
+.*:84: *Info: macro .*
+.*:4: Error: .*
+.*:85: *Info: macro .*
+.*:4: Error: .*
+.*:86: *Info: macro .*
+.*:17: Error: .*
+.*:94: *Info: macro .*
+.*:17: Error: .*
+.*:95: *Info: macro .*
+.*:17: Error: .*
+.*:102: *Info: macro .*
+.*:17: Error: .*
+.*:103: *Info: macro .*
+.*:4: Error: .*
+.*:109: *Info: macro .*
+.*:4: Error: .*
+.*:110: *Info: macro .*
+.*:4: Error: .*
+.*:111: *Info: macro .*
+.*:17: Error: .*
+.*:112: *Info: macro .*
+.*:17: Error: .*
+.*:113: *Info: macro .*
+.*:17: Error: .*
+.*:114: *Info: macro .*
+.*:17: Error: .*
+.*:115: *Info: macro .*
+.*:4: Error: .*
+.*:116: *Info: macro .*
+.*:4: Error: .*
+.*:117: *Info: macro .*
+.*:4: Error: .*
+.*:118: *Info: macro .*
+.*:4: Error: .*
+.*:119: *Info: macro .*
.*Assembler messages:
.*Warning: read-only CSR is written `csrw cycle,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw time,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instret,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31,a1'
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw cycleh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw timeh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instreth,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mvendorid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw marchid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mimpid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mconfigptr,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hgeip,a1'
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mtopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw stopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vstopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw scountovf,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.10'
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vl,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vtype,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
+.*Info: macro .*
.*Assembler messages:
.*Warning: read-only CSR is written `csrw cycle,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw time,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instret,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31,a1'
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw cycleh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw timeh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instreth,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mvendorid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw marchid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mimpid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mconfigptr,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hgeip,a1'
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mtopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw stopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vstopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw scountovf,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.11'
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vl,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vtype,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
+.*Info: macro .*
.*Assembler messages:
.*Warning: read-only CSR is written `csrw cycle,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw time,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instret,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31,a1'
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw cycleh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw timeh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instreth,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31h,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mvendorid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw marchid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mimpid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mconfigptr,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hgeip,a1'
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mtopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw stopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vstopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw scountovf,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `ubadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sbadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sptbr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbadaddr' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mucounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mbound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mibase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mibound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mdbase' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mdbound' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mscounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `mhcounteren' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uie' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uie' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `utvec' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `utvec' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uscratch' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uscratch' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uepc' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uepc' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `ucause' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `ucause' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `utval' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `utval' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uip' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `uip' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sedeleg' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sedeleg' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sideleg' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `sideleg' for the privileged spec `1.12'
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vl,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vtype,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
+.*Info: macro .*
.*Assembler messages:
.*Warning: read-only CSR is written `csrw cycle,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw time,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instret,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31,a1'
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `cycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw cycleh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `timeh', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw timeh,a1'
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `instreth', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw instreth,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter3h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter4h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter5h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter6h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter7h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter8h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter9h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter10h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter11h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter12h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter13h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter14h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter15h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter16h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter17h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter18h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter19h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter20h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter21h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter22h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter23h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter24h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter25h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter26h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter27h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter28h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter29h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter30h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hpmcounter31h,a1'
+.*Info: macro .*
.*Warning: invalid CSR `scounteren' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `scounteren' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `senvcfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `stval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `stval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `satp' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `satp' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mvendorid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw marchid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mimpid,a1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mhartid,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mconfigptr' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mconfigptr,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mcounteren' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mstatush', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstatush' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtinst' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mtval2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `menvcfgh' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfg' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mseccfgh' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg0' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg1' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg3' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg4' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg5' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg6' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg7' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg8' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg9' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg10' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg11' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg12' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg13' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg14' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `pmpcfg15' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr0' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr0' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr1' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr1' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr2' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr3' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr3' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr4' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr4' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr5' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr5' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr6' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr6' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr7' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr7' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr8' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr8' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr9' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr9' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr10' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr10' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr11' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr11' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr12' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr12' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr13' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr13' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr14' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr14' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr15' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr15' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr16' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr17' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr18' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr19' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr20' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr21' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr22' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr23' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr24' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr25' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr26' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr27' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr28' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr29' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr30' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr31' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr32' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr33' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr34' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr35' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr36' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr37' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr38' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr39' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr40' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr41' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr42' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr43' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr44' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr45' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr46' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr47' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr48' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr49' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr50' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr51' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr52' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr53' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr54' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr55' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr56' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr57' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr58' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr59' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr60' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr61' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr62' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `pmpaddr63' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcycleh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `minstreth', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmcounter31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `mcountinhibit' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hedeleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hideleg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hcounteren', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htinst', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgeip', needs `h' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw hgeip,a1'
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `henvcfgh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hgatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedelta', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `htimedeltah', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsstatus', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsie', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstvec', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsscratch', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsepc', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vscause', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstval', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsip', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsatp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miselect', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mireg', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopei', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mtopi', needs `smaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw mtopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvien', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvip', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `midelegh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mieh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mvienh', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mviph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `miph', needs `smaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `sstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen0h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen1h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen2h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mstateen3h', needs `smstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen0h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen1h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen2h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hstateen3h', needs `ssstateen' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `stopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw stopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `sieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `siph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvien', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvictl', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiselect', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsireg', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopei', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstopi', needs `ssaia' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vstopi,a1'
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hidelegh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hvienh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio1h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `hviprio2h', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsieh', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vsiph', needs `ssaia' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `scountovf', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw scountovf,a1'
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent3h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent4h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent5h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent6h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent7h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent8h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent9h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent10h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent11h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent12h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent13h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent14h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent15h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent16h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent17h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent18h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent19h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent20h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent21h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent22h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent23h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent24h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent25h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent26h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent27h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent28h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent29h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent30h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `mhpmevent31h', needs `sscofpmf' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `stimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmp', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs rv32i extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `h' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstimecmph', needs `sstc' extension
+.*Info: macro .*
.*Warning: invalid CSR `utval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `utval' for the privileged spec `1.9.1'
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `frm', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `fcsr', needs `f' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `seed', needs `zkr' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vstart', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxsat', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vxrm', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vcsr', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vl', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vl,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vtype', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vtype,a1'
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: invalid CSR `vlenb', needs `zve32x' extension
+.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
+.*Info: macro .*
projects / binutils-gdb.git / commitdiff