Fix binary pattern for cpfg,f0,c instruction

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5e4e6abf7c19a96d64a81e14aca0222c6101c0a6..731e9e4f9b65e47c953051dbbb117f36625f8386 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+1999-11-22  Nick Clifton  <nickc@cygnus.com>
+
+       * d10v-opc.c: Fix pattern for "cpfg,f{0|1},c" instruction.
+
 1999-11-18  Gavin Romig-Koch  <gavin@cygnus.com>
 
        * mips-opc.c (I5): New.

diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c
index 7970d481c265a6a023222bda5be1f0be0c904c43..c4bb098b65c9159978957abd20ba496c308f9796 100644 (file)
--- a/opcodes/d10v-opc.c
+++ b/opcodes/d10v-opc.c
@@ -206,8 +206,8 @@ const struct d10v_opcode d10v_opcodes[] = {
   { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
   { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
   { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
+  { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } },
   { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
-  { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, CFSRC } },
   { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } },
   { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
   { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },