fix bogus assumption if ddx has set up surface reg for z buffer

this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index ceb947c09d29a1dd61299393993b1be790d88f18..c12eef20242f88a493ebfc112377c1dfee91463c 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -720,8 +720,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    screen->depthPitch  = dri_priv->depthPitch;
 
    /* Check if ddx has set up a surface reg to cover depth buffer */
-   screen->depthHasSurface = ((sPriv->ddx_version.major > 4) &&
-      (screen->chip_flags & RADEON_CHIPSET_TCL));
+   screen->depthHasSurface = (sPriv->ddx_version.major > 4);
 
    if ( dri_priv->textureSize == 0 ) {
       screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;