sscreen->b.chip_class >= VI &&
sscreen->b.info.max_se >= 2;
+ sscreen->has_draw_indirect_multi =
+ (sscreen->b.family >= CHIP_POLARIS10) ||
+ (sscreen->b.chip_class == VI &&
+ sscreen->b.info.pfp_fw_version >= 121 &&
+ sscreen->b.info.me_fw_version >= 87) ||
+ (sscreen->b.chip_class == CIK &&
+ sscreen->b.info.pfp_fw_version >= 211 &&
+ sscreen->b.info.me_fw_version >= 173) ||
+ (sscreen->b.chip_class == SI &&
+ sscreen->b.info.pfp_fw_version >= 121 &&
+ sscreen->b.info.me_fw_version >= 87);
+
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
pipe_mutex_init(sscreen->shader_parts_mutex);
unsigned gs_table_depth;
unsigned tess_offchip_block_dw_size;
bool has_distributed_tess;
+ bool has_draw_indirect_multi;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
radeon_emit(cs, index_max_size);
}
- if (sctx->b.family < CHIP_POLARIS10) {
+ if (!sctx->screen->has_draw_indirect_multi) {
radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
: PKT3_DRAW_INDIRECT,
3, render_cond_bit));