Fix DQS_N errors

diff --git a/gram/simulation/dram_model/ddr3.v b/gram/simulation/dram_model/ddr3.v
index 8918882dd6f02739f3256d53c982902de465a230..732f75ceb432615a17d34912a5c12ba4cc1cbbbe 100644 (file)
--- a/gram/simulation/dram_model/ddr3.v
+++ b/gram/simulation/dram_model/ddr3.v
@@ -503,7 +503,7 @@ module ddr3 (
     always @(ba     ) ba_in      <= #BUS_DELAY ba;
     always @(addr   ) addr_in    <= #BUS_DELAY addr;
     always @(dq     ) dq_in      <= #BUS_DELAY dq;
-    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<32) | dqs;
+    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (~dqs<<32) | dqs;
     always @(odt    ) if (!feature_odt_hi) odt_in     <= #BUS_DELAY odt;
     // create internal clock
     always @(posedge ck_in) diff_ck <= ck_in;
@@ -540,11 +540,11 @@ module ddr3 (
     wire [DQS_BITS-1:0] dqs_en1 = dqs_out_en_dly & {DQS_BITS{out_en}};
     wire [DQ_BITS-1:0] dq_en2 = dq_out_en_dly & {DQS_BITS{out_en}};
     bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,   dqs_in0  ,dqs_en0  );
-    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n, dqs_in1  ,dqs_en1 );
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (~dqs, dqs_in1  ,dqs_en1 );
     bufif1 buf_dq     [DQ_BITS-1:0]  (dq,  dq_in2    , dq_en2 );
 `else
     bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}     }); 
-    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}     }); 
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (~dqs,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}     }); 
     bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}     });
 `endif
     assign tdqs_n = {DQS_BITS{1'bz}};

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index bb3a321b2b463497ca65dd26c5143353821aa3dd..508a35a7ded13bac87a9490aff0c58a2a32098ba 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -40,8 +40,8 @@ module simsoctb;
   wire dram_ras_n;
   wire dram_cas_n;
   wire [15:0] dram_dq;
-  wire [1:0] dram_dqs;
-  wire [1:0] dram_dqs_n;
+  inout wire [1:0] dram_dqs;
+  inout wire [1:0] dram_dqs_n;
   wire [13:0] dram_a;
   wire [2:0] dram_ba;
   wire [1:0] dram_dm;
@@ -69,6 +69,9 @@ module simsoctb;
     .tdqs_n(dram_tdqs_n),
     .odt(dram_odt)
   );
+
+  assign dram_dqs_n = (dram_dqs != 2'hz) ? ~dram_dqs : 2'hz;
+
   //defparam ram_chip.
   
   top simsoctop (