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diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 9cf93f38d40ed7b8ba50e005a457d8af96d782a2..1aa504f6d7ae5ed32b70acdec9f1118bf856b4a2 100644 (file)
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -272,6 +272,17 @@ area of research on its own deemed unlikely to be achievable.
 Note: none of these instructions are in VSX. They are a different paradigm
 and have more akin with their x86 equivalents.
 
+**Critical to note regarding 2-out instructions**:
+
+<https://groups.google.com/g/comp.arch/c/_-dp_ZU6TN0/m/hVuZt86_BgAJ>
+
+```
+>For example, having instructions with 2 dest registers changes
+>the cost for a multi-lane OoO renamer from BigO(n^2) to BigO((2n)^2)
+>so a 4-lane 2-dest renamer costs 16 times as much.
+>And this is for a feature that would be rarely used and is redundant. 
+```
+
 ## fclass and GPR-FPR moves
 
 [[sv/fclass]] - just one instruction.  With SFFS being locked down to