ruby: print addresses in hex

Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements.  So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals.  This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address.  This function has been put to use in some of the
places.  At other places, change has been made to print just the address in
hex.

diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index 3f22a4906a7b302c04062661f0f7a2a643b455b0..30105727c82eb4d47191ee84a9013bc7f7ea2c62 100644 (file)
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -369,7 +369,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
         out_msg.Class := CoherenceClass:GETS;
         out_msg.Sender := machineID;
         out_msg.Dest := createMachineID(MachineType:L1Cache, version);
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Dest);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -386,7 +386,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
         DPRINTF(RubySlicc, "%s\n", machineID);
         out_msg.Dest := createMachineID(MachineType:L1Cache, version);
 
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Dest);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -402,7 +402,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
         out_msg.Sender := machineID;
         out_msg.Dest := createMachineID(MachineType:L1Cache, version);
 
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Dest);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -438,7 +438,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }

diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
index 0eb9a43b53121d697d3d30b7f2310e98b674f008..c6b4cda649837e2e29d99279899bb3d38224b805 100644 (file)
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -392,7 +392,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, clusterID));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -409,7 +409,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         DPRINTF(RubySlicc, "%s\n", machineID);
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, clusterID));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -425,7 +425,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, clusterID));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.AccessMode := in_msg.AccessMode;
@@ -580,7 +580,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, clusterID));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DPRINTF(RubySlicc, "%s\n", address);
+      DPRINTF(RubySlicc, "%#x\n", address);
     }
   }
 
@@ -592,7 +592,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, clusterID));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DPRINTF(RubySlicc, "%s\n", address);
+      DPRINTF(RubySlicc, "%#x\n", address);
 
     }
   }

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index c40a47caee8ec13a5089be37b1e0edfb4aac325f..b8a4c6220b3b2e4bfcc6e6b9616e983f5bb1b5fc 100644 (file)
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -528,7 +528,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
@@ -545,7 +545,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
@@ -562,7 +562,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
@@ -585,7 +585,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
               out_msg.Prefetch := in_msg.Prefetch;
               out_msg.AccessMode := in_msg.AccessMode;
 
-              DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+              DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                       address, out_msg.Destination);
           }
       }
@@ -600,7 +600,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         DPRINTF(RubySlicc, "%s\n", machineID);
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
@@ -620,7 +620,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
               out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
 
-              DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+              DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                       address, out_msg.Destination);
               out_msg.MessageSize := MessageSizeType:Control;
               out_msg.Prefetch := in_msg.Prefetch;
@@ -637,7 +637,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         out_msg.Requestor := machineID;
         out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
-        DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+        DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
                 address, out_msg.Destination);
         out_msg.MessageSize := MessageSizeType:Control;
         out_msg.Prefetch := in_msg.Prefetch;
@@ -759,7 +759,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }
@@ -790,7 +790,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DPRINTF(RubySlicc, "%s\n", address);
+      DPRINTF(RubySlicc, "%#x\n", address);
     }
   }
 
@@ -802,7 +802,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
       out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
                           l2_select_low_bit, l2_select_num_bits, intToID(0)));
       out_msg.MessageSize := MessageSizeType:Response_Control;
-      DPRINTF(RubySlicc, "%s\n", address);
+      DPRINTF(RubySlicc, "%#x\n", address);
 
     }
   }

diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index 4134b796497a006e8e7776f4fb7b4056d7529089..0fd9028c6a2ad1c427afe8455a85d82b5438ef34 100644 (file)
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -174,7 +174,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+    DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %#x\n",
             machineID, requestor, addr);
     cache_entry.Sharers.add(requestor);
   }
@@ -267,7 +267,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         return Event:L1_PUTX_old;
       }
     } else {
-      DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
+      DPRINTF(RubySlicc, "address: %#x, Request Type: %s\n", addr, type);
       error("Invalid L1 forwarded request type");
     }
   }
@@ -293,7 +293,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       peek(L1unblockNetwork_in,  ResponseMsg) {
         Entry cache_entry := getCacheEntry(in_msg.addr);
         TBE tbe := TBEs[in_msg.addr];
-        DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
+        DPRINTF(RubySlicc, "Addr: %#x State: %s Sender: %s Type: %s Dest: %s\n",
                 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
                 in_msg.Sender, in_msg.Type, in_msg.Destination);
 
@@ -357,7 +357,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         Entry cache_entry := getCacheEntry(in_msg.addr);
         TBE tbe := TBEs[in_msg.addr];
 
-        DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
+        DPRINTF(RubySlicc, "Addr: %#x State: %s Req: %s Type: %s Dest: %s\n",
                 in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
                 in_msg.Requestor, in_msg.Type, in_msg.Destination);
 
@@ -546,7 +546,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
       out_msg.Destination.add(tbe.L1_GetX_ID);
       DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
       out_msg.DataBlk := cache_entry.DataBlk;
-      DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
+      DPRINTF(RubySlicc, "Address: %#x, Destination: %s, DataBlock: %s\n",
               out_msg.addr, out_msg.Destination, out_msg.DataBlk);
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }

diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 0a15704942fe75f19e6447824ffc610f46b31f0e..1a83704e2c7002e89930c7f86c51854f691b9de6 100644 (file)
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -396,7 +396,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }

diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 1b1fd4ac7d155256f939f4845ae4fc9392dd8540..1327471fce22bc8dba389fc3fdb37fa6704e4535 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -514,7 +514,7 @@ machine(L1Cache, "Directory protocol")
           out_msg.Acks := in_msg.Acks;
           out_msg.MessageSize := MessageSizeType:Response_Data;
         }
-        DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.addr);
+        DPRINTF(RubySlicc, "Sending data to L2: %#x\n", in_msg.addr);
       }
       else {
         enqueue(responseNetwork_out, ResponseMsg, request_latency) {
@@ -889,7 +889,7 @@ machine(L1Cache, "Directory protocol")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }

diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 84fb276e3d268eb81fd968824a8f17acb7efe1cb..07cfe18d3b18b836fcf674abb2a012e72340dae2 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -797,7 +797,7 @@ machine(L2Cache, "Token protocol")
       out_msg.Dirty := false;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, tbe.DataBlk);
   }
 
@@ -814,7 +814,7 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := tbe.Local_GETX_IntAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, tbe.DataBlk);
   }
 
@@ -864,7 +864,7 @@ machine(L2Cache, "Token protocol")
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, tbe.DataBlk);
   }
 
@@ -883,7 +883,7 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, tbe.DataBlk);
   }
 
@@ -900,7 +900,7 @@ machine(L2Cache, "Token protocol")
       out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
       out_msg.MessageSize := MessageSizeType:Response_Data;
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, tbe.DataBlk);
   }
 
@@ -920,7 +920,7 @@ machine(L2Cache, "Token protocol")
         out_msg.MessageSize := MessageSizeType:ResponseL2hit_Data;
       }
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
   }
 
@@ -940,7 +940,7 @@ machine(L2Cache, "Token protocol")
         out_msg.Acks := tbe.Local_GETX_IntAcks;
       }
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
   }
 
@@ -959,7 +959,7 @@ machine(L2Cache, "Token protocol")
         out_msg.Acks := in_msg.Acks;
       }
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
   }
 
@@ -980,7 +980,7 @@ machine(L2Cache, "Token protocol")
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
   }
 
@@ -1044,7 +1044,7 @@ machine(L2Cache, "Token protocol")
   action(ee_sendLocalInv, "\ee", desc="Send local invalidates") {
     assert(is_valid(tbe));
     tbe.NumIntPendingAcks := countLocalSharers(cache_entry, address);
-    DPRINTF(RubySlicc, "Address: %s, Local Sharers: %s, Pending Acks: %d\n",
+    DPRINTF(RubySlicc, "Address: %#x, Local Sharers: %s, Pending Acks: %d\n",
             address, getLocalSharers(cache_entry, address),
             tbe.NumIntPendingAcks);
     if (isLocalOwnerValid(cache_entry, address)) {
@@ -1494,7 +1494,7 @@ machine(L2Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       assert(is_valid(cache_entry));
       cache_entry.DataBlk := in_msg.DataBlk;
-      DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+      DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
       if ((cache_entry.Dirty == false) && in_msg.Dirty) {
         cache_entry.Dirty := in_msg.Dirty;

diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index dac2027b9596ddf2ecab79332f3e4898527706fe..b8c2da761dcc9b1cf911e163d68be205dcd0a522 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -1294,7 +1294,7 @@ machine(L1Cache, "Token protocol")
 
   action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
 
     L1Dcache.setMRU(cache_entry);
@@ -1304,7 +1304,7 @@ machine(L1Cache, "Token protocol")
 
   action(h_ifetch_hit, "hi", desc="Notify sequencer the load completed.") {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
 
     L1Icache.setMRU(cache_entry);
@@ -1314,7 +1314,7 @@ machine(L1Cache, "Token protocol")
 
   action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
     peek(responseNetwork_in, ResponseMsg) {
       L1Icache.setMRU(address);
@@ -1327,7 +1327,7 @@ machine(L1Cache, "Token protocol")
 
   action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
 
     L1Dcache.setMRU(cache_entry);
@@ -1339,7 +1339,7 @@ machine(L1Cache, "Token protocol")
 
   action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
     assert(is_valid(cache_entry));
-    DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+    DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
             address, cache_entry.DataBlk);
     peek(responseNetwork_in, ResponseMsg) {
       L1Icache.setMRU(address);
@@ -1424,7 +1424,7 @@ machine(L1Cache, "Token protocol")
     peek(responseNetwork_in, ResponseMsg) {
       assert(is_valid(cache_entry));
       assert(in_msg.Tokens != 0);
-      DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
+      DPRINTF(RubySlicc, "L1 received tokens for address: %#x, tokens: %d\n",
               in_msg.addr, in_msg.Tokens);
       cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
       DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
@@ -1544,7 +1544,7 @@ machine(L1Cache, "Token protocol")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index cfb2526a5fc1ff56638a7c59fe8c5e604256d8eb..f5a1d28c35fbd09703b6ca2a728fa3f40387d53e 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -1258,7 +1258,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
 
   action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
     if (send_evictions) {
-      DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+      DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
       sequencer.evictionCallback(address);
     }
   }

diff --git a/src/mem/ruby/common/Address.cc b/src/mem/ruby/common/Address.cc
index d9fadf12876ced31e53578861d942bb4aeb6c576..f0aa71ac6aba47fd708bea25b25a0f7901374d9a 100644 (file)
--- a/src/mem/ruby/common/Address.cc
+++ b/src/mem/ruby/common/Address.cc
@@ -121,3 +121,13 @@ makeNextStrideAddress(Addr addr, int stride)
     return maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
         + RubySystem::getBlockSizeBytes() * stride;
 }
+
+std::string
+printAddress(Addr addr)
+{
+    std::stringstream out;
+    out << "[" << std::hex << "0x" << addr << "," << " line 0x"
+       << maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
+       << std::dec << "]";
+    return out.str();
+}

diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh
index 6210baa5c3e42ef7d1f7876f906bc47c6f0d7090..90955447bc4fe949eba78a0bfdf7b084089dffc7 100644 (file)
--- a/src/mem/ruby/common/Address.hh
+++ b/src/mem/ruby/common/Address.hh
@@ -47,5 +47,6 @@ Addr shiftLowOrderBits(Addr addr, unsigned int number);
 Addr getOffset(Addr addr);
 Addr makeLineAddress(Addr addr);
 Addr makeNextStrideAddress(Addr addr, int stride);
+std::string printAddress(Addr addr);
 
 #endif // __MEM_RUBY_COMMON_ADDRESS_HH__

diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
index 35850f61eebf34c2de187e0ffe2495a951b87e27..72c03457ab16339562d8f4cd285407b5cc25141b 100644 (file)
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -281,7 +281,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
 void
 MessageBuffer::reanalyzeMessages(Addr addr, Tick current_time)
 {
-    DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
+    DPRINTF(RubyQueue, "ReanalyzeMessages %#x\n", addr);
     assert(m_stall_msg_map.count(addr) > 0);
 
     //
@@ -315,7 +315,7 @@ MessageBuffer::reanalyzeAllMessages(Tick current_time)
 void
 MessageBuffer::stallMessage(Addr addr, Tick current_time)
 {
-    DPRINTF(RubyQueue, "Stalling due to %s\n", addr);
+    DPRINTF(RubyQueue, "Stalling due to %#x\n", addr);
     assert(isReady(current_time));
     assert(getOffset(addr) == 0);
     MsgPtr message = m_prio_heap.front();

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index 416aea73be12dae96a492f2654a10e24d5ca8205..00dfc6c640c7745358b5045aa6c5fd4da92e4348 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -55,21 +55,21 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
 void
 AbstractCacheEntry::setLocked(int context)
 {
-    DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", m_Address, context);
+    DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", m_Address, context);
     m_locked = context;
 }
 
 void
 AbstractCacheEntry::clearLocked()
 {
-    DPRINTF(RubyCache, "Clear Lock for addr: %x\n", m_Address);
+    DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", m_Address);
     m_locked = -1;
 }
 
 bool
 AbstractCacheEntry::isLocked(int context) const
 {
-    DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
+    DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
             m_Address, m_locked, context);
     return m_locked == context;
 }

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index be6438711a7b1192286afa080d0c094f27ad9fa3..37078178029a689d4d99dfae777efc1db0c20b62 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -97,7 +97,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
         msgVec->resize(m_in_ports, NULL);
         m_waiting_buffers[addr] = msgVec;
     }
-    DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
+    DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
             addr);
     assert(m_in_ports > m_cur_in_port);
     (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;

diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc
index 350508671dae55d1142015b72d873ccdce627ccd..c4c5b2fafc5b20fa346592fe9ca2abfde35f19f1 100644 (file)
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -36,10 +36,10 @@ void
 RubyRequest::print(ostream& out) const
 {
   out << "[RubyRequest: ";
-  out << "LineAddress = " << m_LineAddress << " ";
-  out << "PhysicalAddress = " << m_PhysicalAddress << " ";
+  out << hex << "LineAddress = 0x" << m_LineAddress << dec << " ";
+  out << hex << "PhysicalAddress = 0x" << m_PhysicalAddress << dec << " ";
   out << "Type = " << m_Type << " ";
-  out << "ProgramCounter = " << m_ProgramCounter << " ";
+  out << hex << "ProgramCounter = 0x" << m_ProgramCounter << dec << " ";
   out << "AccessMode = " << m_AccessMode << " ";
   out << "Size = " << m_Size << " ";
   out << "Prefetch = " << m_Prefetch << " ";

diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index a269d4f5bc00db6922b6e0d50e427ad94930d926..b0e54ec9972ffd1996cd0643f46c1c57732ccfd6 100644 (file)
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -163,7 +163,7 @@ CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
                             DataBlock*& data_ptr)
 {
     assert(address == makeLineAddress(address));
-    DPRINTF(RubyCache, "address: %s\n", address);
+    DPRINTF(RubyCache, "address: %#x\n", address);
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     if (loc != -1) {
@@ -190,7 +190,7 @@ CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
                              DataBlock*& data_ptr)
 {
     assert(address == makeLineAddress(address));
-    DPRINTF(RubyCache, "address: %s\n", address);
+    DPRINTF(RubyCache, "address: %#x\n", address);
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
 
@@ -218,10 +218,10 @@ CacheMemory::isTagPresent(Addr address) const
 
     if (loc == -1) {
         // We didn't find the tag
-        DPRINTF(RubyCache, "No tag match for address: %s\n", address);
+        DPRINTF(RubyCache, "No tag match for address: %#x\n", address);
         return false;
     }
-    DPRINTF(RubyCache, "address: %s found\n", address);
+    DPRINTF(RubyCache, "address: %#x found\n", address);
     return true;
 }
 
@@ -256,7 +256,7 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch)
     assert(address == makeLineAddress(address));
     assert(!isTagPresent(address));
     assert(cacheAvail(address));
-    DPRINTF(RubyCache, "address: %s\n", address);
+    DPRINTF(RubyCache, "address: %#x\n", address);
 
     // Find the first open slot
     int64_t cacheSet = addressToCacheSet(address);
@@ -288,7 +288,7 @@ CacheMemory::deallocate(Addr address)
 {
     assert(address == makeLineAddress(address));
     assert(isTagPresent(address));
-    DPRINTF(RubyCache, "address: %s\n", address);
+    DPRINTF(RubyCache, "address: %#x\n", address);
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     if (loc != -1) {
@@ -417,7 +417,7 @@ CacheMemory::printData(ostream& out) const
 void
 CacheMemory::setLocked(Addr address, int context)
 {
-    DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
+    DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", address, context);
     assert(address == makeLineAddress(address));
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
@@ -428,7 +428,7 @@ CacheMemory::setLocked(Addr address, int context)
 void
 CacheMemory::clearLocked(Addr address)
 {
-    DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
+    DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", address);
     assert(address == makeLineAddress(address));
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
@@ -443,7 +443,7 @@ CacheMemory::isLocked(Addr address, int context)
     int64_t cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
-    DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
+    DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
             address, m_cache[cacheSet][loc]->m_locked, context);
     return m_cache[cacheSet][loc]->isLocked(context);
 }
@@ -582,7 +582,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
         if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
         else {
             DPRINTF(RubyResourceStalls,
-                    "Tag array stall on addr %s in set %d\n",
+                    "Tag array stall on addr %#x in set %d\n",
                     addr, addressToCacheSet(addr));
             numTagArrayStalls++;
             return false;
@@ -591,7 +591,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
         if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
         else {
             DPRINTF(RubyResourceStalls,
-                    "Data array stall on addr %s in set %d\n",
+                    "Data array stall on addr %#x in set %d\n",
                     addr, addressToCacheSet(addr));
             numDataArrayStalls++;
             return false;

diff --git a/src/mem/ruby/structures/DirectoryMemory.cc b/src/mem/ruby/structures/DirectoryMemory.cc
index 267c07174b040ae0d14f61bdedfb44b67f52da61..8aad6f4faa04b5e65645303bccf3ac7e16d2692f 100644 (file)
--- a/src/mem/ruby/structures/DirectoryMemory.cc
+++ b/src/mem/ruby/structures/DirectoryMemory.cc
@@ -114,7 +114,7 @@ AbstractEntry*
 DirectoryMemory::lookup(Addr address)
 {
     assert(isPresent(address));
-    DPRINTF(RubyCache, "Looking up address: %s\n", address);
+    DPRINTF(RubyCache, "Looking up address: %#x\n", address);
 
     uint64_t idx = mapAddressToLocalIdx(address);
     assert(idx < m_num_entries);
@@ -126,7 +126,7 @@ DirectoryMemory::allocate(Addr address, AbstractEntry *entry)
 {
     assert(isPresent(address));
     uint64_t idx;
-    DPRINTF(RubyCache, "Looking up address: %s\n", address);
+    DPRINTF(RubyCache, "Looking up address: %#x\n", address);
 
     idx = mapAddressToLocalIdx(address);
     assert(idx < m_num_entries);

diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc
index d12665ae9f391155d22e418cd95e2509caf511bc..ce6d36c048f26295c4f7fae5fbda8114a80f6811 100644 (file)
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -135,7 +135,7 @@ Prefetcher::regStats()
 void
 Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
 {
-    DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address);
+    DPRINTF(RubyPrefetcher, "Observed miss for %#x\n", address);
     Addr line_addr = makeLineAddress(address);
     numMissObserved++;
 
@@ -204,7 +204,7 @@ void
 Prefetcher::observePfMiss(Addr address)
 {
     numPartialHits++;
-    DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address);
+    DPRINTF(RubyPrefetcher, "Observed partial hit for %#x\n", address);
     issueNextPrefetch(address, NULL);
 }
 
@@ -212,7 +212,7 @@ void
 Prefetcher::observePfHit(Addr address)
 {
     numHits++;
-    DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address);
+    DPRINTF(RubyPrefetcher, "Observed hit for %#x\n", address);
     issueNextPrefetch(address, NULL);
 }
 
@@ -250,7 +250,7 @@ Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
     // launch next prefetch
     stream->m_address = line_addr;
     stream->m_use_time = m_controller->curCycle();
-    DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
+    DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
     m_controller->enqueuePrefetch(line_addr, stream->m_type);
 }
 
@@ -314,7 +314,7 @@ Prefetcher::initializeStream(Addr address, int stride,
 
         // launch prefetch
         numPrefetchRequested++;
-        DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
+        DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
         m_controller->enqueuePrefetch(line_addr, m_array[index].m_type);
     }
 

diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc
index 454775178ada3d856e002ea6dbd1717e34cf91e1..3ad3911cb5e63f565116a45e176104863f399f91 100644 (file)
--- a/src/mem/ruby/system/RubySystem.cc
+++ b/src/mem/ruby/system/RubySystem.cc
@@ -404,7 +404,7 @@ RubySystem::functionalRead(PacketPtr pkt)
     AccessPermission access_perm = AccessPermission_NotPresent;
     int num_controllers = m_abs_cntrl_vec.size();
 
-    DPRINTF(RubySystem, "Functional Read request for %s\n", address);
+    DPRINTF(RubySystem, "Functional Read request for %#x\n", address);
 
     unsigned int num_ro = 0;
     unsigned int num_rw = 0;
@@ -486,7 +486,7 @@ RubySystem::functionalWrite(PacketPtr pkt)
     AccessPermission access_perm = AccessPermission_NotPresent;
     int num_controllers = m_abs_cntrl_vec.size();
 
-    DPRINTF(RubySystem, "Functional Write request for %s\n", addr);
+    DPRINTF(RubySystem, "Functional Write request for %#x\n", addr);
 
     uint32_t M5_VAR_USED num_functional_writes = 0;
 

diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 815e270b6022a2c2f7960290c32db9e4017b64ff..aa4ac742a391f8ebff31732213ab0f164c13fc29 100644 (file)
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -443,7 +443,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
     DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
              curTick(), m_version, "Seq",
              llscSuccess ? "Done" : "SC_Failed", "", "",
-             request_address, total_latency);
+             printAddress(request_address), total_latency);
 
     // update the data unless it is a non-data-carrying flush
     if (RubySystem::getWarmupEnabled()) {
@@ -610,7 +610,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
 
     DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
             curTick(), m_version, "Seq", "Begin", "", "",
-            msg->getPhysicalAddress(),
+            printAddress(msg->getPhysicalAddress()),
             RubyRequestType_to_string(secondary_type));
 
     // The Sequencer currently assesses instruction and data cache hit latency

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 9eaa40d777a188442d30b38203d5ce142e833c0f..a530307ee1516a7f6c84d5bffdc8d9c3d1269cba 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1155,7 +1155,7 @@ ${ident}_Controller::doTransition(${ident}_Event event,
         code('''
 ${ident}_State next_state = state;
 
-DPRINTF(RubyGenerated, "%s, Time: %lld, state: %s, event: %s, addr: %s\\n",
+DPRINTF(RubyGenerated, "%s, Time: %lld, state: %s, event: %s, addr: %#x\\n",
         *this, curCycle(), ${ident}_State_to_string(state),
         ${ident}_Event_to_string(event), addr);
 
@@ -1184,7 +1184,7 @@ if (result == TransitionResult_Valid) {
              ${ident}_Event_to_string(event),
              ${ident}_State_to_string(state),
              ${ident}_State_to_string(next_state),
-             addr, GET_TRANSITION_COMMENT());
+             printAddress(addr), GET_TRANSITION_COMMENT());
 
     CLEAR_TRANSITION_COMMENT();
 ''')
@@ -1208,7 +1208,7 @@ if (result == TransitionResult_Valid) {
              ${ident}_Event_to_string(event),
              ${ident}_State_to_string(state),
              ${ident}_State_to_string(next_state),
-             addr, "Resource Stall");
+             printAddress(addr), "Resource Stall");
 } else if (result == TransitionResult_ProtocolStall) {
     DPRINTF(RubyGenerated, "stalling\\n");
     DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
@@ -1216,7 +1216,7 @@ if (result == TransitionResult_Valid) {
              ${ident}_Event_to_string(event),
              ${ident}_State_to_string(state),
              ${ident}_State_to_string(next_state),
-             addr, "Protocol Stall");
+             printAddress(addr), "Protocol Stall");
 }
 
 return result;

diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 6234f4f7f08d5455352b6c45cb361f5e961d007d..a3223b3ac37d5e5c9706bbc95148530c5339a499 100644 (file)
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -412,7 +412,11 @@ ${{self.c_ident}}::print(ostream& out) const
         # For each field
         code.indent()
         for dm in self.data_members.values():
-            code('out << "${{dm.ident}} = " << m_${{dm.ident}} << " ";''')
+            if dm.type.c_ident == "Addr":
+                code('''
+out << "${{dm.ident}} = " << printAddress(m_${{dm.ident}}) << " ";''')
+            else:
+                code('out << "${{dm.ident}} = " << m_${{dm.ident}} << " ";''')
 
         code.dedent()