mem-cache: alias to mem::getMasterPort in TLB class

TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 46056d07b045440161949f249d652dda3b12b2a2..ed7e680396e8d8437b5f28f959c7312545721a75 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1244,7 +1244,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
 }
 
 BaseMasterPort*
-TLB::getMasterPort()
+TLB::getTableWalkerMasterPort()
 {
     return &stage2Mmu->getPort();
 }

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 637240abb90c7c962c3485fb3e1644cd402ebe13..8ca176a823fa285780aeab95e4f981ac6fe0c2a8 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -401,7 +401,7 @@ class TLB : public BaseTLB
      *
      * @return A pointer to the walker master port
      */
-    BaseMasterPort* getMasterPort() override;
+    BaseMasterPort* getTableWalkerMasterPort() override;
 
     // Caching misc register values here.
     // Writing to misc registers needs to invalidate them.

diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 91f8f867bed40c8c43128bffa391550d491ecd4a..7865d8abee264992bcccd4c4cf8a6fd24732060d 100644 (file)
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -58,6 +58,7 @@ class BaseTLB : public MemObject
     {}
 
   public:
+
     enum Mode { Read, Write, Execute };
 
     class Translation
@@ -138,7 +139,7 @@ class BaseTLB : public MemObject
      *
      * @return A pointer to the walker master port or NULL if not present
      */
-    virtual BaseMasterPort* getMasterPort() { return NULL; }
+    virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; }
 
     void memInvalidate() { flushAll(); }
 };

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 829ebce0092fba89088799d3c4ded56616cb8910..59fd3f00af7ffb2a246f110f69af631cb65c3e9d 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -512,7 +512,7 @@ TLB::unserialize(CheckpointIn &cp)
 }
 
 BaseMasterPort *
-TLB::getMasterPort()
+TLB::getTableWalkerMasterPort()
 {
     return &walker->getMasterPort("port");
 }

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 827ab81665236af2795884c7b3afff83c8e0a4bf..8894a1e4ac4c7ef1ceed2d1495240ca8cd50eca8 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -165,7 +165,7 @@ namespace X86ISA
          *
          * @return A pointer to the walker master port
          */
-        BaseMasterPort *getMasterPort() override;
+        BaseMasterPort *getTableWalkerMasterPort() override;
     };
 }
 

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 30f6baf20cc51d101e1ad01858fd93e1cbc81e02..09de64646a4a9d9318a865a0c8fadcf74275f382 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -621,10 +621,14 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
             ThreadContext::compare(oldTC, newTC);
         */
 
-        BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
-        BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
-        BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
-        BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
+        BaseMasterPort *old_itb_port =
+            oldTC->getITBPtr()->getTableWalkerMasterPort();
+        BaseMasterPort *old_dtb_port =
+            oldTC->getDTBPtr()->getTableWalkerMasterPort();
+        BaseMasterPort *new_itb_port =
+            newTC->getITBPtr()->getTableWalkerMasterPort();
+        BaseMasterPort *new_dtb_port =
+            newTC->getDTBPtr()->getTableWalkerMasterPort();
 
         // Move over any table walker ports if they exist
         if (new_itb_port) {
@@ -652,13 +656,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
         CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
         if (oldChecker && newChecker) {
             BaseMasterPort *old_checker_itb_port =
-                oldChecker->getITBPtr()->getMasterPort();
+                oldChecker->getITBPtr()->getTableWalkerMasterPort();
             BaseMasterPort *old_checker_dtb_port =
-                oldChecker->getDTBPtr()->getMasterPort();
+                oldChecker->getDTBPtr()->getTableWalkerMasterPort();
             BaseMasterPort *new_checker_itb_port =
-                newChecker->getITBPtr()->getMasterPort();
+                newChecker->getITBPtr()->getTableWalkerMasterPort();
             BaseMasterPort *new_checker_dtb_port =
-                newChecker->getDTBPtr()->getMasterPort();
+                newChecker->getDTBPtr()->getTableWalkerMasterPort();
 
             newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
             newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());