radv/gfx10: set cache control registers

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 57e143ece46eca22ced8471f134f936ed4c66b8d..a7c9dd90093f94227a2e0978c36a5fc29902df2c 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -299,6 +299,27 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                                  S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
        }
 
+       if (physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
+                                      S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                                      S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                                      S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                                      S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+                                      S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+                                      S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+                                      S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
+
+               radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
+                                      S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                                      S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                                      S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                                      S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+                                      S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                                      S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                                      S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
+                                      S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
+       }
+
        if (physical_device->rad_info.chip_class >= GFX8) {
                uint32_t vgt_tess_distribution;