parse_xaiger to not take box_lookup

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3e40562b732b3b3cbddbbdaa6d3fe224a6042fb4..be900f0e78fa1ba1a6e61248aeb3aa49398ea0d4 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -414,14 +414,25 @@ struct XAigerWriter
                                                auto w = box_module->wire(port_name);
                                                log_assert(w);
                                                if (w->get_bool_attribute("\\abc9_carry")) {
-                                                       if (w->port_input)
+                                                       if (w->port_input) {
+                                                               if (carry_in != IdString())
+                                                                       log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
                                                                carry_in = port_name;
-                                                       if (w->port_output)
+                                                       }
+                                                       if (w->port_output) {
+                                                               if (carry_out != IdString())
+                                                                       log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
                                                                carry_out = port_name;
+                                                       }
                                                }
                                                else
                                                        r.first->second.push_back(port_name);
                                        }
+
+                                       if (carry_in != IdString() && carry_out == IdString())
+                                               log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+                                       if (carry_in == IdString() && carry_out != IdString())
+                                               log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
                                        if (carry_in != IdString()) {
                                                log_assert(carry_out != IdString());
                                                r.first->second.push_back(carry_in);

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 3d00aee1032d2d02b399ddef683ff315749805ce..f030933ec9871749671ee002ba6c3282bd8c1fdd 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -340,7 +340,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
        return wire;
 }
 
-void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
+void AigerReader::parse_xaiger()
 {
        std::string header;
        f >> header;
@@ -382,6 +382,21 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
        if (f.peek() == '\n')
                f.get();
 
+       dict<int,IdString> box_lookup;
+       for (auto m : design->modules()) {
+               auto it = m->attributes.find(ID(abc9_box_id));
+               if (it == m->attributes.end())
+                       continue;
+               if (m->name.begins_with("$paramod"))
+                       continue;
+               auto id = it->second.as_int();
+               auto r = box_lookup.insert(std::make_pair(id, m->name));
+               if (!r.second)
+                       log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+                                       log_id(m), id, log_id(r.first->second));
+               log_assert(r.second);
+       }
+
        // Parse footer (symbol table, comments, etc.)
        std::string s;
        for (int c = f.get(); c != EOF; c = f.get()) {
@@ -456,7 +471,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
                                uint32_t boxUniqueId = parse_xaiger_literal(f);
                                log_assert(boxUniqueId > 0);
                                uint32_t oldBoxNum = parse_xaiger_literal(f);
-                               RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId));
+                               RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
                                boxes.emplace_back(cell);
                        }
                }
@@ -720,25 +735,12 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-       pool<IdString> seen_boxes;
-       pool<IdString> flops;
        dict<IdString, std::vector<IdString>> box_ports;
        unsigned ci_count = 0, co_count = 0, flop_count = 0;
        for (auto cell : boxes) {
                RTLIL::Module* box_module = design->module(cell->type);
                log_assert(box_module);
 
-               bool is_flop = false;
-               if (seen_boxes.insert(cell->type).second) {
-                       if (box_module->attributes.count("\\abc9_flop")) {
-                               log_assert(flop_count < flopNum);
-                               flops.insert(cell->type);
-                               is_flop = true;
-                       }
-               }
-               else
-                       is_flop = flops.count(cell->type);
-
                auto r = box_ports.insert(cell->type);
                if (r.second) {
                        // Make carry in the last PI, and carry out the last PO
@@ -788,7 +790,7 @@ void AigerReader::post_process()
                        cell->setPort(port_name, rhs);
                }
 
-               if (is_flop) {
+               if (box_module->attributes.count("\\abc9_flop")) {
                        log_assert(co_count < outputs.size());
                        Wire *wire = outputs[co_count++];
                        log_assert(wire);
@@ -900,7 +902,7 @@ void AigerReader::post_process()
                                        wire->attributes["\\init"] = init;
                        }
                        else if (type == "box") {
-                               RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable));
+                               RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
                                if (cell) { // ABC could have optimised this box away
                                        module->rename(cell, escaped_s);
                                        for (const auto &i : cell->connections()) {

diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 583c9d0f99903376fd292c17ec68ed1123728d46..de3c3efbc9b10008335d68df5877b864a972c7ea 100644 (file)
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -47,7 +47,7 @@ struct AigerReader
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
     void parse_aiger();
-    void parse_xaiger(const dict<int,IdString> &box_lookup);
+    void parse_xaiger();
     void parse_aiger_ascii();
     void parse_aiger_binary();
     void post_process();

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1ae1637bd826933f2c6fe48e1db4bd655eb121d3..3c53a522382d84588c6ec9beab07b2555dc3a783 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -251,7 +251,7 @@ struct abc9_output_filter
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
                bool cleanup, vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
                const std::vector<RTLIL::Cell*> &/*cells*/, bool show_tempdir, std::string box_file, std::string lut_file,
-               std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs
+               std::string wire_delay, bool nomfs
 )
 {
        map_autoidx = autoidx++;
@@ -348,7 +348,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                log_assert(!design->module(ID($__abc9__)));
                {
                        AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-                       reader.parse_xaiger(box_lookup);
+                       reader.parse_xaiger();
                }
                ifs.close();
                Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
@@ -400,7 +400,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                log_assert(!design->module(ID($__abc9__)));
 
                AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-               reader.parse_xaiger(box_lookup);
+               reader.parse_xaiger();
                ifs.close();
 
 #if 0
@@ -967,45 +967,6 @@ struct Abc9Pass : public Pass {
                if (!box_file.empty() && !is_absolute_path(box_file) && box_file[0] != '+')
                    box_file = std::string(pwd) + "/" + box_file;
 
-               dict<int,IdString> box_lookup;
-               for (auto m : design->modules()) {
-                       auto it = m->attributes.find(ID(abc9_box_id));
-                       if (it == m->attributes.end())
-                               continue;
-                       if (m->name.begins_with("$paramod"))
-                               continue;
-                       auto id = it->second.as_int();
-                       auto r = box_lookup.insert(std::make_pair(id, m->name));
-                       if (!r.second)
-                               log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-                                               log_id(m), id, log_id(r.first->second));
-                       log_assert(r.second);
-
-                       RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-                       for (auto p : m->ports) {
-                               auto w = m->wire(p);
-                               log_assert(w);
-                               if (w->attributes.count(ID(abc9_carry))) {
-                                       if (w->port_input) {
-                                               if (carry_in)
-                                                       log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-                                               carry_in = w;
-                                       }
-                                       else if (w->port_output) {
-                                               if (carry_out)
-                                                       log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-                                               carry_out = w;
-                                       }
-                               }
-                       }
-                       if (carry_in || carry_out) {
-                               if (carry_in && !carry_out)
-                                       log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-                               if (!carry_in && carry_out)
-                                       log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-                       }
-               }
-
                SigMap assign_map;
                CellTypes ct(design);
                for (auto module : design->selected_modules())
@@ -1056,7 +1017,7 @@ struct Abc9Pass : public Pass {
                        design->selected_active_module = module->name.str();
                        abc9_module(design, module, script_file, exe_file, cleanup, lut_costs,
                                        delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
-                                       box_file, lut_file, wire_delay, box_lookup, nomfs);
+                                       box_file, lut_file, wire_delay, nomfs);
                        design->selected_active_module.clear();
                }