Simplify

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 11064e072cc574a1ec63296309be2e1e49654686..b387ca0a2f3fd969b78d79c934d665df96ad0760 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -92,16 +92,12 @@ match ffFJKG
 endmatch
 
 code sigH sigO clock clock_pol
-       sigO = sigH;
-
        if (ffFJKG) {
                sigH = port(ffFJKG, \Q);
                for (auto b : sigH)
                        if (b.wire->get_bool_attribute(\keep))
                                reject;
 
-               sigO = sigH;
-
                SigBit c = port(ffFJKG, \CLK).as_bit();
                bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 
@@ -111,6 +107,8 @@ code sigH sigO clock clock_pol
                clock = c;
                clock_pol = cp;
        }
+
+       sigO = sigH;
 endcode
 
 match addA