svga: fix depth and coverage mask output declaration
authorCharmaine Lee <charmainel@vmware.com>
Mon, 27 Nov 2017 21:24:26 +0000 (13:24 -0800)
committerBrian Paul <brianp@vmware.com>
Mon, 10 Sep 2018 19:07:30 +0000 (13:07 -0600)
Set the component mask to zero for both registers.

Reviewed-by: Brian Paul <brianp@vmware.com>
src/gallium/drivers/svga/svga_tgsi_vgpu10.c

index 85074187155d45384393531c2bd0369575b790bc..abfbd523605a979ae274bbaeffeddc8a6781c453 100644 (file)
@@ -2122,7 +2122,9 @@ emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
                       unsigned index, unsigned size)
 {
    assert(opcode0.opcodeType);
-   assert(operand0.mask);
+   assert(operand0.mask ||
+          (operand0.operandType == VGPU10_OPERAND_TYPE_OUTPUT_DEPTH) ||
+          (operand0.operandType == VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK));
 
    begin_emit_instruction(emit);
    emit_dword(emit, opcode0.value);
@@ -2293,7 +2295,7 @@ emit_fragdepth_output_declaration(struct svga_shader_emitter_v10 *emit)
    operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
    operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
    operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
-   operand0.mask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
+   operand0.mask = 0;
 
    emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
 }
@@ -2318,7 +2320,7 @@ emit_samplemask_output_declaration(struct svga_shader_emitter_v10 *emit)
    operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK;
    operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
    operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
-   operand0.mask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
+   operand0.mask = 0;
 
    emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
 }