fix BRAM width and init

diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v
index c60330b4faf665433813138980834fa98c508a68..6c5e4733ad42ad0a90df8d1160fbd202a8eff892 100644 (file)
--- a/techlibs/gowin/brams_map.v
+++ b/techlibs/gowin/brams_map.v
@@ -8,23 +8,24 @@
 module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
        parameter CFG_ABITS = 10;
        parameter CFG_DBITS = 16;
-       parameter CFG_ENABLE_A = 3;
-
-        parameter [16383:0] INIT = 16384'hx;
-        parameter CLKPOL2 = 1;
-        parameter CLKPOL3 = 1;
+       parameter CFG_ENABLE_A = 1;
+       parameter [16383:0] INIT = 16384'hx;
+       parameter CLKPOL2 = 1;
+       parameter CLKPOL3 = 1;
 
        input CLK2;
        input CLK3;
 
        input [CFG_ABITS-1:0] A1ADDR;
        input [CFG_DBITS-1:0] A1DATA;   
-        input [CFG_ENABLE_A-1:0] A1EN;
+       input [CFG_ENABLE_A-1:0] A1EN;
 
        input [CFG_ABITS-1:0] B1ADDR;
        output [CFG_DBITS-1:0] B1DATA;
        input B1EN;
 
+       wire [31-CFG_DBITS:0] open;
+
        
        generate if (CFG_DBITS == 1) begin
                SDP   #(
@@ -39,7 +40,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
                        .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
                        .WREB(1'b0),   .CEB(B1EN),
                        .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                       .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+                       .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+                       .DO({open, B1DATA}),
+                       .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+                       .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
                );
        end else if (CFG_DBITS == 2) begin
                SDP    #(
@@ -54,7 +58,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
                        .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
                        .WREB(1'b0),   .CEB(B1EN),
                        .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+                       .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+                       .DO({open, B1DATA}),
+                       .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+                       .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
                );
        end else if (CFG_DBITS <= 4) begin
                SDP    #(
@@ -69,7 +76,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
                        .WREA(A1EN),   .OCE(1'b0),
                        .WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
                        .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+                       .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+                       .DO({open, B1DATA}),
+                       .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+                       .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
                );
        end else if (CFG_DBITS <= 8) begin
                SDP    #(
@@ -84,7 +94,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
                        .WREA(A1EN),   .OCE(1'b0), .CEA(1'b1),
                        .WREB(1'b0),   .CEB(B1EN),
                        .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+                       .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+                       .DO({open, B1DATA}),
+                       .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
+                       .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
                );
        end else if (CFG_DBITS <= 16) begin
                SDP    #(
@@ -99,7 +112,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
                        .WREA(A1EN),   .OCE(1'b0),
                        .WREB(1'b0),   .CEB(B1EN), .CEA(1'b1),
                        .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
-                        .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR)
+                       .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
+                       .DO({open, B1DATA}),
+                       .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}),
+                       .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
                );
        end else begin
                wire TECHMAP_FAIL = 1'b1;

diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index cfddcec1234f47c54088e21dfeeb8254458700d9..f67627e8a03726a0e32a53b9f638cae9dcf1ea27 100644 (file)
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -211,7 +211,7 @@ struct SynthGowinPass : public ScriptPass
                if (check_label("map_cells"))
                {
                        run("techmap -map +/gowin/cells_map.v");
-                       run("setundef -undriven -zero");
+                       run("setundef -undriven -params -zero");
                        run("hilomap -singleton -hicell VCC V -locell GND G");
                        run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
                        run("dffinit  -ff DFF Q INIT");