arch-riscv: Fix disassembling of all register instructions

How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.

This patch fixes the problem.

Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index e6c2b67aedfe304f2125a3fe7dd65bebe13dd65e..9a9aa9da444fe201bc5c7224a051f4c34c2ebc12 100644 (file)
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -48,9 +48,9 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     stringstream ss;
     ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
         registerName(_srcRegIdx[0]);
-    if (_srcRegIdx[1].index() != 0)
+    if (_numSrcRegs >= 2)
         ss << ", " << registerName(_srcRegIdx[1]);
-    if (_srcRegIdx[2].index() != 0)
+    if (_numSrcRegs >= 3)
         ss << ", " << registerName(_srcRegIdx[2]);
     return ss.str();
 }