-;; ColdFire V1, V2 and V3 DFA description.
+;; ColdFire V1, V2, V3 and V4/V4e DFA description.
;; Copyright (C) 2007 Free Software Foundation, Inc.
-;; Contributed by CodeSourcery Inc.
+;; Contributed by CodeSourcery Inc., www.codesourcery.com
;;
;; This file is part of GCC.
;;
;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
;; Boston, MA 02110-1301, USA.
-;; Intruction types recognized by DFA.
-;; This attribute correspond to type1 attribute with the exceptions below.
-;; omove - optimized move. All explicit loads on cfv1 and long explicit
-;; loads on cfv2 execute one cycle faster then they should.
-;; Supposedly, that is due to combined instruction decoding
-;; and address generation phases.
-;; ??? To let genattrtab live, implement this attribute in C.
-(define_attr "type2"
- "alu, alu_reg, bcc, bra, call, jmp, lea, mul_l, mul_w, omove, pea,
- rts, unlk, unknown"
- (symbol_ref "m68k_sched_attr_type2 (insn)"))
-
;; Instruction Buffer
-(define_automaton "cf_ib")
+(define_automaton "cfv123_ib")
;; These pseudo units are used to model instruction buffer of ColdFire cores.
;; Instruction of size N can be issued only when cf_ib_wN is available.
-(define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cf_ib")
+(define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cfv123_ib")
;; Instruction occupies 1 word in the instruction buffer.
(define_reservation "cf_ib1" "cf_ib_w1")
"cf_ib_w3|cf_ib_w2|cf_ib_w1")
;; Operand Execution Pipeline
-(define_automaton "cf_oep")
+(define_automaton "cfv123_oep")
-(define_cpu_unit "cf_dsoc, cf_agex" "cf_oep")
+(define_cpu_unit "cf_dsoc,cf_agex" "cfv123_oep")
;; A memory unit that is reffered to as 'certain hardware resources' in
;; ColdFire reference manuals. This unit remains occupied for two cycles
;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
;; two consecutive stores.
-(define_automaton "cf_chr")
+(define_automaton "cfv123_chr")
-(define_cpu_unit "cf_chr" "cf_chr")
+(define_cpu_unit "cf_chr" "cfv123_chr")
;; Memory bus
-(define_automaton "cf_mem")
+(define_automaton "cfv123_mem")
;; When memory bus is subscribed, that implies that instruction buffer won't
;; get its portion this cycle. To model that we query if cf_mem unit is
;; subscribed and adjust number of prefetched instruction words accordingly.
;;
-(define_query_cpu_unit "cf_mem1, cf_mem2" "cf_mem")
+(define_query_cpu_unit "cf_mem1, cf_mem2" "cfv123_mem")
(define_reservation "cf_mem" "cf_mem1+cf_mem2")
+(define_automaton "cf_mac")
+
+(define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4"
+ "cf_mac")
+
+(define_automaton "cfv123_guess")
+
+(define_query_cpu_unit "cfv123_guess" "cfv123_guess")
+
;; Register to register move.
;; Takes 1 cycle.
(define_reservation "cfv123_alu_00"
(define_reservation "cfv3_mul_w_i0"
"cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
-(define_automaton "cf_mac")
-
-(define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4"
- "cf_mac")
-
;; Long multiplication with mac.
;; Takes 5 cycles.
(define_reservation "cfv123_mac_l_00"
(define_insn_reservation "cfv123_alu_00_1" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "alu,alu_reg,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "00"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_alu_00")
(define_insn_reservation "cfv123_alu_00_2" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "alu,alu_reg,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "00"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_alu_00")
(define_insn_reservation "cfv123_alu_00_3" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "alu,alu_reg,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "00"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_alu_00")
-(define_insn_reservation "cfv12_alu_10_1" 3
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_alu_10_1" 3
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_alu_10")
-(define_insn_reservation "cfv12_alu_10_2" 3
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_alu_10_2" 3
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_alu_10")
-(define_insn_reservation "cfv12_alu_10_3" 3
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_alu_10_3" 3
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_10")
-(define_insn_reservation "cfv12_omove_10_1" 2
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_omove_10_1" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_omove_10")
-(define_insn_reservation "cfv12_omove_10_2" 2
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_omove_10_2" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_omove_10")
-(define_insn_reservation "cfv12_omove_10_3" 2
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+(define_insn_reservation "cfv1_omove_10_3" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_omove_10")
+
+(define_insn_reservation "cfv2_alu_10_1" 3
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv12_alu_10")
+
+(define_insn_reservation "cfv2_alu_10_2" 3
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv12_alu_10")
+
+(define_insn_reservation "cfv2_alu_10_3" 3
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_alu_10")
+
+(define_insn_reservation "cfv2_omove_10_1" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv12_omove_10")
+
+(define_insn_reservation "cfv2_omove_10_2" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv12_omove_10")
+
+(define_insn_reservation "cfv2_omove_10_3" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_omove_10")
(define_insn_reservation "cfv3_alu_10_1" 4
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_alu_10")
(define_insn_reservation "cfv3_alu_10_2" 4
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_alu_10")
(define_insn_reservation "cfv3_alu_10_3" 4
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_10")
(define_insn_reservation "cfv3_omove_10_1" 3
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_omove_10")
(define_insn_reservation "cfv3_omove_10_2" 3
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_omove_10")
(define_insn_reservation "cfv3_omove_10_3" 3
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "10"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_omove_10")
-(define_insn_reservation "cfv12_alu_i0_2" 4
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+(define_insn_reservation "cfv1_alu_i0_2" 4
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_alu_i0")
-(define_insn_reservation "cfv12_alu_i0_3" 4
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+(define_insn_reservation "cfv1_alu_i0_3" 4
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_i0")
-(define_insn_reservation "cfv12_omove_i0_2" 3
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+(define_insn_reservation "cfv1_omove_i0_2" 3
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_omove_i0")
-(define_insn_reservation "cfv12_omove_i0_3" 3
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+(define_insn_reservation "cfv1_omove_i0_3" 3
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_omove_i0")
+
+(define_insn_reservation "cfv2_alu_i0_2" 4
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_alu_i0")
+
+(define_insn_reservation "cfv2_alu_i0_3" 4
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_alu_i0")
+
+(define_insn_reservation "cfv2_omove_i0_2" 3
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_omove_i0")
+
+(define_insn_reservation "cfv2_omove_i0_3" 3
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_omove_i0")
(define_insn_reservation "cfv3_alu_i0_2" 5
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_alu_i0")
(define_insn_reservation "cfv3_alu_i0_3" 5
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_i0")
(define_insn_reservation "cfv3_omove_i0_2" 4
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_omove_i0")
(define_insn_reservation "cfv3_omove_i0_3" 4
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_omove_i0")
-(define_insn_reservation "cfv12_alu_01_1" 0
+(define_insn_reservation "cfv12_alu_01_1" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_alu_01")
-(define_insn_reservation "cfv12_alu_01_2" 0
+(define_insn_reservation "cfv12_alu_01_2" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_alu_01")
-(define_insn_reservation "cfv12_alu_01_3" 0
+(define_insn_reservation "cfv12_alu_01_3" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_01")
-(define_insn_reservation "cfv3_alu_01_1" 0
+(define_insn_reservation "cfv3_alu_01_1" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_alu_01")
-(define_insn_reservation "cfv3_alu_01_2" 0
+(define_insn_reservation "cfv3_alu_01_2" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_alu_01")
-(define_insn_reservation "cfv3_alu_01_3" 0
+(define_insn_reservation "cfv3_alu_01_3" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "01"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "01"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_01")
-(define_insn_reservation "cfv12_alu_0i_2" 0
+(define_insn_reservation "cfv12_alu_0i_2" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "0i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "0i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_alu_0i")
-(define_insn_reservation "cfv12_alu_0i_3" 0
+(define_insn_reservation "cfv12_alu_0i_3" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "0i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_0i")
-(define_insn_reservation "cfv3_alu_0i_2" 0
+(define_insn_reservation "cfv3_alu_0i_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "0i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "0i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_alu_0i")
-(define_insn_reservation "cfv3_alu_0i_3" 0
+(define_insn_reservation "cfv3_alu_0i_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu,omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "0i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_0i")
-(define_insn_reservation "cfv12_alu_11_1" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_alu_11_1" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_alu_11")
-(define_insn_reservation "cfv12_alu_11_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_alu_11_2" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_alu_11")
-(define_insn_reservation "cfv12_alu_11_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_alu_11_3" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_11")
-(define_insn_reservation "cfv12_omove_11_1" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_omove_11_1" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_omove_11")
-(define_insn_reservation "cfv12_omove_11_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_omove_11_2" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_omove_11")
-(define_insn_reservation "cfv12_omove_11_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+(define_insn_reservation "cfv1_omove_11_3" 1
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_omove_11")
+
+(define_insn_reservation "cfv2_alu_11_1" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv12_alu_11")
+
+(define_insn_reservation "cfv2_alu_11_2" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv12_alu_11")
+
+(define_insn_reservation "cfv2_alu_11_3" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_alu_11")
+
+(define_insn_reservation "cfv2_omove_11_1" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv12_omove_11")
+
+(define_insn_reservation "cfv2_omove_11_2" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv12_omove_11")
+
+(define_insn_reservation "cfv2_omove_11_3" 1
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_omove_11")
-(define_insn_reservation "cfv3_alu_11_1" 0
+(define_insn_reservation "cfv3_alu_11_1" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_alu_11")
-(define_insn_reservation "cfv3_alu_11_2" 0
+(define_insn_reservation "cfv3_alu_11_2" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "size" "2"))
(eq_attr "op_mem" "11"))
"cf_ib2+cfv3_alu_11")
-(define_insn_reservation "cfv3_alu_11_3" 0
+(define_insn_reservation "cfv3_alu_11_3" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_11")
-(define_insn_reservation "cfv3_omove_11_1" 0
+(define_insn_reservation "cfv3_omove_11_1" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_omove_11")
-(define_insn_reservation "cfv3_omove_11_2" 0
+(define_insn_reservation "cfv3_omove_11_2" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "size" "2"))
(eq_attr "op_mem" "11"))
"cf_ib2+cfv3_omove_11")
-(define_insn_reservation "cfv3_omove_11_3" 0
+(define_insn_reservation "cfv3_omove_11_3" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_omove_11")
-(define_insn_reservation "cfv12_alu_i1_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+(define_insn_reservation "cfv1_alu_i1_2" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_alu_i1")
-(define_insn_reservation "cfv12_alu_i1_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+(define_insn_reservation "cfv1_alu_i1_3" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_i1")
-(define_insn_reservation "cfv12_omove_i1_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+(define_insn_reservation "cfv1_omove_i1_2" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_omove_i1")
-(define_insn_reservation "cfv12_omove_i1_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+(define_insn_reservation "cfv1_omove_i1_3" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_omove_i1")
-(define_insn_reservation "cfv3_alu_i1_2" 0
+(define_insn_reservation "cfv2_alu_i1_2" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_alu_i1")
+
+(define_insn_reservation "cfv2_alu_i1_3" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_alu_i1")
+
+(define_insn_reservation "cfv2_omove_i1_2" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_omove_i1")
+
+(define_insn_reservation "cfv2_omove_i1_3" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_omove_i1")
+
+(define_insn_reservation "cfv3_alu_i1_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_alu_i1")
-(define_insn_reservation "cfv3_alu_i1_3" 0
+(define_insn_reservation "cfv3_alu_i1_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_i1")
-(define_insn_reservation "cfv3_omove_i1_2" 0
+(define_insn_reservation "cfv3_omove_i1_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_omove_i1")
-(define_insn_reservation "cfv3_omove_i1_3" 0
+(define_insn_reservation "cfv3_omove_i1_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_omove_i1")
-(define_insn_reservation "cfv12_alu_1i_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "1i"))
+(define_insn_reservation "cfv1_alu_1i_2" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_alu_1i")
-(define_insn_reservation "cfv12_alu_1i_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "1i"))
+(define_insn_reservation "cfv1_alu_1i_3" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_alu_1i")
-(define_insn_reservation "cfv12_omove_1i_2" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "1i"))
+(define_insn_reservation "cfv1_omove_1i_2" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_omove_1i")
-(define_insn_reservation "cfv12_omove_1i_3" 0
- (and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "1i"))
+(define_insn_reservation "cfv1_omove_1i_3" 2
+ (and (and (and (eq_attr "cpu" "cfv1")
+ (eq_attr "type" "
+clr,clr_l,mov3q_l,move,moveq_l,tst,
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_omove_1i")
+
+(define_insn_reservation "cfv2_alu_1i_2" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_alu_1i")
+
+(define_insn_reservation "cfv2_alu_1i_3" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_alu_1i")
+
+(define_insn_reservation "cfv2_omove_1i_2" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
+ "cf_ib2+cfv12_omove_1i")
+
+(define_insn_reservation "cfv2_omove_1i_3" 2
+ (and (and (and (eq_attr "cpu" "cfv2")
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_omove_1i")
-(define_insn_reservation "cfv3_alu_1i_2" 0
+(define_insn_reservation "cfv3_alu_1i_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "1i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_alu_1i")
-(define_insn_reservation "cfv3_alu_1i_3" 0
+(define_insn_reservation "cfv3_alu_1i_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "alu"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "1i"))
+ (eq_attr "type" "
+alu_l,aluq_l,bitr,bitrw,cmp,cmp_l,alux_l,ext,neg_l,scc,shift,
+clr,clr_l,mov3q_l,move,moveq_l,tst"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_alu_1i")
-(define_insn_reservation "cfv3_omove_1i_2" 0
+(define_insn_reservation "cfv3_omove_1i_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "1i"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_omove_1i")
-(define_insn_reservation "cfv3_omove_1i_3" 0
+(define_insn_reservation "cfv3_omove_1i_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "omove"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "1i"))
+ (eq_attr "type" "
+move_l,tst_l"))
+ (eq_attr "op_mem" "1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_omove_1i")
(define_insn_reservation "cfv123_lea_10_1" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "lea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "lea"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_lea_10")
(define_insn_reservation "cfv123_lea_10_2" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "lea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "lea"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_lea_10")
(define_insn_reservation "cfv123_lea_10_3" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "lea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "lea"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_lea_10")
(define_insn_reservation "cfv123_lea_i0_2" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "lea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "lea"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv123_lea_i0")
(define_insn_reservation "cfv123_lea_i0_3" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "type2" "lea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "lea"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_lea_i0")
-(define_insn_reservation "cfv12_pea_11_1" 0
+(define_insn_reservation "cfv12_pea_11_1" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_pea_11")
-(define_insn_reservation "cfv12_pea_11_2" 0
+(define_insn_reservation "cfv12_pea_11_2" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_pea_11")
-(define_insn_reservation "cfv12_pea_11_3" 0
+(define_insn_reservation "cfv12_pea_11_3" 1
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_pea_11")
-(define_insn_reservation "cfv3_pea_11_1" 0
+(define_insn_reservation "cfv3_pea_11_1" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_pea_11")
-(define_insn_reservation "cfv3_pea_11_2" 0
+(define_insn_reservation "cfv3_pea_11_2" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_pea_11")
-(define_insn_reservation "cfv3_pea_11_3" 0
+(define_insn_reservation "cfv3_pea_11_3" 1
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "11"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_pea_11")
-(define_insn_reservation "cfv12_pea_i1_2" 0
+(define_insn_reservation "cfv12_pea_i1_2" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_pea_i1")
-(define_insn_reservation "cfv12_pea_i1_3" 0
+(define_insn_reservation "cfv12_pea_i1_3" 2
(and (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_pea_i1")
-(define_insn_reservation "cfv3_pea_i1_2" 0
+(define_insn_reservation "cfv3_pea_i1_2" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_pea_i1")
-(define_insn_reservation "cfv3_pea_i1_3" 0
+(define_insn_reservation "cfv3_pea_i1_3" 2
(and (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "pea"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i1"))
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_pea_i1")
(define_insn_reservation "cfv123_mul_l_00_1" 18
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_mul_l_00")
(define_insn_reservation "cfv123_mul_l_00_2" 18
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_mul_l_00")
(define_insn_reservation "cfv123_mul_l_00_3" 18
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_mul_l_00")
(define_insn_reservation "cfv123_mul_w_00_1" 9
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_mul_w_00")
(define_insn_reservation "cfv123_mul_w_00_2" 9
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_mul_w_00")
(define_insn_reservation "cfv123_mul_w_00_3" 9
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_mul_w_00")
(define_insn_reservation "cfv12_mul_l_10_1" 20
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_mul_l_10")
(define_insn_reservation "cfv12_mul_l_10_2" 20
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_mul_l_10")
(define_insn_reservation "cfv12_mul_l_10_3" 20
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mul_l_10")
(define_insn_reservation "cfv3_mul_l_10_1" 21
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_mul_l_10")
(define_insn_reservation "cfv3_mul_l_10_2" 21
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_mul_l_10")
(define_insn_reservation "cfv3_mul_l_10_3" 21
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mul_l_10")
(define_insn_reservation "cfv12_mul_w_10_1" 11
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_mul_w_10")
(define_insn_reservation "cfv12_mul_w_10_2" 11
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_mul_w_10")
(define_insn_reservation "cfv12_mul_w_10_3" 11
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mul_w_10")
(define_insn_reservation "cfv3_mul_w_10_1" 12
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_mul_w_10")
(define_insn_reservation "cfv3_mul_w_10_2" 12
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_mul_w_10")
(define_insn_reservation "cfv3_mul_w_10_3" 12
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mul_w_10")
(define_insn_reservation "cfv12_mul_w_i0_2" 12
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_mul_w_i0")
(define_insn_reservation "cfv12_mul_w_i0_3" 12
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mul_w_i0")
-
(define_insn_reservation "cfv3_mul_w_i0_2" 13
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_mul_w_i0")
(define_insn_reservation "cfv3_mul_w_i0_3" 13
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "no"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mul_w_i0")
(define_insn_reservation "cfv123_mac_l_00_1" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_mac_l_00")
(define_insn_reservation "cfv123_mac_l_00_2" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_mac_l_00")
(define_insn_reservation "cfv123_mac_l_00_3" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_mac_l_00")
(define_insn_reservation "cfv123_mac_w_00_1" 3
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_mac_w_00")
(define_insn_reservation "cfv123_mac_w_00_2" 3
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_mac_w_00")
(define_insn_reservation "cfv123_mac_w_00_3" 3
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_mac_w_00")
(define_insn_reservation "cfv12_mac_l_10_1" 7
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_mac_l_10")
(define_insn_reservation "cfv12_mac_l_10_2" 7
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_mac_l_10")
(define_insn_reservation "cfv12_mac_l_10_3" 7
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mac_l_10")
(define_insn_reservation "cfv3_mac_l_10_1" 8
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_mac_l_10")
(define_insn_reservation "cfv3_mac_l_10_2" 8
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_mac_l_10")
(define_insn_reservation "cfv3_mac_l_10_3" 8
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_l"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mac_l_10")
(define_insn_reservation "cfv12_mac_w_10_1" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_mac_w_10")
(define_insn_reservation "cfv12_mac_w_10_2" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_mac_w_10")
(define_insn_reservation "cfv12_mac_w_10_3" 5
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mac_w_10")
(define_insn_reservation "cfv3_mac_w_10_1" 6
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_mac_w_10")
(define_insn_reservation "cfv3_mac_w_10_2" 6
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_mac_w_10")
(define_insn_reservation "cfv3_mac_w_10_3" 6
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mac_w_10")
(define_insn_reservation "cfv12_mac_w_i0_2" 6
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_mac_w_i0")
(define_insn_reservation "cfv12_mac_w_i0_3" 6
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_mac_w_i0")
(define_insn_reservation "cfv3_mac_w_i0_2" 7
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_mac_w_i0")
(define_insn_reservation "cfv3_mac_w_i0_3" 7
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_mac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_mac_w_i0")
(define_insn_reservation "cfv123_emac_00_1" 4
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l,mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv123_emac_00")
(define_insn_reservation "cfv123_emac_00_2" 4
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l,mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv123_emac_00")
(define_insn_reservation "cfv123_emac_00_3" 4
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "00"))
+ (eq_attr "type" "mul_l,mul_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv123_emac_00")
-(define_insn_reservation "cfv12_emac_10_1" 6
+(define_insn_reservation "cfv12_emac_l_10_1" 6
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_emac_10")
-(define_insn_reservation "cfv12_emac_10_2" 6
+(define_insn_reservation "cfv12_emac_l_10_2" 6
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_emac_10")
-(define_insn_reservation "cfv12_emac_10_3" 6
+(define_insn_reservation "cfv12_emac_l_10_3" 6
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_emac_10")
-(define_insn_reservation "cfv3_emac_10_1" 7
+(define_insn_reservation "cfv3_emac_l_10_1" 7
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_emac_10")
-(define_insn_reservation "cfv3_emac_10_2" 7
+(define_insn_reservation "cfv3_emac_l_10_2" 7
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_emac_10")
-(define_insn_reservation "cfv3_emac_10_3" 7
+(define_insn_reservation "cfv3_emac_l_10_3" 7
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_l,mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "10"))
+ (eq_attr "type" "mul_l"))
+ (eq_attr "op_mem" "10,i0,i1,11,1i"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv3_emac_10")
+
+(define_insn_reservation "cfv12_emac_w_10_1" 6
+ (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv12_emac_10")
+
+(define_insn_reservation "cfv12_emac_w_10_2" 6
+ (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv12_emac_10")
+
+(define_insn_reservation "cfv12_emac_w_10_3" 6
+ (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
+ "cf_ib3+cfv12_emac_10")
+
+(define_insn_reservation "cfv3_emac_w_10_1" 7
+ (and (and (and (and (eq_attr "cpu" "cfv3")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "1"))
+ "cf_ib1+cfv3_emac_10")
+
+(define_insn_reservation "cfv3_emac_w_10_2" 7
+ (and (and (and (and (eq_attr "cpu" "cfv3")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "2"))
+ "cf_ib2+cfv3_emac_10")
+
+(define_insn_reservation "cfv3_emac_w_10_3" 7
+ (and (and (and (and (eq_attr "cpu" "cfv3")
+ (eq_attr "mac" "cf_emac"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_emac_10")
(define_insn_reservation "cfv12_emac_w_i0_2" 7
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv12_emac_w_i0")
(define_insn_reservation "cfv12_emac_w_i0_3" 7
(and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_emac_w_i0")
(define_insn_reservation "cfv3_emac_w_i0_2" 8
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "1,2"))
"cf_ib2+cfv3_emac_w_i0")
(define_insn_reservation "cfv3_emac_w_i0_3" 8
(and (and (and (and (eq_attr "cpu" "cfv3")
(eq_attr "mac" "cf_emac"))
- (eq_attr "type2" "mul_w"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- (eq_attr "op_mem" "i0"))
+ (eq_attr "type" "mul_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_emac_w_i0")
-(define_insn_reservation "cfv12_rts_1" 5
- (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "rts"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+(define_insn_reservation "cfv12_rts" 5
+ (and (eq_attr "cpu" "cfv1,cfv2")
+ (eq_attr "type" "rts"))
"cf_ib1+cfv12_rts")
-(define_insn_reservation "cfv3_rts_1" 8
- (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "rts"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+(define_insn_reservation "cfv3_rts" 8
+ (and (eq_attr "cpu" "cfv3")
+ (eq_attr "type" "rts"))
"cf_ib1+cfv3_rts")
(define_insn_reservation "cfv12_call_1" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_call")
(define_insn_reservation "cfv12_call_2" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_call")
(define_insn_reservation "cfv12_call_3" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_call")
(define_insn_reservation "cfv3_call_1" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_call")
(define_insn_reservation "cfv3_call_2" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_call")
(define_insn_reservation "cfv3_call_3" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "call"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bsr,jsr"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_call")
(define_insn_reservation "cfv12_bcc_1" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_bcc")
(define_insn_reservation "cfv12_bcc_2" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_bcc")
(define_insn_reservation "cfv12_bcc_3" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_bcc")
(define_insn_reservation "cfv3_bcc_1" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_bcc")
(define_insn_reservation "cfv3_bcc_2" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_bcc")
(define_insn_reservation "cfv3_bcc_3" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bcc"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bcc"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_bcc")
(define_insn_reservation "cfv12_bra_1" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_bra")
(define_insn_reservation "cfv12_bra_2" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_bra")
(define_insn_reservation "cfv12_bra_3" 2
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_bra")
(define_insn_reservation "cfv3_bra_1" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_bra")
(define_insn_reservation "cfv3_bra_2" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_bra")
(define_insn_reservation "cfv3_bra_3" 1
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "bra"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "bra"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_bra")
(define_insn_reservation "cfv12_jmp_1" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv12_jmp")
(define_insn_reservation "cfv12_jmp_2" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv12_jmp")
(define_insn_reservation "cfv12_jmp_3" 3
(and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv12_jmp")
(define_insn_reservation "cfv3_jmp_1" 5
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "1"))
"cf_ib1+cfv3_jmp")
(define_insn_reservation "cfv3_jmp_2" 5
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "2"))
"cf_ib2+cfv3_jmp")
(define_insn_reservation "cfv3_jmp_3" 5
(and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "jmp"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+ (eq_attr "type" "jmp"))
+ (eq_attr "size" "3"))
"cf_ib3+cfv3_jmp")
-;; Misc reservations.
-
-(define_insn_reservation "cfv12_unlk_1" 2
- (and (and (eq_attr "cpu" "cfv1,cfv2")
- (eq_attr "type2" "unlk"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+(define_insn_reservation "cfv12_unlk" 2
+ (and (eq_attr "cpu" "cfv1,cfv2")
+ (eq_attr "type" "unlk"))
"cf_ib1+cfv12_alu_10")
-(define_insn_reservation "cfv3_unlk_1" 3
- (and (and (eq_attr "cpu" "cfv3")
- (eq_attr "type2" "unlk"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+(define_insn_reservation "cfv3_unlk" 3
+ (and (eq_attr "cpu" "cfv3")
+ (eq_attr "type" "unlk"))
"cf_ib1+cfv3_alu_10")
-;; This automaton is used to gather statistics on insns that need reservations.
-(define_automaton "cf_guess")
+;; Dummy reservation for instructions that are not handled.
+(define_insn_reservation "cfv123_guess" 3
+ (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+ (eq_attr "type" "falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
+ div_w,div_l,link,mvsz,nop,trap,unknown"))
+ "cf_ib3+cfv123_guess+cf_dsoc+cf_agex+cf_mem")
-(define_query_cpu_unit "cf_guess" "cf_guess")
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;; Dummy reservation for instructions that are not handled yet.
+;; Below is pipeline description of ColdFire V4 core.
+;; It is substantially different from the description of V1, V2 or V3 cores,
+;; primarily due to no need to model the instruction buffer.
+;;
+;; V4 pipeline model uses a completely separate set of cpu units.
+
+;; Operand Execution Pipeline.
+(define_automaton "cfv4_oep")
+
+(define_cpu_unit "cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da"
+ "cfv4_oep")
+
+;; This automaton is used to support CFv4 dual-issue.
+(define_automaton "cfv4_ds")
+
+;; V4 has 3 cases of dual-issue.
+;; After issuing a cfv4_pOEPx instruction, it'll be possible to issue
+;; a cfv4_sOEPx instruction on the same cycle (see final_presence_sets below).
+(define_cpu_unit "cfv4_pOEP1,cfv4_sOEP1,
+ cfv4_pOEP2,cfv4_sOEP2,
+ cfv4_pOEP3,cfv4_sOEP3" "cfv4_ds")
+
+(final_presence_set "cfv4_sOEP1" "cfv4_pOEP1")
+(final_presence_set "cfv4_sOEP2" "cfv4_pOEP2")
+(final_presence_set "cfv4_sOEP3" "cfv4_pOEP3")
+
+;; Reservation for instructions that don't allow dual-issue.
+(define_reservation "cfv4_ds" "cfv4_pOEP1+cfv4_sOEP1+
+ cfv4_pOEP2+cfv4_sOEP2+
+ cfv4_pOEP3+cfv4_sOEP3")
+
+;; Memory access resource.
+(define_automaton "cfv4_mem")
+
+(define_cpu_unit "cfv4_mem" "cfv4_mem")
+
+;; EMAC.
+(define_automaton "cfv4_emac")
+
+(define_cpu_unit "cfv4_emac" "cfv4_emac")
+
+;; FPU.
+(define_automaton "cfv4_fp")
+
+(define_cpu_unit "cfv4_fp" "cfv4_fp")
+
+;; Automaton for unknown instruction.
+(define_automaton "cfv4_guess")
+
+(define_query_cpu_unit "cfv4_guess" "cfv4_guess")
+
+;; This bypass allows 1st case of dual-issue.
+(define_bypass 0 "cfv4_00_oag_pOEP1,cfv4_10_pOEP1,cfv4_i0_pOEP1"
+ "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_pOEP1,
+ cfv4_00_oag_moveql,cfv4_00_ex_sOEP13")
+
+;; The following bypasses decrease the latency of producers if it modifies
+;; a target register in the EX stage and the consumer also uses
+;; that register in the EX stage.
+(define_bypass 1 "cfv4_00_ex" "cfv4_00_ex,cfv4_00_ex_sOEP13")
+(define_bypass 1 "cfv4_00_ex" "cfv4_10,cfv4_10_pOEP1,cfv4_i0,cfv4_i0_pOEP1"
+ "!m68k_sched_address_bypass_p")
+
+;; Indexed loads with scale factors 2 and 4 require an update of the index
+;; register in the register file. Considering that the index register is
+;; only needed at the second cycle of address generation, we get
+;; a latency of 4.
+;; Producers for indexed loads with scale factor 1 should have
+;; a latency of 3. Since we're only allowed one bypass, we handle it
+;; in the adjust_cost hook.
+(define_bypass 4
+ "cfv4_00_oag,cfv4_00_oag_pOEP3_sOEP12,cfv4_00_oag_lea,cfv4_00_oag_pOEP1,
+ cfv4_00_oag_moveql"
+ "cfv4_i0,cfv4_i0_pOEP1"
+ "m68k_sched_indexed_address_bypass_p")
+
+;; First part of cfv4_00.
+;; If issued in pairs with cfv4_movel_?0, the cost should be increased.
+;; ??? Is it possible that combined cfv4_movel_00 and cfv4_oag_00 instructions
+;; have longer latency than the two instructions emitted sequentially?
+;; Due to register renaming, the result of the sequence would be available
+;; after 3 cycles, instead of 4 for combined instruction?
+(define_insn_reservation "cfv4_00_oag" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,clr_l,cmp_l,mov3q_l,neg_l"))
+ (eq_attr "op_mem" "00"))
+ "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
+
+(define_insn_reservation "cfv4_00_oag_pOEP3_sOEP12" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "move_l,mov3q_l,clr_l"))
+ (and (eq_attr "op_mem" "00")
+ (and (eq_attr "opx_type" "Rn")
+ (eq_attr "opy_type" "none,imm_q,imm_w,imm_l"))))
+ "cfv4_sOEP1|cfv4_sOEP2|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
+
+(define_insn_reservation "cfv4_00_oag_lea" 1
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "lea"))
+ "cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_00_oag_pOEP1" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "move_l,mov3q_l,clr_l"))
+ (and (eq_attr "op_mem" "00")
+ (ior (eq_attr "opx_type" "!Rn")
+ (eq_attr "opy_type" "!none,imm_q,imm_w,imm_l"))))
+ "cfv4_sOEP1|(cfv4_pOEP1,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
+
+(define_insn_reservation "cfv4_00_oag_moveql" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "moveq_l"))
+ (eq_attr "op_mem" "00"))
+ "cfv4_sOEP1|cfv4_sOEP2|cfv4_sOEP3|(cfv4_pOEP3,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
-(define_insn_reservation "cf_guess_1" 1
- (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "guess" "yes"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
- "cf_ib1+cf_guess+cf_dsoc+cf_agex")
+;; Second part of cfv4_00.
+;; Latency is either 1 or 4 depending on which stage the consumer
+;; will need the data.
-(define_insn_reservation "cf_guess_2" 1
- (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "guess" "yes"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
- "cf_ib2+cf_guess+cf_dsoc+cf_agex")
+(define_insn_reservation "cfv4_00_ex" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "bitr,bitrw,clr,cmp,move,mvsz,scc,tst"))
+ (eq_attr "op_mem" "00"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_00_ex_sOEP13" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alux_l,ext,shift,tst_l"))
+ (eq_attr "op_mem" "00"))
+ "cfv4_sOEP1|cfv4_sOEP3|(cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex)")
+
+;; Several types mentioned in this reservation (e.g., ext and shift) don't
+;; support implicit load. But we handle them anyway due to first scheduling
+;; pass, which handles non-strict rtl.
+;;
+;; Latency is either 1 or 4 depending in which stage the consumer
+;; will need the data.
+(define_insn_reservation "cfv4_10" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,moveq_l,mvsz,neg_l,
+ shift,tst,tst_l"))
+ (eq_attr "op_mem" "10"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
+
+;; Specialization of cfv4_10.
+;; move.l has OC2-to-DS forwarding path, that saves one cycle of latency.
+(define_insn_reservation "cfv4_10_pOEP1" 3
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "move_l"))
+ (eq_attr "op_mem" "10"))
+ "cfv4_pOEP1,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
+
+;; Same here. But +1 to latency due to longer OAG.
+(define_insn_reservation "cfv4_i0" 5
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,moveq_l,mvsz,neg_l,
+ shift,tst,tst_l"))
+ (eq_attr "op_mem" "i0"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
-(define_insn_reservation "cf_guess_3" 1
- (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
- (eq_attr "guess" "yes"))
- (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
- "cf_ib3+cf_guess+cf_dsoc+cf_agex")
+;; ??? Does indexed load trigger dual-issue?
+;; ??? Does OC2-to-DS forwarding path saves a cycle?
+(define_insn_reservation "cfv4_i0_pOEP1" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "move_l"))
+ (eq_attr "op_mem" "i0"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
+
+;; This reservation is for moves and clr. Arithmetic instructions
+;; don't write to memory unless they also read from it.
+;; But, before reload we can have all sorts of things.
+;; With cfv4_pOEP2 allow dual-issue for type 2 cases.
+(define_insn_reservation "cfv4_01" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
+ shift"))
+ (eq_attr "op_mem" "01"))
+ "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+;; ??? Does indexed store trigger dual-issue?
+(define_insn_reservation "cfv4_0i" 2
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
+ shift"))
+ (eq_attr "op_mem" "0i"))
+ "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+(define_insn_reservation "cfv4_11" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
+ shift"))
+ (eq_attr "op_mem" "11"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+;; Latency is 2 due to long OAG stage.
+(define_insn_reservation "cfv4_i1" 2
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
+ shift"))
+ (eq_attr "op_mem" "i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+;; This one is the same as cfv4_i1.
+;; ??? Should it be different?
+(define_insn_reservation "cfv4_1i" 2
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitr,bitrw,
+ clr,clr_l,cmp,cmp_l,ext,
+ mov3q_l,move,move_l,moveq_l,mvsz,neg_l,
+ shift"))
+ (eq_attr "op_mem" "1i"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+;; ??? Does pea indeed support case 2 of dual-issue?
+(define_insn_reservation "cfv4_11_pea" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "11,00,01,0i,10"))
+ "cfv4_pOEP2,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+;; ??? Does pea indeed support case 2 of dual-issue?
+;; ??? Does indexed store trigger dual-issue?
+(define_insn_reservation "cfv4_i1_pea" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "pea"))
+ (eq_attr "op_mem" "i1,1i"))
+ "cfv4_pOEP2,cfv4_oag,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_da,cfv4_mem")
+
+(define_insn_reservation "cfv4_link" 2
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "link"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_ex,cfv4_da,cfv4_mem")
+
+(define_insn_reservation "cfv4_unlink" 2
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "unlk"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_divw_00" 20
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "div_w"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*15")
+
+(define_insn_reservation "cfv4_divw_10" 20
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "div_w"))
+ (eq_attr "op_mem" "10,11,1i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15")
+
+(define_insn_reservation "cfv4_divw_i0" 21
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "div_w"))
+ (eq_attr "op_mem" "i0,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*15")
+
+(define_insn_reservation "cfv4_divl_00" 35
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "div_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex*30")
+
+(define_insn_reservation "cfv4_divl_10" 35
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "div_l"))
+ (eq_attr "op_mem" "10,11,1i,i0,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex*30")
+
+(define_insn_reservation "cfv4_emac_mul_00" 7
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "mul_w,mul_l"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_emac")
+
+(define_insn_reservation "cfv4_emac_mul_10" 7
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "mul_w,mul_l"))
+ (eq_attr "op_mem" "10,11,1i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac")
+
+(define_insn_reservation "cfv4_emac_mul_i0" 8
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "mul_w,mul_l"))
+ (eq_attr "op_mem" "i0,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac")
+
+(define_insn_reservation "cfv4_falu_00" 7
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "falu,fcmp,fmul"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
+
+(define_insn_reservation "cfv4_falu_10" 7
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "falu,fcmp,fmul"))
+ (eq_attr "op_mem" "10,i0,11,1i,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp")
+
+(define_insn_reservation "cfv4_fneg_00" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fmove,fneg,ftst"))
+ (eq_attr "op_mem" "00"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
+
+(define_insn_reservation "cfv4_fmove_fneg_10" 4
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fmove,fneg,ftst"))
+ (eq_attr "op_mem" "10,i0,11,1i,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp")
+
+(define_insn_reservation "cfv4_fmove_01" 1
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fmove,fneg,ftst"))
+ (eq_attr "op_mem" "01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp,cfv4_da,cfv4_mem")
+
+(define_insn_reservation "cfv4_fdiv_00" 23
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fdiv"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*17")
+
+(define_insn_reservation "cfv4_fdiv_10" 23
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fdiv"))
+ (eq_attr "op_mem" "10,i0,11,1i,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*17")
+
+(define_insn_reservation "cfv4_fsqrt_00" 56
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fsqrt"))
+ (eq_attr "op_mem" "00,01,0i"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp*50")
+
+(define_insn_reservation "cfv4_fsqrt_10" 56
+ (and (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fsqrt"))
+ (eq_attr "op_mem" "10,i0,11,1i,i1"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_fp*50")
+
+(define_insn_reservation "cfv4_bcc" 0
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "bcc"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_fbcc" 2
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "fbcc"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex,cfv4_fp")
+
+;; ??? Why is bra said to write to memory: 1(0/1) ?
+(define_insn_reservation "cfv4_bra_bsr" 1
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "bra,bsr"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_jmp_jsr" 5
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "jmp,jsr"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_rts" 2
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "rts"))
+ "cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex")
+
+(define_insn_reservation "cfv4_nop" 1
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "nop"))
+ "cfv4_ds+cfv4_oag+cfv4_oc1+cfv4_mem+cfv4_oc2+cfv4_ex")
+
+(define_insn_reservation "cfv4_guess" 10
+ (and (eq_attr "cpu" "cfv4")
+ (eq_attr "type" "trap,unknown"))
+ "cfv4_guess+cfv4_ds,cfv4_oag,cfv4_oc1+cfv4_mem,cfv4_oc2,cfv4_ex,cfv4_emac+cfv4_fp")
+
+(define_insn_reservation "ignore" 0
+ (eq_attr "type" "ignore")
+ "nothing")
(UNSPEC_COS 2)
(UNSPEC_GOT 3)
(UNSPEC_IB 4)
+ (UNSPEC_TIE 5)
])
;; UNSPEC_VOLATILE usage:
;; ::::::::::::::::::::
;; Processor type.
-(define_attr "cpu" "cfv1, cfv2, cfv3, unknown"
+(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
(const (symbol_ref "m68k_sched_cpu")))
;; MAC type.
(define_attr "mac" "no, cf_mac, cf_emac"
(const (symbol_ref "m68k_sched_mac")))
-;; Instruction type.
-;; Basically, an asm pattern.
-(define_attr "type"
- "add_l, addq_l, asr_l, bcc, bclr, bra, bset, bsr,
- clr_b, clr_w, clr_l, cmp_l,
- ext_w, extb_l, ext_l,
- fadd, fcmp, fdiv, ff1, fintrz, fmove, fmul, fsqrt, fsub, ftst, jmp, jsr,
- ib,
- lea, lsr_l,
- move_b, move_w, move_l, moveq_l, mov3q_l, mvs_b, mvs_w, mvz_b, mvz_w,
- muls_w, muls_l, mulu_w, mulu_l,
- neg_l, nop, not_l,
- pea, rts,
- scc, sub_l, subq_l,
- trap, tst_b, tst_l, tst_w,
- unlk, unknown"
- (const_string "unknown"))
-
;; Instruction type for use in scheduling description.
;; _l and _w suffixes indicate size of the operands of instruction.
;; alu - usual arithmetic or logic instruction.
-;; alu_reg1 - arithmetic or logic instruction with one operand that is
-;; a register.
-;; alu_regx - arithmetic or logic instruction which has a register for its
-;; X operand.
;; aluq - arithmetic or logic instruction which has a quick immediate (the one
;; that is encoded in the instruction word) for its Y operand.
-;; <all other values> - corresponding asm instructions.
-(define_attr "type1"
- "alu_l, alu_reg1, alu_regx, aluq_l, bcc, bra, bsr, clr, cmp_l, jmp, jsr, lea,
- mov3q_l, move, move_l, moveq_l, mul_l, mul_w, pea, rts, tst, tst_l, unlk,
+;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
+;; bcc - conditional branch.
+;; bitr - bit operation that only updates flags.
+;; bitrw - bit operation that updates flags and output operand.
+;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
+;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
+;; instruction.
+;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
+;; buffer.
+;; ignore - fake instruction.
+;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
+;; mvsz - mvs or mvz instruction.
+;; neg, nop, pea, rts, scc - corresponding instruction.
+;; shift - arithmetic or logical shift instruction.
+;; trap, tst, unlk - corresponding instruction.
+(define_attr "type"
+ "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
+ div_w,div_l,ext,
+ falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
+ ib,ignore,
+ jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
+ pea,rts,scc,shift,
+ trap,tst,tst_l,unlk,
unknown"
- (cond [(eq_attr "type" "add_l,sub_l") (const_string "alu_l")
- (eq_attr "type" "ext_w,extb_l,ext_l,neg_l,not_l")
- (const_string "alu_reg1")
- (eq_attr "type" "asr_l,lsr_l") (const_string "alu_regx")
- (eq_attr "type" "addq_l,subq_l") (const_string "aluq_l")
- (eq_attr "type" "bcc") (const_string "bcc")
- (eq_attr "type" "bra") (const_string "bra")
- (eq_attr "type" "bsr") (const_string "bsr")
- (eq_attr "type" "clr_b,clr_l,clr_w") (const_string "clr")
- (eq_attr "type" "cmp_l") (const_string "cmp_l")
- (eq_attr "type" "jmp") (const_string "jmp")
- (eq_attr "type" "jsr") (const_string "jsr")
- (eq_attr "type" "lea") (const_string "lea")
- (eq_attr "type" "mov3q_l") (const_string "mov3q_l")
- (eq_attr "type" "move_b,move_w") (const_string "move")
- (eq_attr "type" "move_l") (const_string "move_l")
- (eq_attr "type" "moveq_l") (const_string "moveq_l")
- (eq_attr "type" "muls_l,mulu_l") (const_string "mul_l")
- (eq_attr "type" "muls_w,mulu_w") (const_string "mul_w")
- (eq_attr "type" "pea") (const_string "pea")
- (eq_attr "type" "rts") (const_string "rts")
- (eq_attr "type" "tst_b,tst_w") (const_string "tst")
- (eq_attr "type" "tst_l") (const_string "tst_l")
- (eq_attr "type" "unlk") (const_string "unlk")]
- (const_string "unknown")))
+ (const_string "unknown"))
;; Index of the X or Y operand in recog_data.operand[].
;; Should be used only within opx_type and opy_type.
(define_attr "opx" "" (const_int 0))
(define_attr "opy" "" (const_int 1))
-;; Type of the X operand.
-;; See m68k.c: enum attr_op_type.
-(define_attr "opx_type"
- "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
- (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
- (eq_attr "type1" "alu_reg1,alu_regx,lea,moveq_l,mul_l,mul_w")
- (const_string "reg")
- (eq_attr "type1" "pea") (const_string "mem1")
- (eq_attr "type1" "bcc") (const_string "imm_q")
- (eq_attr "type1" "bra,bsr") (const_string "imm_w")
- (eq_attr "type1" "jmp,jsr")
- (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
- (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
-
;; Type of the Y operand.
;; See m68k.c: enum attr_op_type.
(define_attr "opy_type"
- "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
- (cond [(eq_attr "type1" "alu_reg1,bcc,bra,bsr,clr,jmp,jsr,rts,tst,tst_l,
- unlk") (const_string "none")
- (eq_attr "type1" "mov3q_l,moveq_l,aluq_l") (const_string "imm_q")
- (eq_attr "type1" "lea,pea")
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
+ jmp,jsr,nop,rts,scc,trap,tst,tst_l,
+ unlk,unknown") (const_string "none")
+ (eq_attr "type" "lea,pea")
(symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
(symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
-;; Instruction size in words.
-(define_attr "size" ""
- (cond [(eq_attr "type1" "alu_reg1,moveq_l,rts,unlk") (const_int 1)]
- (symbol_ref "m68k_sched_attr_size (insn)")))
+;; Type of the X operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opx_type"
+ "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "pea") (const_string "mem1")
+ (eq_attr "type" "jmp,jsr")
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
+ (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
;; Access to the X operand: none, read, write, read/write, unknown.
;; Access to the Y operand is either none (if opy_type is none)
;; or read otherwise.
-(define_attr "opx_access" "none, r, w, rw, unknown"
- (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
- (eq_attr "type1" "bcc,bra,bsr,cmp_l,jmp,jsr,tst,tst_l")
- (const_string "r")
- (eq_attr "type1" "clr,lea,mov3q_l,move,move_l,moveq_l,pea")
- (const_string "w")
- (eq_attr "type1" "alu_l,alu_reg1,alu_regx,aluq_l")
- (const_string "rw")]
- (const_string "unknown")))
-
-;; Memory relation of operands:
-;; r - register or immediate operand
-;; m - non-indexed memory location
-;; i - indexed memory location
-
-(define_attr "opx_mem" "r, m, i, unknown"
- (cond [(eq_attr "opx_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
- (eq_attr "opx_type" "mem1,mem234,mem5,mem7") (const_string "m")
- (eq_attr "opx_type" "mem6") (const_string "i")]
- (const_string "unknown")))
-
-(define_attr "opy_mem" "r, m, i, unknown"
- (cond [(eq_attr "opy_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
- (eq_attr "opy_type" "mem1,mem234,mem5,mem7") (const_string "m")
- (eq_attr "opy_type" "mem6") (const_string "i")]
- (const_string "unknown")))
+(define_attr "opx_access" "none, r, w, rw"
+ (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+ unknown") (const_string "none")
+ (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
+ jmp,jsr,tst,tst_l") (const_string "r")
+ (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
+ mov3q_l,move,move_l,moveq_l,mvsz,
+ pea,scc") (const_string "w")
+ (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
+ falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
+ neg_l,shift") (const_string "rw")]
+ ;; Should never be used.
+ (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
;; Memory accesses of the insn.
;; 00 - no memory references
;; 10 - memory is read
-;; i10 - indexed memory is read
+;; i0 - indexed memory is read
;; 01 - memory is written
-;; 0i1 - indexed memory is written
+;; 0i - indexed memory is written
;; 11 - memory is read, memory is written
-;; i11 - indexed memory is read, memory is written
-;; 1i1 - memory is read, indexed memory is written
-;;
-;; unknown - should now occur on normal insn.
-;; ??? This attribute is implemented in C to spare genattrtab from
-;; ??? optimizing it.
-(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i, unknown"
-; (cond [(and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "r"))
-; (const_string "00")
-;
-; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "m"))
-; (cond [(eq_attr "opx_access" "r") (const_string "10")
-; (eq_attr "opx_access" "w") (const_string "01")
-; (eq_attr "opx_access" "rw") (const_string "11")]
-; (const_string "unknown"))
-;
-; (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "i"))
-; (cond [(eq_attr "opx_access" "r") (const_string "i0")
-; (eq_attr "opx_access" "w") (const_string "0i")
-; (eq_attr "opx_access" "rw") (const_string "i1")]
-; (const_string "unknown"))
-;
-; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "r"))
-; (const_string "10")
-;
-; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "m"))
-; (cond [(eq_attr "opx_access" "w") (const_string "11")]
-; (const_string "unknown"))
-;
-; (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "i"))
-; (cond [(eq_attr "opx_access" "w") (const_string "1i")]
-; (const_string "unknown"))
-;
-; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "r"))
-; (const_string "i0")
-;
-; (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "m"))
-; (cond [(eq_attr "opx_access" "w") (const_string "i1")]
-; (const_string "unknown"))]
-; (const_string "unknown"))
+;; i1 - indexed memory is read, memory is written
+;; 1i - memory is read, indexed memory is written
+(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
(symbol_ref "m68k_sched_attr_op_mem (insn)"))
-;; Attribute to support partial automata description.
-;; This attribute has value 'yes' for instructions that are not
-;; fully handled yet.
-(define_attr "guess" "yes, no"
- (cond [(ior (eq (symbol_ref "reload_completed") (const_int 0))
- (eq_attr "type1" "unknown"))
- (const_string "yes")]
- (const_string "no")))
-
-;; Attribute to support statistics gathering.
-;; Todo means that insn lacks something to get pipeline description.
-;; Done means that insn was transformed to suit pipeline description.
-;; Nothing means that insn was originally good enough for scheduling.
-(define_attr "split" "todo, done, nothing"
- (if_then_else (eq_attr "type" "unknown")
- (const_string "todo")
- (const_string "nothing")))
+;; Instruction size in words.
+(define_attr "size" "1,2,3"
+ (symbol_ref "m68k_sched_attr_size (insn)"))
+
\f
;; Mode macros for floating point operations.
;; Valid floating point modes
m68k_emit_move_double (operands);
DONE;
}
- [(set_attr "type" "fmove,*")
- (set_attr "split" "done,*")])
+ [(set_attr "type" "fmove,*")])
(define_insn_and_split "pushdi"
[(set (match_operand:DI 0 "push_operand" "=m")
"@
tst%.l %0
cmp%.w #0,%0"
- [(set_attr "type" "tst_l,*")])
+ [(set_attr "type" "tst_l,cmp")])
;; This can't use an address register, because comparisons
;; with address registers as second operand always test the whole word.
(match_operand:HI 0 "nonimmediate_operand" "dm"))]
""
"tst%.w %0"
- [(set_attr "type" "tst_w")])
+ [(set_attr "type" "tst")])
(define_expand "tstqi"
[(set (cc0)
(match_operand:QI 0 "nonimmediate_operand" "dm"))]
""
"tst%.b %0"
- [(set_attr "type" "tst_b")])
+ [(set_attr "type" "tst")])
(define_expand "tst<mode>"
[(set (cc0)
if (FP_REG_P (operands[0]))
return "ftst%.x %0";
return "ftst%.<FP:prec> %0";
-})
+}
+ [(set_attr "type" "ftst")])
(define_insn "tst<mode>_cf"
[(set (cc0)
if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
|| (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
{
- cc_status.flags |= CC_REVERSED;
+ cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.w %d0,%d1";
}
return "cmp%.w %d1,%d0";
clr%.l %0
mov3q%.l %1,%-
pea %a1"
- [(set_attr "type" "clr_l,mov3q_l,pea")
- (set_attr "split" "done")])
+ [(set_attr "type" "clr_l,mov3q_l,pea")])
;This is never used.
;(define_insn "swapsi"
moveq #0,%0
sub%.l %0,%0
clr%.l %0"
- [(set_attr "type" "moveq_l,sub_l,clr_l")
- (set_attr "opy_type" "imm_q,reg,*")
- (set_attr "split" "done")])
+ [(set_attr "type" "moveq_l,alu_l,clr_l")
+ (set_attr "opy" "*,0,*")])
;; Special case of fullword move when source is zero for 68040_60.
;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
return "";
}
}
- [(set_attr "type" "lea,clr_l")
- (set_attr "opy_type" "imm_w,*")
- (set_attr "split" "done")])
+ [(set_attr "type" "lea,clr_l")])
;; Special case of fullword move when source is zero.
(define_insn "*movsi_const0"
"@
sub%.l %0,%0
clr%.l %0"
- [(set_attr "type" "sub_l,clr_l")
- (set_attr "opy_type" "reg,*")
- (set_attr "split" "done")])
+ [(set_attr "type" "alu_l,clr_l")
+ (set_attr "opy" "0,*")])
;; General case of fullword move.
;;
return "";
}
}
- [(set_attr "type" "mov3q_l, moveq_l,*, mvz_w, mvs_w, move_l, move_w, pea, lea, move_l, move_l, move_l")
- (set (attr "split")
- (if_then_else (eq_attr "alternative" "2")
- (const_string "*")
- (const_string "done")))])
+ [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
;; Special case of fullword move, where we need to get a non-GOT PIC
;; reference into an address register.
clr%.b %0
move%.b %1,%0
move%.b %1,%0"
- [(set_attr "type" "clr_b,clr_b,move_b,move_b")
- (set_attr "split" "done")])
+ [(set_attr "type" "clr,clr,move,move")])
(define_expand "pushqi1"
[(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
"ISA_HAS_MVS_MVZ"
"mvz%.w %1,%0"
- [(set_attr "type" "mvz_w")])
+ [(set_attr "type" "mvsz")])
(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
"ISA_HAS_MVS_MVZ"
"mvz%.b %1,%0"
- [(set_attr "type" "mvz_b")])
+ [(set_attr "type" "mvsz")])
(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
"ISA_HAS_MVS_MVZ"
"mvs%.w %1,%0"
- [(set_attr "type" "mvs_w")])
+ [(set_attr "type" "mvsz")])
(define_insn "*68k_extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
"@
ext%.l %0
move%.w %1,%0"
- [(set_attr "type" "ext_l,move_w")])
+ [(set_attr "type" "ext,move")])
(define_insn "extendqihi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
""
"ext%.w %0"
- [(set_attr "type" "ext_w")])
+ [(set_attr "type" "ext")])
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
"ISA_HAS_MVS_MVZ"
"mvs%.b %1,%0"
- [(set_attr "type" "mvs_b")])
+ [(set_attr "type" "mvsz")])
(define_insn "*68k_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
"TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
"extb%.l %0"
- [(set_attr "type" "extb_l")])
+ [(set_attr "type" "ext")])
\f
;; Conversions between float and double.
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(float:FP (match_operand:SI 1 "general_operand" "dmi")))]
"TARGET_68881"
- "f<FP:round>move%.l %1,%0")
+ "f<FP:round>move%.l %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "floatsi<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[1]))
return "fintrz%.x %f1,%0";
return "fintrz%.<FP:prec> %f1,%0";
-})
+}
+ [(set_attr "type" "falu")])
(define_insn "ftrunc<mode>2_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return "fintrz%.d %f1,%0";
return "fintrz%.<FP:prec> %f1,%0";
}
- [(set_attr "type" "fintrz")])
+ [(set_attr "type" "falu")])
;; Convert a float whose value is an integer
;; to an actual integer. Second stage of converting float to integer type.
[(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
(fix:QI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.b %1,%0")
+ "fmove%.b %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>qi2_cf"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
(fix:HI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.w %1,%0")
+ "fmove%.w %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>hi2_cf"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
[(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
(fix:SI (match_operand:FP 1 "general_operand" "f")))]
"TARGET_68881"
- "fmove%.l %1,%0")
+ "fmove%.l %1,%0"
+ [(set_attr "type" "fmove")])
(define_insn "fix<mode>si2_cf"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
operands[1] = adjust_address (operands[1], SImode, 4);
return "add%.l %1,%0";
}
- [(set_attr "type" "add_l")])
+ [(set_attr "type" "alu_l")])
(define_insn "adddi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
(plus:SI (match_dup 0)
(match_dup 1)))]
""
- [(set_attr "type" "addq_l,subq_l,add_l,add_l,*,lea,lea,lea")
+ [(set_attr "type" "aluq_l,aluq_l,alu_l,alu_l,*,lea,lea,lea")
(set_attr "opy" "2,2,2,2,*,*,*,*")
- (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")
- (set_attr "split" "done,done,done,done,*,done,done,done")])
+ (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=a")
(plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.l %2,%0")
+ "f<FP:round>add%.l %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.w %2,%0")
+ "f<FP:round>add%.w %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
(match_operand:FP 1 "general_operand" "0")))]
"TARGET_68881"
- "f<FP:round>add%.b %2,%0")
+ "f<FP:round>add%.b %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:round>add%.x %2,%0";
return "f<FP:round>add%.<FP:prec> %f2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "add<mode>3_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return "f<FP:prec>add%.d %2,%0";
return "f<FP:prec>add%.<FP:prec> %2,%0";
}
- [(set_attr "type" "fadd")])
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
\f
;; subtract instructions
operands[1] = adjust_address (operands[1], SImode, 4);
return "sub%.l %1,%0";
}
- [(set_attr "type" "sub_l")])
+ [(set_attr "type" "alu_l")])
(define_insn "subdi3"
[(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
sub%.l %2,%0
sub%.l %2,%0
sub%.l %2,%0"
- [(set_attr "type" "subq_l,sub_l,sub_l,sub_l")
+ [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
(set_attr "opy" "2")])
(define_insn ""
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
"TARGET_68881"
- "f<FP:round>sub%.l %2,%0")
+ "f<FP:round>sub%.l %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
"TARGET_68881"
- "f<FP:round>sub%.w %2,%0")
+ "f<FP:round>sub%.w %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(minus:FP (match_operand:FP 1 "general_operand" "0")
(float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
"TARGET_68881"
- "f<FP:round>sub%.b %2,%0")
+ "f<FP:round>sub%.b %2,%0"
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
if (FP_REG_P (operands[2]))
return "f<FP:round>sub%.x %2,%0";
return "f<FP:round>sub%.<FP:prec> %f2,%0";
-})
+}
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
(define_insn "sub<mode>3_cf"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return "f<FP:prec>sub%.d %2,%0";
return "f<FP:prec>sub%.<FP:prec> %2,%0";
}
- [(set_attr "type" "fsub")])
+ [(set_attr "type" "falu")
+ (set_attr "opy" "2")])
\f
;; multiply instructions
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
}
- [(set_attr "type" "muls_w")
+ [(set_attr "type" "mul_w")
(set_attr "opy" "2")])
(define_insn "mulhisi3"
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
}
- [(set_attr "type" "muls_w")
+ [(set_attr "type" "mul_w")
(set_attr "opy" "2")])
(define_insn "*mulhisisi3_s"
{
return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
}
- [(set_attr "type" "muls_w")
+ [(set_attr "type" "mul_w")
(set_attr "opy" "2")])
(define_expand "mulsi3"
"TARGET_68020"
"muls%.l %2,%0"
- [(set_attr "type" "muls_l")
+ [(set_attr "type" "mul_l")
(set_attr "opy" "2")])
(define_insn "*mulsi3_cf"
(match_operand:SI 2 "general_operand" "d<Q>")))]
"TARGET_COLDFIRE"
"muls%.l %2,%0"
- [(set_attr "type" "muls_l")
+ [(set_attr "type" "mul_l")
(set_attr "opy" "2")])
(define_insn "umulhisi3"
{
return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
}
- [(set_attr "type" "mulu_w")
+ [(set_attr "type" "mul_w")
(set_attr "opy" "2")])
(define_insn "*mulhisisi3_z"
{
return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
}
- [(set_attr "type" "mulu_w")
+ [(set_attr "type" "mul_w")
(set_attr "opy" "2")])
;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
return TARGET_68040
? "f<FP:round>mul%.l %2,%0"
: "f<FP:round_mul>mul%.l %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "mul<mode>3_floathi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return TARGET_68040
? "f<FP:round>mul%.w %2,%0"
: "f<FP:round_mul>mul%.w %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "mul<mode>3_floatqi_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
return TARGET_68040
? "f<FP:round>mul%.b %2,%0"
: "f<FP:round_mul>mul%.b %2,%0";
-})
+}
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
(define_insn "muldf_68881"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f")
return "f<FP:prec>mul%.d %2,%0";
return "f<FP:prec>mul%.<FP:prec> %2,%0";
}
- [(set_attr "type" "fmul")])
+ [(set_attr "type" "fmul")
+ (set_attr "opy" "2")])
\f
;; divide instructions
return "f<FP:prec>div%.d %2,%0";
return "f<FP:prec>div%.<FP:prec> %2,%0";
}
- [(set_attr "type" "fdiv")])
+ [(set_attr "type" "fdiv")
+ (set_attr "opy" "2")])
\f
;; Remainder instructions.
return "rems%.l %2,%3:%0";
else
return "rems%.l %2,%3:%0\;divs%.l %2,%0";
-})
+}
+ [(set_attr "type" "div_l")
+ (set_attr "opy" "2")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
return "remu%.l %2,%3:%0";
else
return "remu%.l %2,%3:%0\;divu%.l %2,%0";
-})
+}
+ [(set_attr "type" "div_l")
+ (set_attr "opy" "2")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
if (FP_REG_P (operands[1]))
return "f<FP:prec>sqrt%.d %1,%0";
return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
-})
+}
+ [(set_attr "type" "fsqrt")])
;; Absolute value instructions
;; If using software floating point, just zero the sign bit.
if (FP_REG_P (operands[1]))
return "f<FP:prec>abs%.d %1,%0";
return "f<FP:prec>abs%.<FP:prec> %1,%0";
-})
+}
+ [(set_attr "type" "bitrw,fneg")])
\f
;; bit indexing instructions
(clz:SI (match_operand:SI 1 "register_operand" "0")))]
"ISA_HAS_FF1"
"ff1 %0"
- [(set_attr "type" "ff1")])
+ [(set_attr "type" "ext")])
\f
;; one complement instructions
(not:SI (match_operand:SI 1 "general_operand" "0")))]
"TARGET_COLDFIRE"
"not%.l %0"
- [(set_attr "type" "not_l")])
+ [(set_attr "type" "neg_l")])
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
operands[1] = adjust_address (operands[1], HImode, 2);
return "move%.w %1,%0";
}
- [(set_attr "type" "move_w")])
+ [(set_attr "type" "move")])
(define_insn "subregsi1ashrdi_const32"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(match_operand:SI 2 "general_operand" "dI")))]
""
"asr%.l %2,%0"
- [(set_attr "type" "asr_l")
+ [(set_attr "type" "shift")
(set_attr "opy" "2")])
(define_insn "ashrhi3"
(match_operand:SI 2 "general_operand" "dI")))]
""
"lsr%.l %2,%0"
- [(set_attr "type" "lsr_l")
+ [(set_attr "type" "shift")
(set_attr "opy" "2")])
(define_insn "lshrhi3"
CC_STATUS_INIT;
return "bset %1,%0";
}
- [(set_attr "type" "bset")])
+ [(set_attr "type" "bitrw")])
;; set bit, bit number is (sign/zero)_extended from HImode/QImode
(define_insn "*bsetmemqi_ext"
CC_STATUS_INIT;
return "bset %1,%0";
}
- [(set_attr "type" "bset")])
+ [(set_attr "type" "bitrw")])
;; clear bit, bit number is int
(define_insn "bclrmemqi"
CC_STATUS_INIT;
return "bclr %1,%0";
}
- [(set_attr "type" "bclr")])
+ [(set_attr "type" "bitrw")])
;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
(define_insn "*bclrmemqi_ext"
CC_STATUS_INIT;
return "bclr %1,%0";
}
- [(set_attr "type" "bclr")])
+ [(set_attr "type" "bitrw")])
;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
{
OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
}
- [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
- (set_attr "split" "done")])
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bne"
[(set (pc)
{
OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
}
- [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
- (set_attr "split" "done")])
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bgt"
[(set (pc)
{
OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
}
- [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
- (set_attr "split" "done")])
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bgtu"
[(set (pc)
{
OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
}
- [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
- (set_attr "split" "done")])
+ [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
(define_insn "bltu"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjor %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunordered"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjun %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "buneq"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjueq %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunge"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjuge %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bungt"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjugt %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunle"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjule %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bunlt"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjult %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "bltgt"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjogl %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
\f
;; Negated conditional jump instructions.
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjun %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunordered_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjor %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*buneq_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjogl %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunge_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjolt %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bungt_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjole %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunle_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjogt %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bunlt_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjoge %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
(define_insn "*bltgt_rev"
[(set (pc)
{
gcc_assert (cc_prev_status.flags & CC_IN_68881);
return "fjueq %l0";
-})
+}
+ [(set_attr "type" "fbcc")])
\f
;; Unconditional and other jump instructions
(define_insn "jump"
{
return MOTOROLA ? "jmp (%0)" : "jmp %0@";
}
- [(set_attr "type" "bra")])
+ [(set_attr "type" "jmp")])
;; Jump to variable address from dispatch table of relative addresses.
(define_insn ""
"!SIBLING_CALL_P (insn)"
{
return output_call (operands[0]);
-})
+}
+ [(set_attr "type" "jsr")])
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
"!SIBLING_CALL_P (insn)"
"jsr %a1"
[(set_attr "type" "jsr")
- (set_attr "split" "done")
(set_attr "opx" "1")])
(define_insn "*symbolic_call_value_jsr"
return m68k_symbolic_call;
}
[(set_attr "type" "jsr")
- (set_attr "split" "done")
(set_attr "opx" "1")])
(define_insn "*symbolic_call_value_bsr"
return m68k_symbolic_call;
}
[(set_attr "type" "bsr")
- (set_attr "split" "done")
(set_attr "opx" "1")])
;; Call subroutine returning any type.
return "link.w %0,%1";
else
return "link.l %0,%1";
-})
+}
+ [(set_attr "type" "link")])
(define_expand "unlink"
[(parallel
}
})
+;; These are to prevent the scheduler from moving stores to the frame
+;; before the stack adjustment.
+(define_insn "stack_tie"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK [(match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "register_operand" "r")]
+ UNSPEC_TIE))]
+ ""
+ ""
+ [(set_attr "type" "ignore")])
+
;; Instruction that subscribes one word in ColdFire instruction buffer.
;; This instruction is used within scheduler only and should not appear
;; in the instruction stream.
projects / gcc.git / commitdiff