+2015-11-16 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/arm/arm-cores.def (cortex-a35): New.
+ * config/arm/arm.c (arm_cortex_a35_tune): New.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Regenerate.
+ * config/arm/bpabi.h (BE8_LINK_SPEC): Add cortex-a35.
+ * config/arm/t-aprofile: Likewise.
+ * doc/invoke.texi (-mcpu): Likewise.
+
2015-11-16 Jim Wilson <jim.wilson@linaro.org>
* config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1
ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
/* V8 Architecture Processors */
+ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
EnumValue
Enum(processor_type) String(cortex-a17.cortex-a7) Value(cortexa17cortexa7)
+EnumValue
+Enum(processor_type) String(cortex-a35) Value(cortexa35)
+
EnumValue
Enum(processor_type) String(cortex-a53) Value(cortexa53)
cortexr4f,cortexr5,cortexr7,
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
- cortexa53,cortexa57,cortexa72,
- exynosm1,qdf24xx,xgene1,
- cortexa57cortexa53,cortexa72cortexa53"
+ cortexa35,cortexa53,cortexa57,
+ cortexa72,exynosm1,qdf24xx,
+ xgene1,cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
tune_params::SCHED_AUTOPREF_FULL
};
+const struct tune_params arm_cortex_a35_tune =
+{
+ arm_9e_rtx_costs,
+ &cortexa53_extra_costs,
+ NULL, /* Sched adj cost. */
+ arm_default_branch_cost,
+ &arm_default_vec_cost,
+ 1, /* Constant limit. */
+ 5, /* Max cond insns. */
+ 8, /* Memset max inline. */
+ 1, /* Issue rate. */
+ ARM_PREFETCH_NOT_BENEFICIAL,
+ tune_params::PREF_CONST_POOL_FALSE,
+ tune_params::PREF_LDRD_FALSE,
+ tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
+ tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
+ tune_params::DISPARAGE_FLAGS_NEITHER,
+ tune_params::PREF_NEON_64_FALSE,
+ tune_params::PREF_NEON_STRINGOPS_TRUE,
+ FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
+ tune_params::SCHED_AUTOPREF_OFF
+};
+
const struct tune_params arm_cortex_a53_tune =
{
arm_9e_rtx_costs,
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
|mcpu=marvell-pj4 \
+ |mcpu=cortex-a35 \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
|mcpu=cortex-a12|mcpu=cortex-a17 \
|mcpu=cortex-a15.cortex-a7 \
|mcpu=cortex-a17.cortex-a7 \
+ |mcpu=cortex-a35 \
|mcpu=cortex-a53 \
|mcpu=cortex-a57 \
|mcpu=cortex-a57.cortex-a53 \
MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a17
MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a15.cortex-a7
MULTILIB_MATCHES += march?armv7ve=mcpu?cortex-a17.cortex-a7
+MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a35
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
-@samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
+@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
@samp{cortex-r4},
@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
@samp{cortex-m4},