Minor changes to get new cpu to compile with FULL_SYSTEM.

cpu/beta_cpu/full_cpu.hh:
    Make cpu_id protected rather than private so derived
    classes can access it.
cpu/beta_cpu/regfile.hh:
    Get rid of troublesome debugging statement.

--HG--
extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5

diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/beta_cpu/full_cpu.hh
index a7916f9aecd2e087e953eb58328074ea0a328ba4..42370f1e7891864771c2c41336a8709a6ccb81b5 100644 (file)
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/beta_cpu/full_cpu.hh
@@ -40,7 +40,7 @@ class BaseFullCPU : public BaseCPU
     BaseFullCPU(Params &params);
 #endif // FULL_SYSTEM
 
-  private:
+  protected:
     int cpu_id;
 };
 

diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh
index d7664707d319f3f9ad9a03b0de009b2ef1ef4ad1..b88a33bfb4d0094e02e4865ecf564b3edfaed6fb 100644 (file)
--- a/cpu/beta_cpu/regfile.hh
+++ b/cpu/beta_cpu/regfile.hh
@@ -428,11 +428,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
         break;
 
       case ISA::IPR_IPLR:
-#ifdef DEBUG
-        if (break_ipl != -1 && break_ipl == (val & 0x1f))
-            debug_break();
-#endif
-
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         break;