#ifndef NDEBUG
kernelPanicEvent = addKernelFuncEventOrPanic<BreakPCEvent>("panic");
-#if 0
- kernelDieEvent = addKernelFuncEventOrPanic<BreakPCEvent>("die_if_kernel");
-#endif
-
#endif
/**
/** Event to halt the simulator if the kernel calls panic() */
BreakPCEvent *kernelPanicEvent;
-#if 0
- /** Event to halt the simulator if the kernel calls die_if_kernel */
- BreakPCEvent *kernelDieEvent;
-#endif
-
#endif
/**
0, // 0xbd
"nphalt", // 0xbe
"copypal", // 0xbf
-#if 0
- 0, // 0xc0
- 0, // 0xc1
- 0, // 0xc2
- 0, // 0xc3
- 0, // 0xc4
- 0, // 0xc5
- 0, // 0xc6
- 0, // 0xc7
- 0, // 0xc8
- 0, // 0xc9
- 0, // 0xca
- 0, // 0xcb
- 0, // 0xcc
- 0, // 0xcd
- 0, // 0xce
- 0, // 0xcf
- 0, // 0xd0
- 0, // 0xd1
- 0, // 0xd2
- 0, // 0xd3
- 0, // 0xd4
- 0, // 0xd5
- 0, // 0xd6
- 0, // 0xd7
- 0, // 0xd8
- 0, // 0xd9
- 0, // 0xda
- 0, // 0xdb
- 0, // 0xdc
- 0, // 0xdd
- 0, // 0xde
- 0, // 0xdf
- 0, // 0xe0
- 0, // 0xe1
- 0, // 0xe2
- 0, // 0xe3
- 0, // 0xe4
- 0, // 0xe5
- 0, // 0xe6
- 0, // 0xe7
- 0, // 0xe8
- 0, // 0xe9
- 0, // 0xea
- 0, // 0xeb
- 0, // 0xec
- 0, // 0xed
- 0, // 0xee
- 0, // 0xef
- 0, // 0xf0
- 0, // 0xf1
- 0, // 0xf2
- 0, // 0xf3
- 0, // 0xf4
- 0, // 0xf5
- 0, // 0xf6
- 0, // 0xf7
- 0, // 0xf8
- 0, // 0xf9
- 0, // 0xfa
- 0, // 0xfb
- 0, // 0xfc
- 0, // 0xfd
- 0, // 0xfe
- 0 // 0xff
-#endif
};
if (index > NumCodes || index < 0)
#define pdNil ((pPDR) 0)
#define ipdNil -1
-/*
- * The structure of the runtime procedure descriptor created by the loader
- * for use by the static exception system.
- */
-/*
- * If 0'd out because exception_info chokes Visual C++ and because there
- * don't seem to be any references to this structure elsewhere in gdb.
- */
-#if 0
-typedef struct runtime_pdr {
- coff_addr adr; /* memory address of start of procedure */
- coff_uint regmask; /* save register mask */
- coff_int regoffset; /* save register offset */
- coff_uint fregmask; /* save floating point register mask */
- coff_int fregoffset; /* save floating point register offset */
- coff_int frameoffset; /* frame size */
- coff_ushort framereg; /* frame pointer register */
- coff_ushort pcreg; /* offset or reg of return pc */
- coff_int irpss; /* index into the runtime string table */
- coff_uint reserved;
- struct exception_info *exception_info;/* pointer to exception array */
-} RPDR, *pRPDR;
-#define cbRPDR sizeof(RPDR)
-#define rpdNil ((pRPDR) 0)
-#endif
-
/*
* Line Numbers
*
zero() const
{
return data(0)->zero();
-#if 0
- for (off_type i = 0; i < size(); ++i)
- if (!data(i)->zero())
- return false;
- return true;
-#endif
}
/**
commit.setROB(&rob);
lastActivatedCycle = 0;
-#if 0
- // Give renameMap & rename stage access to the freeList;
- for (ThreadID tid = 0; tid < numThreads; tid++)
- globalSeqNum[tid] = 1;
-#endif
DPRINTF(O3CPU, "Creating O3CPU object.\n");
ThreadID
DefaultFetch<Impl>::branchCount()
{
-#if 0
- list<ThreadID>::iterator thread = activeThreads->begin();
- assert(thread != activeThreads->end());
- ThreadID tid = *thread;
-#endif
-
panic("Branch Count Fetch policy unimplemented\n");
return InvalidThreadID;
}
int
InstructionQueue<Impl>::countInsts()
{
-#if 0
- //ksewell:This works but definitely could use a cleaner write
- //with a more intuitive way of counting. Right now it's
- //just brute force ....
- // Change the #if if you want to use this method.
- int total_insts = 0;
-
- for (ThreadID tid = 0; tid < numThreads; ++tid) {
- ListIt count_it = instList[tid].begin();
-
- while (count_it != instList[tid].end()) {
- if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
- if (!(*count_it)->isIssued()) {
- ++total_insts;
- } else if ((*count_it)->isMemRef() &&
- !(*count_it)->memOpDone) {
- // Loads that have not been marked as executed still count
- // towards the total instructions.
- ++total_insts;
- }
- }
-
- ++count_it;
- }
- }
-
- return total_insts;
-#else
return numEntries - freeEntries;
-#endif
}
template <class Impl>
taken = getPrediction(counter_val);
-#if 0
- // Speculative update.
- if (taken) {
- DPRINTF(Fetch, "Branch updated as taken.\n");
- localCtrs[local_predictor_idx]++;
- } else {
- DPRINTF(Fetch, "Branch updated as not taken.\n");
- localCtrs[local_predictor_idx]--;
- }
-#endif
-
return taken;
}
Addr pteAddr;
Addr dmaAddr;
-#if 0
- DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
- for (int i = 0; i < 4; i++) {
- DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
- i, wsba[i], wsm[i]);
-
- windowBase = wsba[i];
- windowMask = ~wsm[i] & (ULL(0xfff) << 20);
-
- if ((busAddr & windowMask) == (windowBase & windowMask)) {
- DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
- i, windowBase, windowMask, (busAddr & windowMask),
- (windowBase & windowMask));
- }
- }
-#endif
-
for (int i = 0; i < 4; i++) {
windowBase = wsba[i];
CFGR_PCI64_DET);
}
-// all these #if 0's are because i don't THINK the kernel needs to
-// have these implemented. if there is a problem relating to one of
-// these, you may need to add functionality in.
-
-// grouped together and #if 0'ed to avoid empty if body and make clang happy
-#if 0
- if (reg & CFGR_TBI_EN) ;
- if (reg & CFGR_MODE_1000) ;
-
- if (reg & CFGR_PINT_DUPSTS ||
- reg & CFGR_PINT_LNKSTS ||
- reg & CFGR_PINT_SPDSTS)
- ;
-
- if (reg & CFGR_TMRTEST) ;
- if (reg & CFGR_MRM_DIS) ;
- if (reg & CFGR_MWI_DIS) ;
-
- if (reg & CFGR_DATA64_EN) ;
- if (reg & CFGR_M64ADDR) ;
- if (reg & CFGR_PHY_RST) ;
- if (reg & CFGR_PHY_DIS) ;
-
- if (reg & CFGR_REQALG) ;
- if (reg & CFGR_SB) ;
- if (reg & CFGR_POW) ;
- if (reg & CFGR_EXD) ;
- if (reg & CFGR_PESEL) ;
- if (reg & CFGR_BROM_DIS) ;
- if (reg & CFGR_EXT_125) ;
- if (reg & CFGR_BEM) ;
-
- if (reg & CFGR_T64ADDR) ;
- // panic("CFGR_T64ADDR is read only register!\n");
-#endif
if (reg & CFGR_AUTO_1000)
panic("CFGR_AUTO_1000 not implemented!\n");
eepromClk = reg & MEAR_EECLK;
// since phy is completely faked, MEAR_MD* don't matter
-
-// grouped together and #if 0'ed to avoid empty if body and make clang happy
-#if 0
- if (reg & MEAR_MDIO) ;
- if (reg & MEAR_MDDIR) ;
- if (reg & MEAR_MDC) ;
-#endif
break;
case PTSCR:
case TX_CFG:
regs.txcfg = reg;
-#if 0
- if (reg & TX_CFG_CSI) ;
- if (reg & TX_CFG_HBI) ;
- if (reg & TX_CFG_MLB) ;
- if (reg & TX_CFG_ATP) ;
- if (reg & TX_CFG_ECRETRY) {
- /*
- * this could easily be implemented, but considering
- * the network is just a fake pipe, wouldn't make
- * sense to do this
- */
- }
-
- if (reg & TX_CFG_BRST_DIS) ;
-#endif
-
-#if 0
- /* we handle our own DMA, ignore the kernel's exhortations */
- if (reg & TX_CFG_MXDMA) ;
-#endif
// also, we currently don't care about fill/drain
// thresholds though this may change in the future with
case RX_CFG:
regs.rxcfg = reg;
-#if 0
- if (reg & RX_CFG_AEP) ;
- if (reg & RX_CFG_ARP) ;
- if (reg & RX_CFG_STRIPCRC) ;
- if (reg & RX_CFG_RX_RD) ;
- if (reg & RX_CFG_ALP) ;
- if (reg & RX_CFG_AIRL) ;
-
- /* we handle our own DMA, ignore what kernel says about it */
- if (reg & RX_CFG_MXDMA) ;
-
- //also, we currently don't care about fill/drain thresholds
- //though this may change in the future with more realistic
- //networks or a driver which changes it according to feedback
- if (reg & (RX_CFG_DRTH | RX_CFG_DRTH0)) ;
-#endif
break;
case PQCR:
acceptArp = (reg & RFCR_AARP) ? true : false;
multicastHashEnable = (reg & RFCR_MHEN) ? true : false;
-#if 0
- if (reg & RFCR_APAT)
- panic("RFCR_APAT not implemented!\n");
-#endif
if (reg & RFCR_UHEN)
panic("Unicast hash filtering not used by drivers!\n");
regs.tbisr |= (TBISR_MR_AN_COMPLETE | TBISR_MR_LINK_STATUS);
}
-#if 0
- if (reg & TBICR_MR_RESTART_AN) ;
-#endif
-
break;
case TBISR:
regs.tanar |= reg & ~(TANAR_RF1 | TANAR_RF2 | TANAR_UNUSED);
// Pause capability unimplemented
-#if 0
- if (reg & TANAR_PS2) ;
- if (reg & TANAR_PS1) ;
-#endif
-
break;
case TANLPAR:
cmdsts &= 0xffff0000;
cmdsts += rxPacket->length; //i.e. set CMDSTS_SIZE
-#if 0
- /*
- * all the driver uses these are for its own stats keeping
- * which we don't care about, aren't necessary for
- * functionality and doing this would just slow us down.
- * if they end up using this in a later version for
- * functional purposes, just undef
- */
- if (rxFilterEnable) {
- cmdsts &= ~CMDSTS_DEST_MASK;
- const EthAddr &dst = rxFifoFront()->dst();
- if (dst->unicast())
- cmdsts |= CMDSTS_DEST_SELF;
- if (dst->multicast())
- cmdsts |= CMDSTS_DEST_MULTI;
- if (dst->broadcast())
- cmdsts |= CMDSTS_DEST_MASK;
- }
-#endif
-
IpPtr ip(rxPacket);
if (extstsEnable && ip) {
extsts |= EXTSTS_IPPKT;
/** pci settings */
bool ioEnable;
-#if 0
- bool memEnable;
- bool bmEnable;
-#endif
/*** BASIC STRUCTURES FOR TX/RX ***/
/* Data FIFOs */
panic("receive filter not implemented\n");
bool drop = true;
-
-#if 0
- string type;
-
- EthHdr *eth = packet->eth();
- if (eth->unicast()) {
- // If we're accepting all unicast addresses
- if (acceptUnicast)
- drop = false;
-
- // If we make a perfect match
- if (acceptPerfect && params->eaddr == eth.dst())
- drop = false;
-
- if (acceptArp && eth->type() == ETH_TYPE_ARP)
- drop = false;
-
- } else if (eth->broadcast()) {
- // if we're accepting broadcasts
- if (acceptBroadcast)
- drop = false;
-
- } else if (eth->multicast()) {
- // if we're accepting all multicasts
- if (acceptMulticast)
- drop = false;
-
- }
-
- if (drop) {
- DPRINTF(Ethernet, "rxFilter drop\n");
- DDUMP(EthernetData, packet->data, packet->length);
- }
-#endif
return drop;
}
SimpleDisk::write(Addr addr, baddr_t block, int count)
{
panic("unimplemented!\n");
-
-#if 0
- uint8_t *data = physmem->dma_addr(addr, count);
- if (!data)
- panic("dma out of range! write addr=%#x count=%d\n", addr, count);
-
- image->write(data, block, count);
-#endif
}
SimpleDisk *
*/
setMask = numSets - 1;
- #if 0
- // GpuTLB doesn't yet support full system
- walker = p->walker;
- walker->setTLB(this);
- #endif
-
maxCoalescedReqs = p->maxOutstandingReqs;
// Do not allow maxCoalescedReqs to be more than the TLB associativity
case 'n':
case 'N': {
args += 2;
-#if 0
- uint64_t n = (uint64_t)args++;
- struct reg_values *rv = (struct reg_values *)args++;
-#endif
}
break;
case 'r':
case 'R': {
args += 2;
-#if 0
- uint64_t n = (uint64_t)args++;
- struct reg_desc *rd = (struct reg_desc *)args++;
-#endif
}
break;
case '%':
overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
}
-#if 0
- // MSHR access formulas
- for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
- MemCmd cmd(access_idx);
- const string &cstr = cmd.toString();
-
- mshrAccesses[access_idx]
- .name(name() + "." + cstr + "_mshr_accesses")
- .desc("number of " + cstr + " mshr accesses(hits+misses)")
- .flags(total | nozero | nonan)
- ;
- mshrAccesses[access_idx] =
- mshr_hits[access_idx] + mshr_misses[access_idx]
- + mshr_uncacheable[access_idx];
- }
-
- demandMshrAccesses
- .name(name() + ".demand_mshr_accesses")
- .desc("number of demand (read+write) mshr accesses")
- .flags(total | nozero | nonan)
- ;
- demandMshrAccesses = demandMshrHits + demandMshrMisses;
-
- overallMshrAccesses
- .name(name() + ".overall_mshr_accesses")
- .desc("number of overall (read+write) mshr accesses")
- .flags(total | nozero | nonan)
- ;
- overallMshrAccesses = overallMshrHits + overallMshrMisses
- + overallMshrUncacheable;
-#endif
-
// MSHR miss rate formulas
for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
MemCmd cmd(access_idx);
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrUncacheableLatency;
-#if 0
- /** The total number of MSHR accesses per command and thread. */
- Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
- /** The total number of demand MSHR accesses. */
- Stats::Formula demandMshrAccesses;
- /** The total number of MSHR accesses. */
- Stats::Formula overallMshrAccesses;
-#endif
-
/** The miss rate in the MSHRs pre command and thread. */
Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
/** The demand miss rate in the MSHRs. */
void
GPUCoalescer::checkCoherence(Addr addr)
{
-#ifdef CHECK_COHERENCE
- m_ruby_system->checkGlobalCoherenceInvariant(addr);
-#endif
}
void
return true;
}
-#ifdef CHECK_COHERENCE
-// This code will check for cases if the given cache block is exclusive in
-// one node and shared in another-- a coherence violation
-//
-// To use, the SLICC specification must call sequencer.checkCoherence(address)
-// when the controller changes to a state with new permissions. Do this
-// in setState. The SLICC spec must also define methods "isBlockShared"
-// and "isBlockExclusive" that are specific to that protocol
-//
-void
-RubySystem::checkGlobalCoherenceInvariant(const Address& addr)
-{
-#if 0
- NodeID exclusive = -1;
- bool sharedDetected = false;
- NodeID lastShared = -1;
-
- for (int i = 0; i < m_chip_vector.size(); i++) {
- if (m_chip_vector[i]->isBlockExclusive(addr)) {
- if (exclusive != -1) {
- // coherence violation
- WARN_EXPR(exclusive);
- WARN_EXPR(m_chip_vector[i]->getID());
- WARN_EXPR(addr);
- WARN_EXPR(getTime());
- ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
- } else if (sharedDetected) {
- WARN_EXPR(lastShared);
- WARN_EXPR(m_chip_vector[i]->getID());
- WARN_EXPR(addr);
- WARN_EXPR(getTime());
- ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
- } else {
- exclusive = m_chip_vector[i]->getID();
- }
- } else if (m_chip_vector[i]->isBlockShared(addr)) {
- sharedDetected = true;
- lastShared = m_chip_vector[i]->getID();
-
- if (exclusive != -1) {
- WARN_EXPR(lastShared);
- WARN_EXPR(exclusive);
- WARN_EXPR(addr);
- WARN_EXPR(getTime());
- ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
- }
- }
- }
-#endif
-}
-#endif
-
RubySystem *
RubySystemParams::create()
{
void
Sequencer::checkCoherence(Addr addr)
{
-#ifdef CHECK_COHERENCE
- m_ruby_system->checkGlobalCoherenceInvariant(addr);
-#endif
}
void
*/
warn("Checkpoints for file descriptors currently do not work.");
-#if 0
- for (int x = 0; x < fds->getSize(); x++)
- (*fds)[x].serializeSection(cp, csprintf("FDEntry%d", x));
-#endif
-
}
void
* come back and fix them at a later date.
*/
warn("Checkpoints for file descriptors currently do not work.");
-#if 0
- for (int x = 0; x < fds->getSize(); x++)
- (*fds)[x]->unserializeSection(cp, csprintf("FDEntry%d", x));
- fds->restoreFileOffsets();
-#endif
// The above returns a bool so that you could do something if you don't
// find the param in the checkpoint if you wanted to, like set a default
// but in this case we'll just stick with the instantiated value if not
projects / gem5.git / commitdiff