platforms/genesys2: add eth clock timing constraint

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 0a454ab86c0a74dd09b0ebc958ffc23257217036..89f721205fcdd20292d94e417dd36c5e9be3ad2c 100644 (file)
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -117,3 +117,7 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+        except ConstraintError:
+            pass