if (pm.blacklist_cells.count(pm.st.shiftx))
return;
SigSpec A = pm.st.shiftx->getPort("\\A");
- SigSpec B = pm.st.shiftx->getPort("\\B");
+ SigSpec B = pm.st.shiftxB;
+ log_assert(!B.empty());
SigSpec Y = pm.st.shiftx->getPort("\\Y");
const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
- const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int();
+ const int B_WIDTH = GetSize(pm.st.shiftxB);
const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
int trailing_zeroes = 0;
for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;
endmatch
code shiftxB
+ shiftxB = port(shiftx, \B);
+
if (macc) {
- shiftxB = port(shiftx, \B);
const int b_width = param(shiftx, \B_WIDTH).as_int();
if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
shiftxB = shiftxB.extract(0, b_width-1);
+
if (port(macc, \Y) != shiftxB) {
blacklist(shiftx);
reject;