Actually use pm.st.shiftxB
authorEddie Hung <eddie@fpgeh.com>
Fri, 26 Apr 2019 02:59:33 +0000 (19:59 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 26 Apr 2019 02:59:33 +0000 (19:59 -0700)
passes/pmgen/split_shiftx.cc
passes/pmgen/split_shiftx.pmg

index 2af0ebecfac8200442efe5ccc9338d15bb6c8b21..3cbabcd76ac425ef812907a6fbcef9922e14133a 100644 (file)
@@ -30,10 +30,11 @@ void create_split_shiftx(split_shiftx_pm &pm)
        if (pm.blacklist_cells.count(pm.st.shiftx))
                return;
        SigSpec A = pm.st.shiftx->getPort("\\A");
-       SigSpec B = pm.st.shiftx->getPort("\\B");
+       SigSpec B = pm.st.shiftxB;
+       log_assert(!B.empty());
        SigSpec Y = pm.st.shiftx->getPort("\\Y");
        const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
-       const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int();
+       const int B_WIDTH = GetSize(pm.st.shiftxB);
        const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
        int trailing_zeroes = 0;
        for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;
index c9e0ff995d166983ec6c6d96f7e8e2716da632a6..3aafe1975f62fa1a8ab5263c8704665a4afa894d 100644 (file)
@@ -12,11 +12,13 @@ match macc
 endmatch
 
 code shiftxB
+       shiftxB = port(shiftx, \B);
+
        if (macc) {
-               shiftxB = port(shiftx, \B);
                const int b_width = param(shiftx, \B_WIDTH).as_int();
                if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
                        shiftxB = shiftxB.extract(0, b_width-1);
+
                if (port(macc, \Y) != shiftxB) {
                        blacklist(shiftx);
                        reject;