input rst;
endmodule
-(* abc9_box_id=1, whitebox *)
+(* abc9_box, blackbox *)
module MUXF8(input I0, I1, S, output O);
+specify
+ (I0 => O) = 0;
+ (I1 => O) = 0;
+ (S => O) = 0;
+endspecify
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
synth -run coarse; \
opt -full; \
techmap; \
- abc9 -lut 4 -box ../abc.box; \
+ abc9 -lut 4; \
clean; \
check -assert; \
select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
- setattr -mod -unset whitebox'"
+ setattr -mod -unset blackbox'"