Allow whitebox modules to be overwritten

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 943466ee3d134ad59e940ab510ea6448dcf101da..c8ca6d1640855616bd70b0940e0f8a9c22575270 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1172,7 +1172,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 
                        if (design->has((*it)->str)) {
                                RTLIL::Module *existing_mod = design->module((*it)->str);
-                               if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+                               if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
                                        log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str());
                                } else if (nooverwrite) {
                                        log("Ignoring re-definition of module `%s' at %s:%d.\n",

diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
index 7e928ec781b2376f1548c70409e7507d510c2376..ddb80b700d00c400f79f88f327ac8c7caa0a2dd7 100644 (file)
--- a/techlibs/ice40/tests/test_arith.ys
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -8,8 +8,6 @@ rename test gold
 miter -equiv -flatten -make_outputs gold gate miter
 sat -verify -prove trigger 0 -show-ports miter
 
-delete A:whitebox # Necessary since whiteboxes cannot
-                  # be overwritten...
 synth_ice40 -top gate
 
 read_verilog test_arith.v