vc4: Fix register class handling of DDX/DDY arguments.

I had this exactly backwards, but apparently the piglit tests were all
landing in r0-r3 anyway.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>

diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c
index 6c99b054e9f2224a1292d1654ff5041bdf0503db..ab343ee3134409ba9603b18790cf41a5136d6113 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_register_allocate.c
+++ b/src/gallium/drivers/vc4/vc4_register_allocate.c
@@ -247,7 +247,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
 
                 case QOP_ROT_MUL:
                         assert(inst->src[0].file == QFILE_TEMP);
-                        class_bits[inst->src[0].index] &= ~CLASS_BIT_R0_R3;
+                        class_bits[inst->src[0].index] &= CLASS_BIT_R0_R3;
                         break;
 
                 default: